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Moved busreset in uhci_init up to avoid clearing of FLBASE in Via 83572
(PR1)
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parent
327f4e8394
commit
e99cd85d69
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=44125
@ -314,6 +314,9 @@ uhci_init(sc)
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uhci_run(sc, 0); /* stop the controller */
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UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */
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/* PR1 The VIA 823C572 reset FLBASEADDR as well */
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uhci_busreset(sc);
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/* Allocate and initialize real frame array. */
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r = usb_allocmem(sc->sc_dmatag,
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UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t),
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@ -324,18 +327,12 @@ uhci_init(sc)
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UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */
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UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&dma)); /* set frame list */
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/* PR1 moved uhci_busreset up */
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#ifdef USB_DEBUG
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/* PR1 */
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if ( UREAD4(sc, UHCI_FLBASEADDR) != DMAADDR(&dma) )
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printf("PR1:before busreset: FLBASEADDR = 0x%08x != DMADDR(&dma) = 0x%08x\n",
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UREAD4(sc, UHCI_FLBASEADDR), DMAADDR(&dma));
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#endif
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uhci_busreset(sc);
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#ifdef USB_DEBUG
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/* PR1 */
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if ( UREAD4(sc, UHCI_FLBASEADDR) != DMAADDR(&dma) )
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printf("PR1:after busreset: FLBASEADDR = 0x%08x != DMADDR(&dma) = 0x%08x\n",
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UREAD4(sc, UHCI_FLBASEADDR), DMAADDR(&dma));
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printf("PR1:after busreset: FLBASEADDR=0x%08x, DMADDR(&dma)=0x%08x\n",
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UREAD4(sc, UHCI_FLBASEADDR), DMAADDR(&dma));
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#endif
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/* Allocate the dummy QH where bulk traffic will be queued. */
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bsqh = uhci_alloc_sqh(sc);
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@ -888,7 +885,7 @@ uhci_waitintr(sc, reqh)
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int usecs;
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uhci_intr_info_t *ii;
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DPRINTFN(10,("uhci_waitintr: timeout = %ds\n", timo));
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DPRINTFN(15,("uhci_waitintr: timeout = %ds\n", timo));
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reqh->status = USBD_IN_PROGRESS;
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for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) {
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