mirror of
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Remove EISA attachment (fea) from pdq driver. Remove vestiges of
TurboChannel and Q-Bus support while I'm here. Remove obsolete diagnostics from man page.
This commit is contained in:
parent
3fb3ab7f1c
commit
f08a6f5946
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=313834
@ -634,7 +634,6 @@ MLINKS+=fd.4 stderr.4 \
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fd.4 stdout.4
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MLINKS+=fdt.4 FDT.4
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MLINKS+=firewire.4 ieee1394.4
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MLINKS+=fpa.4 fea.4
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MLINKS+=fwe.4 if_fwe.4
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MLINKS+=fwip.4 if_fwip.4
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MLINKS+=fxp.4 if_fxp.4
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@ -4,16 +4,14 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd March 13, 1995
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.Dd February 15, 2017
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.Dt FPA 4
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.Os
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.Sh NAME
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.Nm fpa ,
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.Nm fea
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.Nm fpa
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.Nd device drivers for DEC FDDI controllers
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.Sh SYNOPSIS
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.Cd "device fpa"
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.Cd "device fea"
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.Pp
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.Fx
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only:
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@ -21,25 +19,9 @@ only:
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.Sh DESCRIPTION
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The
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.Nm
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and
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.Nm fea
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device drivers provide support for the DEC DEFPA PCI FDDI Controller and
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the DEC DEFEA EISA FDDI Controller, respectively.
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All variants of either
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device driver provide support for the DEC DEFPA PCI FDDI Controller.
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All variants of the
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controller are supported including the DAS and SAS configurations.
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.Sh DIAGNOSTICS
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.Bl -diag
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.It "fea%d: error: desired IRQ of %d does not match device's actual IRQ (%d)"
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The device probe detected that the DEFEA board is configured for a different
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interrupt than the one specified in the kernel configuration file.
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.It "fea%d: error: memory not enabled! ECU reconfiguration required"
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The device probe found that no device memory had been configured on the
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DEFEA.
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Although the DEFEA can be configured with no device memory, this driver
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requires a minimum of 1K device memory to be set up.
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The ECU (EISA Configuration
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Utility) will need to be run to change the settings.
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.El
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.Sh SEE ALSO
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.Xr arp 4 ,
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.Xr netintro 4 ,
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@ -47,9 +29,7 @@ Utility) will need to be run to change the settings.
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.Sh AUTHORS
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The
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.Nm
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and
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.Nm fea
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device drivers and this manual page were written by
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device driver and this manual page were written by
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.An Matt Thomas .
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.Sh CAVEATS
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Normally, the device driver will not enable the reception of SMT frames.
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@ -1974,7 +1974,6 @@ device xmphy # XaQti XMAC II
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# ex: Intel EtherExpress Pro/10 and other i82595-based adapters,
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# Olicom Ethernet PC Card devices.
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# fe: Fujitsu MB86960A/MB86965A Ethernet
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# fea: DEC DEFEA EISA FDDI adapter
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# fpa: Support for the Digital DEFPA PCI FDDI. `device fddi' is also needed.
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# fxp: Intel EtherExpress Pro/100B
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# (hint of prefer_iomap can be done to prefer I/O instead of Mem mapping)
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@ -2087,7 +2086,6 @@ device ex
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device fe
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hint.fe.0.at="isa"
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hint.fe.0.port="0x300"
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device fea
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device sn
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hint.sn.0.at="isa"
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hint.sn.0.port="0x300"
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@ -2409,10 +2409,9 @@ dev/pci/pcib_if.m standard
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dev/pci/pcib_support.c standard
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dev/pci/vga_pci.c optional pci
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dev/pcn/if_pcn.c optional pcn pci
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dev/pdq/if_fea.c optional fea eisa
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dev/pdq/if_fpa.c optional fpa pci
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dev/pdq/pdq.c optional nowerror fea eisa | fpa pci
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dev/pdq/pdq_ifsubr.c optional nowerror fea eisa | fpa pci
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dev/pdq/pdq.c optional nowerror fpa pci
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dev/pdq/pdq_ifsubr.c optional nowerror fpa pci
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dev/pms/freebsd/driver/ini/src/agtiapi.c optional pmspcv \
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compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w"
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dev/pms/RefTisa/sallsdk/spc/sadisc.c optional pmspcv \
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@ -1,286 +0,0 @@
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/*-
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* Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* DEC PDQ FDDI Controller
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*
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* This module support the DEFEA EISA FDDI Controller.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/lock.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_media.h>
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#include <net/fddi.h>
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#include <dev/eisa/eisaconf.h>
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#include <dev/pdq/pdq_freebsd.h>
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#include <dev/pdq/pdqreg.h>
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static void pdq_eisa_subprobe (pdq_bus_t, u_int32_t, u_int32_t *, u_int32_t *, u_int32_t *);
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static void pdq_eisa_devinit (pdq_softc_t *);
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static const char * pdq_eisa_match (eisa_id_t);
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static int pdq_eisa_probe (device_t);
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static int pdq_eisa_attach (device_t);
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static int pdq_eisa_detach (device_t);
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static int pdq_eisa_shutdown (device_t);
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static void pdq_eisa_ifintr (void *);
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#define DEFEA_IRQS 0x0000FBA9U
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#define DEFEA_INTRENABLE 0x8 /* level interrupt */
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#define DEFEA_DECODE_IRQ(n) ((DEFEA_IRQS >> ((n) << 2)) & 0x0f)
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#define EISA_DEVICE_ID_DEC_DEC3001 0x10a33001
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#define EISA_DEVICE_ID_DEC_DEC3002 0x10a33002
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#define EISA_DEVICE_ID_DEC_DEC3003 0x10a33003
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#define EISA_DEVICE_ID_DEC_DEC3004 0x10a33004
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static void
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pdq_eisa_subprobe(bc, iobase, maddr, msize, irq)
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pdq_bus_t bc;
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u_int32_t iobase;
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u_int32_t *maddr;
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u_int32_t *msize;
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u_int32_t *irq;
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{
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if (irq != NULL)
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*irq = DEFEA_DECODE_IRQ(PDQ_OS_IORD_8(bc, iobase, PDQ_EISA_IO_CONFIG_STAT_0) & 3);
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*maddr = (PDQ_OS_IORD_8(bc, iobase, PDQ_EISA_MEM_ADD_CMP_0) << 8)
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| (PDQ_OS_IORD_8(bc, iobase, PDQ_EISA_MEM_ADD_CMP_1) << 16);
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*msize = (PDQ_OS_IORD_8(bc, iobase, PDQ_EISA_MEM_ADD_MASK_0) + 4) << 8;
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return;
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}
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static void
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pdq_eisa_devinit (sc)
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pdq_softc_t *sc;
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{
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pdq_uint8_t data;
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/*
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* Do the standard initialization for the DEFEA registers.
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*/
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PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_FUNCTION_CTRL, 0x23);
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PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_IO_CMP_1_1, (sc->io_bsh >> 8) & 0xF0);
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PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_IO_CMP_0_1, (sc->io_bsh >> 8) & 0xF0);
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PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_SLOT_CTRL, 0x01);
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data = PDQ_OS_IORD_8(sc->io_bst, sc->io_bsh, PDQ_EISA_BURST_HOLDOFF);
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#if defined(PDQ_IOMAPPED)
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PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_BURST_HOLDOFF, data & ~1);
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#else
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PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_BURST_HOLDOFF, data | 1);
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#endif
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data = PDQ_OS_IORD_8(sc->io_bst, sc->io_bsh, PDQ_EISA_IO_CONFIG_STAT_0);
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PDQ_OS_IOWR_8(sc->io_bst, sc->io_bsh, PDQ_EISA_IO_CONFIG_STAT_0, data | DEFEA_INTRENABLE);
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return;
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}
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static const char *
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pdq_eisa_match (type)
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eisa_id_t type;
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{
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switch (type) {
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case EISA_DEVICE_ID_DEC_DEC3001:
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case EISA_DEVICE_ID_DEC_DEC3002:
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case EISA_DEVICE_ID_DEC_DEC3003:
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case EISA_DEVICE_ID_DEC_DEC3004:
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return ("DEC FDDIcontroller/EISA Adapter");
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break;
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default:
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break;
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}
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return (NULL);
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}
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static int
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pdq_eisa_probe (dev)
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device_t dev;
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{
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const char *desc;
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u_int32_t iobase;
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u_int32_t irq;
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u_int32_t maddr;
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u_int32_t msize;
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u_int32_t eisa_id = eisa_get_id(dev);
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desc = pdq_eisa_match(eisa_id);
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if (!desc) {
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return (ENXIO);
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}
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device_set_desc(dev, desc);
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iobase = eisa_get_slot(dev) * EISA_SLOT_SIZE;
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pdq_eisa_subprobe((pdq_bus_t)SYS_RES_IOPORT, iobase, &maddr, &msize, &irq);
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eisa_add_iospace(dev, iobase, 0x200, RESVADDR_NONE);
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eisa_add_mspace(dev, maddr, msize, RESVADDR_NONE);
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eisa_add_intr(dev, irq, EISA_TRIGGER_LEVEL);
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return (0);
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}
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static void
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pdq_eisa_ifintr(arg)
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void * arg;
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{
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pdq_softc_t * sc;
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sc = arg;
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PDQ_LOCK(sc);
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(void) pdq_interrupt(sc->sc_pdq);
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PDQ_LOCK(sc);
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return;
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}
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static int
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pdq_eisa_attach (dev)
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device_t dev;
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{
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pdq_softc_t * sc;
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int error;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->io_rid = 0;
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sc->io_type = SYS_RES_IOPORT;
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sc->io = bus_alloc_resource_any(dev, sc->io_type, &sc->io_rid,
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RF_ACTIVE);
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if (!sc->io) {
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device_printf(dev, "Unable to allocate I/O space resource.\n");
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error = ENXIO;
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goto bad;
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}
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sc->io_bsh = rman_get_bushandle(sc->io);
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sc->io_bst = rman_get_bustag(sc->io);
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sc->mem_rid = 0;
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sc->mem_type = SYS_RES_MEMORY;
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sc->mem = bus_alloc_resource_any(dev, sc->mem_type, &sc->mem_rid,
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RF_ACTIVE);
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if (!sc->mem) {
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device_printf(dev, "Unable to allocate memory resource.\n");
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error = ENXIO;
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goto bad;
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}
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sc->mem_bsh = rman_get_bushandle(sc->mem);
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sc->mem_bst = rman_get_bustag(sc->mem);
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sc->irq_rid = 0;
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sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
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RF_SHAREABLE | RF_ACTIVE);
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if (!sc->irq) {
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device_printf(dev, "Unable to allocate interrupt resource.\n");
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error = ENXIO;
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goto bad;
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}
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pdq_eisa_devinit(sc);
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error = pdq_ifattach(sc, sc->sc_pdq->pdq_hwaddr.lanaddr_bytes,
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PDQ_DEFEA);
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if (error)
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goto bad;
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error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
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NULL, pdq_eisa_ifintr, sc, &sc->irq_ih);
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if (error) {
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device_printf(dev, "Failed to setup interrupt handler.\n");
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pdq_ifdetach(sc);
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return (error);
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}
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return (0);
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bad:
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pdq_free(dev);
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return (error);
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}
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static int
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pdq_eisa_detach (dev)
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device_t dev;
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{
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pdq_softc_t * sc;
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sc = device_get_softc(dev);
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pdq_ifdetach(sc);
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return (0);
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}
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static int
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pdq_eisa_shutdown(dev)
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device_t dev;
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{
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pdq_softc_t * sc;
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sc = device_get_softc(dev);
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PDQ_LOCK(sc);
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pdq_hwreset(sc->sc_pdq);
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PDQ_UNLOCK(sc);
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return (0);
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}
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static device_method_t pdq_eisa_methods[] = {
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DEVMETHOD(device_probe, pdq_eisa_probe),
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DEVMETHOD(device_attach, pdq_eisa_attach),
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DEVMETHOD(device_attach, pdq_eisa_detach),
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DEVMETHOD(device_shutdown, pdq_eisa_shutdown),
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{ 0, 0 }
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};
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static driver_t pdq_eisa_driver = {
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"fea",
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pdq_eisa_methods,
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sizeof(pdq_softc_t),
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};
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DRIVER_MODULE(fea, eisa, pdq_eisa_driver, pdq_devclass, 0, 0);
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/* MODULE_DEPEND(fea, eisa, 1, 1, 1); */
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MODULE_DEPEND(fea, fddi, 1, 1, 1);
|
@ -163,10 +163,6 @@ static const char * const * const pdq_pmd_types[] = {
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static const char * const pdq_descriptions[] = {
|
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"DEFPA PCI",
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"DEFEA EISA",
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"DEFTA TC",
|
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"DEFAA Futurebus",
|
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"DEFQA Q-bus",
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};
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static void
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@ -1088,8 +1084,7 @@ pdq_hwreset(
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state = PDQ_PSTS_ADAPTER_STATE(PDQ_CSR_READ(csrs, csr_port_status));
|
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if (state == PDQS_DMA_UNAVAILABLE)
|
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return;
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PDQ_CSR_WRITE(csrs, csr_port_data_a,
|
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(state == PDQS_HALTED && pdq->pdq_type != PDQ_DEFTA) ? 0 : PDQ_PRESET_SKIP_SELFTEST);
|
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PDQ_CSR_WRITE(csrs, csr_port_data_a, PDQ_PRESET_SKIP_SELFTEST);
|
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PDQ_CSR_WRITE(csrs, csr_port_reset, 1);
|
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PDQ_OS_USEC_DELAY(100);
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PDQ_CSR_WRITE(csrs, csr_port_reset, 0);
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@ -1164,13 +1159,11 @@ pdq_stop(
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pdq_read_fwrev(&pdq->pdq_csrs, &pdq->pdq_fwrev);
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pdq->pdq_chip_rev = pdq_read_chiprev(&pdq->pdq_csrs);
|
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|
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if (pdq->pdq_type == PDQ_DEFPA) {
|
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/*
|
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* Disable interrupts and DMA.
|
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*/
|
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PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_mode_control, 0);
|
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PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_status, 0x10);
|
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}
|
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/*
|
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* Disable interrupts and DMA.
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*/
|
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PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_mode_control, 0);
|
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PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_status, 0x10);
|
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|
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/*
|
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* Flush all the databuf queues.
|
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@ -1229,27 +1222,21 @@ pdq_stop(
|
||||
* Allow the DEFPA to do DMA. Then program the physical
|
||||
* addresses of the consumer and descriptor blocks.
|
||||
*/
|
||||
if (pdq->pdq_type == PDQ_DEFPA) {
|
||||
#ifdef PDQTEST
|
||||
PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_mode_control,
|
||||
PDQ_PFI_MODE_DMA_ENABLE);
|
||||
PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_mode_control,
|
||||
PDQ_PFI_MODE_DMA_ENABLE);
|
||||
#else
|
||||
PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_mode_control,
|
||||
PDQ_PFI_MODE_DMA_ENABLE
|
||||
/*|PDQ_PFI_MODE_PFI_PCI_INTR*/|PDQ_PFI_MODE_PDQ_PCI_INTR);
|
||||
PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_mode_control,
|
||||
PDQ_PFI_MODE_DMA_ENABLE
|
||||
/*|PDQ_PFI_MODE_PFI_PCI_INTR*/|PDQ_PFI_MODE_PDQ_PCI_INTR);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Make sure the unsolicited queue has events ...
|
||||
*/
|
||||
pdq_process_unsolicited_events(pdq);
|
||||
|
||||
if ((pdq->pdq_type == PDQ_DEFEA && pdq->pdq_chip_rev == PDQ_CHIP_REV_E)
|
||||
|| pdq->pdq_type == PDQ_DEFTA)
|
||||
PDQ_CSR_WRITE(csrs, csr_port_data_b, PDQ_DMA_BURST_16LW);
|
||||
else
|
||||
PDQ_CSR_WRITE(csrs, csr_port_data_b, PDQ_DMA_BURST_8LW);
|
||||
PDQ_CSR_WRITE(csrs, csr_port_data_b, PDQ_DMA_BURST_8LW);
|
||||
PDQ_CSR_WRITE(csrs, csr_port_data_a, PDQ_SUB_CMD_DMA_BURST_SIZE_SET);
|
||||
pdq_do_port_control(csrs, PDQ_PCTL_SUB_CMD);
|
||||
|
||||
@ -1408,8 +1395,7 @@ pdq_interrupt(
|
||||
pdq_uint32_t data;
|
||||
int progress = 0;
|
||||
|
||||
if (pdq->pdq_type == PDQ_DEFPA)
|
||||
PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_status, 0x18);
|
||||
PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_status, 0x18);
|
||||
|
||||
while ((data = PDQ_CSR_READ(csrs, csr_port_status)) & PDQ_PSTS_INTR_PENDING) {
|
||||
progress = 1;
|
||||
@ -1454,7 +1440,7 @@ pdq_interrupt(
|
||||
pdq_halt_code_t halt_code = PDQ_PSTS_HALT_ID(PDQ_CSR_READ(csrs, csr_port_status));
|
||||
printf(": halt code = %d (%s)\n",
|
||||
halt_code, pdq_halt_codes[halt_code]);
|
||||
if (halt_code == PDQH_DMA_ERROR && pdq->pdq_type == PDQ_DEFPA) {
|
||||
if (halt_code == PDQH_DMA_ERROR) {
|
||||
PDQ_PRINTF(("\tPFI status = 0x%x, Host 0 Fatal Interrupt = 0x%x\n",
|
||||
PDQ_CSR_READ(&pdq->pdq_pci_csrs, csr_pfi_status),
|
||||
data & PDQ_HOST_INT_FATAL_ERROR));
|
||||
@ -1503,8 +1489,7 @@ pdq_interrupt(
|
||||
PDQ_CSR_WRITE(csrs, csr_host_int_type_0, PDQ_HOST_INT_XMT_DATA_FLUSH);
|
||||
}
|
||||
}
|
||||
if (pdq->pdq_type == PDQ_DEFPA)
|
||||
PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_status, 0x18);
|
||||
PDQ_CSR_WRITE(&pdq->pdq_pci_csrs, csr_pfi_status, 0x18);
|
||||
}
|
||||
return progress;
|
||||
}
|
||||
@ -1639,9 +1624,8 @@ pdq_initialize(
|
||||
* Initialize the CSR references.
|
||||
* the DEFAA (FutureBus+) skips a longword between registers
|
||||
*/
|
||||
pdq_init_csrs(&pdq->pdq_csrs, bus, csr_base, pdq->pdq_type == PDQ_DEFAA ? 2 : 1);
|
||||
if (pdq->pdq_type == PDQ_DEFPA)
|
||||
pdq_init_pci_csrs(&pdq->pdq_pci_csrs, bus, csr_base, 1);
|
||||
pdq_init_csrs(&pdq->pdq_csrs, bus, csr_base, 1);
|
||||
pdq_init_pci_csrs(&pdq->pdq_pci_csrs, bus, csr_base, 1);
|
||||
|
||||
PDQ_PRINTF(("PDQ CSRs: BASE = " PDQ_OS_CSR_FMT "\n", pdq->pdq_csrs.csr_base));
|
||||
PDQ_PRINTF((" Port Reset = " PDQ_OS_CSR_FMT " [0x%08x]\n",
|
||||
@ -1774,7 +1758,7 @@ pdq_initialize(
|
||||
if (state == PDQS_HALTED) {
|
||||
pdq_halt_code_t halt_code = PDQ_PSTS_HALT_ID(PDQ_CSR_READ(&pdq->pdq_csrs, csr_port_status));
|
||||
printf("Halt code = %d (%s)\n", halt_code, pdq_halt_codes[halt_code]);
|
||||
if (halt_code == PDQH_DMA_ERROR && pdq->pdq_type == PDQ_DEFPA)
|
||||
if (halt_code == PDQH_DMA_ERROR)
|
||||
PDQ_PRINTF(("PFI status = 0x%x, Host 0 Fatal Interrupt = 0x%x\n",
|
||||
PDQ_CSR_READ(&pdq->pdq_pci_csrs, csr_pfi_status),
|
||||
PDQ_CSR_READ(&pdq->pdq_csrs, csr_host_int_type_0) & PDQ_HOST_INT_FATAL_ERROR));
|
||||
|
@ -86,10 +86,6 @@ extern devclass_t pdq_devclass;
|
||||
|
||||
enum _pdq_type_t {
|
||||
PDQ_DEFPA, /* PCI-bus */
|
||||
PDQ_DEFEA, /* EISA-bus */
|
||||
PDQ_DEFTA, /* TurboChannel */
|
||||
PDQ_DEFAA, /* FutureBus+ */
|
||||
PDQ_DEFQA /* Q-bus */
|
||||
};
|
||||
|
||||
#define sc_ifmedia ifmedia
|
||||
|
@ -459,6 +459,8 @@ pdq_ifattach(pdq_softc_t *sc, const pdq_uint8_t *llc, pdq_type_t type)
|
||||
{
|
||||
struct ifnet *ifp;
|
||||
|
||||
KASSERT(type == PDQ_DEFPA, ("We only support PCI attachment."));
|
||||
|
||||
ifp = PDQ_IFNET(sc) = if_alloc(IFT_FDDI);
|
||||
if (ifp == NULL) {
|
||||
device_printf(sc->dev, "can not if_alloc()\n");
|
||||
|
@ -127,52 +127,6 @@ struct _pdq_pci_csrs_t {
|
||||
#define PDQ_PFI_STATUS_PDQ_INTR 0x10 /* PDQ Int received */
|
||||
#define PDQ_PFI_STATUS_DMA_ABORT 0x08 /* PDQ DMA Abort asserted */
|
||||
|
||||
#define PDQ_EISA_BURST_HOLDOFF 0x0040
|
||||
#define PDQ_EISA_SLOT_ID 0x0C80
|
||||
#define PDQ_EISA_SLOT_CTRL 0x0C84
|
||||
#define PDQ_EISA_MEM_ADD_CMP_0 0x0C85
|
||||
#define PDQ_EISA_MEM_ADD_CMP_1 0x0C86
|
||||
#define PDQ_EISA_MEM_ADD_CMP_2 0x0C87
|
||||
#define PDQ_EISA_MEM_ADD_HI_CMP_0 0x0C88
|
||||
#define PDQ_EISA_MEM_ADD_HI_CMP_1 0x0C89
|
||||
#define PDQ_EISA_MEM_ADD_HI_CMP_2 0x0C8A
|
||||
#define PDQ_EISA_MEM_ADD_MASK_0 0x0C8B
|
||||
#define PDQ_EISA_MEM_ADD_MASK_1 0x0C8C
|
||||
#define PDQ_EISA_MEM_ADD_MASK_2 0x0C8D
|
||||
#define PDQ_EISA_MEM_ADD_LO_CMP_0 0x0C8E
|
||||
#define PDQ_EISA_MEM_ADD_LO_CMP_1 0x0C8F
|
||||
#define PDQ_EISA_MEM_ADD_LO_CMP_2 0x0C90
|
||||
#define PDQ_EISA_IO_CMP_0_0 0x0C91
|
||||
#define PDQ_EISA_IO_CMP_0_1 0x0C92
|
||||
#define PDQ_EISA_IO_CMP_1_0 0x0C93
|
||||
#define PDQ_EISA_IO_CMP_1_1 0x0C94
|
||||
#define PDQ_EISA_IO_CMP_2_0 0x0C95
|
||||
#define PDQ_EISA_IO_CMP_2_1 0x0C96
|
||||
#define PDQ_EISA_IO_CMP_3_0 0x0C97
|
||||
#define PDQ_EISA_IO_CMP_3_1 0x0C98
|
||||
#define PDQ_EISA_IO_ADD_MASK_0_0 0x0C99
|
||||
#define PDQ_EISA_IO_ADD_MASK_0_1 0x0C9A
|
||||
#define PDQ_EISA_IO_ADD_MASK_1_0 0x0C9B
|
||||
#define PDQ_EISA_IO_ADD_MASK_1_1 0x0C9C
|
||||
#define PDQ_EISA_IO_ADD_MASK_2_0 0x0C9D
|
||||
#define PDQ_EISA_IO_ADD_MASK_2_1 0x0C9E
|
||||
#define PDQ_EISA_IO_ADD_MASK_3_0 0x0C9F
|
||||
#define PDQ_EISA_IO_ADD_MASK_3_1 0x0CA0
|
||||
#define PDQ_EISA_MOD_CONFIG_1 0x0CA1
|
||||
#define PDQ_EISA_MOD_CONFIG_2 0x0CA2
|
||||
#define PDQ_EISA_MOD_CONFIG_3 0x0CA3
|
||||
#define PDQ_EISA_MOD_CONFIG_4 0x0CA4
|
||||
#define PDQ_EISA_MOD_CONFIG_5 0x0CA5
|
||||
#define PDQ_EISA_MOD_CONFIG_6 0x0CA6
|
||||
#define PDQ_EISA_MOD_CONFIG_7 0x0CA7
|
||||
#define PDQ_EISA_DIP_SWITCH 0x0CA8
|
||||
#define PDQ_EISA_IO_CONFIG_STAT_0 0x0CA9
|
||||
#define PDQ_EISA_IO_CONFIG_STAT_1 0x0CAA
|
||||
#define PDQ_EISA_DMA_CONFIG 0x0CAB
|
||||
#define PDQ_EISA_INPUT_PORT 0x0CAC
|
||||
#define PDQ_EISA_OUTPUT_PORT 0x0CAD
|
||||
#define PDQ_EISA_FUNCTION_CTRL 0x0CAE
|
||||
|
||||
#define PDQ_TC_CSR_OFFSET 0x00100000
|
||||
#define PDQ_TC_CSR_SPACE 0x0040
|
||||
#define PDQ_FBUS_CSR_OFFSET 0x00200000
|
||||
|
@ -53,10 +53,6 @@ typedef enum _pdq_state_t pdq_state_t;
|
||||
|
||||
enum _pdq_type_t {
|
||||
PDQ_DEFPA, /* PCI-bus */
|
||||
PDQ_DEFEA, /* EISA-bus */
|
||||
PDQ_DEFTA, /* TurboChannel */
|
||||
PDQ_DEFAA, /* FutureBus+ */
|
||||
PDQ_DEFQA /* Q-bus */
|
||||
};
|
||||
|
||||
#if defined(PDQTEST)
|
||||
|
Loading…
Reference in New Issue
Block a user