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https://git.FreeBSD.org/src.git
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- As suggested by OpenSolaris use up-burst-sizes for determining the
supported burst sizes. - Add support for 64-bit burst sizes (required for SBus GEM). - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const.
This commit is contained in:
parent
ff5a50322a
commit
f27d082cdf
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=190112
@ -190,7 +190,7 @@ static bus_deactivate_resource_t sbus_deactivate_resource;
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static bus_get_dma_tag_t sbus_get_dma_tag;
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static bus_get_dma_tag_t sbus_get_dma_tag;
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static ofw_bus_get_devinfo_t sbus_get_devinfo;
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static ofw_bus_get_devinfo_t sbus_get_devinfo;
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static int sbus_inlist(const char *, const char **);
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static int sbus_inlist(const char *, const char *const *);
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static struct sbus_devinfo * sbus_setup_dinfo(device_t, struct sbus_softc *,
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static struct sbus_devinfo * sbus_setup_dinfo(device_t, struct sbus_softc *,
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phandle_t);
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phandle_t);
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static void sbus_destroy_dinfo(struct sbus_devinfo *);
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static void sbus_destroy_dinfo(struct sbus_devinfo *);
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@ -217,16 +217,15 @@ static device_method_t sbus_methods[] = {
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DEVMETHOD(bus_print_child, sbus_print_child),
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DEVMETHOD(bus_print_child, sbus_print_child),
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DEVMETHOD(bus_probe_nomatch, sbus_probe_nomatch),
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DEVMETHOD(bus_probe_nomatch, sbus_probe_nomatch),
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DEVMETHOD(bus_read_ivar, sbus_read_ivar),
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DEVMETHOD(bus_read_ivar, sbus_read_ivar),
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DEVMETHOD(bus_setup_intr, sbus_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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DEVMETHOD(bus_alloc_resource, sbus_alloc_resource),
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DEVMETHOD(bus_alloc_resource, sbus_alloc_resource),
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DEVMETHOD(bus_activate_resource, sbus_activate_resource),
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DEVMETHOD(bus_activate_resource, sbus_activate_resource),
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DEVMETHOD(bus_deactivate_resource, sbus_deactivate_resource),
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DEVMETHOD(bus_deactivate_resource, sbus_deactivate_resource),
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DEVMETHOD(bus_release_resource, sbus_release_resource),
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DEVMETHOD(bus_release_resource, sbus_release_resource),
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DEVMETHOD(bus_get_resource_list, sbus_get_resource_list),
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DEVMETHOD(bus_setup_intr, sbus_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
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DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
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DEVMETHOD(bus_get_resource_list, sbus_get_resource_list),
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DEVMETHOD(bus_get_dma_tag, sbus_get_dma_tag),
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DEVMETHOD(bus_get_dma_tag, sbus_get_dma_tag),
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DEVMETHOD(bus_child_pnpinfo_str, ofw_bus_gen_child_pnpinfo_str),
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/* ofw_bus interface */
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/* ofw_bus interface */
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DEVMETHOD(ofw_bus_get_devinfo, sbus_get_devinfo),
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DEVMETHOD(ofw_bus_get_devinfo, sbus_get_devinfo),
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@ -236,7 +235,7 @@ static device_method_t sbus_methods[] = {
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DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
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DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
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DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
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DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
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{ 0, 0 }
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KOBJMETHOD_END
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};
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};
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static driver_t sbus_driver = {
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static driver_t sbus_driver = {
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@ -266,14 +265,14 @@ struct sbus_icarg {
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bus_addr_t sica_clr;
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bus_addr_t sica_clr;
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};
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};
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static const char *sbus_order_first[] = {
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static const char *const sbus_order_first[] = {
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"auxio",
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"auxio",
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"dma",
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"dma",
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NULL
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NULL
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};
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};
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static int
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static int
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sbus_inlist(const char *name, const char **list)
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sbus_inlist(const char *name, const char *const *list)
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{
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{
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int i;
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int i;
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@ -313,32 +312,33 @@ sbus_attach(device_t dev)
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bus_size_t size;
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bus_size_t size;
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u_long vec;
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u_long vec;
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phandle_t child, node;
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phandle_t child, node;
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int clock, i, intr, rid;
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uint32_t prop;
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int i, j;
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sc = device_get_softc(dev);
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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sc->sc_dev = dev;
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node = ofw_bus_get_node(dev);
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node = ofw_bus_get_node(dev);
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rid = 0;
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i = 0;
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sc->sc_sysio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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sc->sc_sysio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
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RF_ACTIVE);
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RF_ACTIVE);
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if (sc->sc_sysio_res == NULL)
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if (sc->sc_sysio_res == NULL)
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panic("%s: cannot allocate device memory", __func__);
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panic("%s: cannot allocate device memory", __func__);
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if (OF_getprop(node, "interrupts", &intr, sizeof(intr)) == -1)
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if (OF_getprop(node, "interrupts", &prop, sizeof(prop)) == -1)
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panic("%s: cannot get IGN", __func__);
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panic("%s: cannot get IGN", __func__);
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sc->sc_ign = INTIGN(intr);
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sc->sc_ign = INTIGN(prop);
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sc->sc_cbustag = sbus_alloc_bustag(sc);
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sc->sc_cbustag = sbus_alloc_bustag(sc);
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/*
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/*
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* Record clock frequency for synchronous SCSI.
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* Record clock frequency for synchronous SCSI.
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* IS THIS THE CORRECT DEFAULT??
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* IS THIS THE CORRECT DEFAULT??
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*/
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*/
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if (OF_getprop(node, "clock-frequency", &clock, sizeof(clock)) == -1)
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if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
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clock = 25000000;
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prop = 25000000;
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sc->sc_clockfreq = clock;
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sc->sc_clockfreq = prop;
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clock /= 1000;
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prop /= 1000;
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device_printf(dev, "clock %d.%03d MHz\n", clock / 1000, clock % 1000);
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device_printf(dev, "clock %d.%03d MHz\n", prop / 1000, prop % 1000);
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/*
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/*
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* Collect address translations from the OBP.
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* Collect address translations from the OBP.
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@ -362,9 +362,9 @@ sbus_attach(device_t dev)
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sc->sc_rd[i].rd_slot = range[i].cspace;
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sc->sc_rd[i].rd_slot = range[i].cspace;
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sc->sc_rd[i].rd_coffset = range[i].coffset;
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sc->sc_rd[i].rd_coffset = range[i].coffset;
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sc->sc_rd[i].rd_cend = sc->sc_rd[i].rd_coffset + size;
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sc->sc_rd[i].rd_cend = sc->sc_rd[i].rd_coffset + size;
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rid = resource_list_add_next(rl, SYS_RES_MEMORY, phys,
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j = resource_list_add_next(rl, SYS_RES_MEMORY, phys,
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phys + size - 1, size);
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phys + size - 1, size);
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if ((res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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if ((res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &j,
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RF_ACTIVE)) == NULL)
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RF_ACTIVE)) == NULL)
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panic("%s: cannot allocate decoded range", __func__);
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panic("%s: cannot allocate decoded range", __func__);
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sc->sc_rd[i].rd_bushandle = rman_get_bushandle(res);
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sc->sc_rd[i].rd_bushandle = rman_get_bushandle(res);
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@ -381,11 +381,12 @@ sbus_attach(device_t dev)
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/*
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/*
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* Get the SBus burst transfer size if burst transfers are supported.
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* Get the SBus burst transfer size if burst transfers are supported.
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* XXX: is the default correct?
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*/
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*/
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if (OF_getprop(node, "burst-sizes", &sc->sc_burst,
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if (OF_getprop(node, "up-burst-sizes", &sc->sc_burst,
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sizeof(sc->sc_burst)) == -1 || sc->sc_burst == 0)
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sizeof(sc->sc_burst)) == -1 || sc->sc_burst == 0)
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sc->sc_burst = SBUS_BURST_DEF;
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sc->sc_burst =
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(SBUS_BURST64_DEF << SBUS_BURST64_SHIFT) | SBUS_BURST_DEF;
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/* initalise the IOMMU */
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/* initalise the IOMMU */
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@ -421,6 +422,7 @@ sbus_attach(device_t dev)
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/*
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/*
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* Hunt through all the interrupt mapping regs and register our
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* Hunt through all the interrupt mapping regs and register our
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* interrupt controller for the corresponding interrupt vectors.
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* interrupt controller for the corresponding interrupt vectors.
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* We do this early in order to be able to catch stray interrupts.
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*/
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*/
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for (i = 0; i <= SBUS_MAX_INO; i++) {
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for (i = 0; i <= SBUS_MAX_INO; i++) {
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if (sbus_find_intrmap(sc, i, &intrmap, &intrclr) == 0)
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if (sbus_find_intrmap(sc, i, &intrmap, &intrclr) == 0)
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@ -439,31 +441,32 @@ sbus_attach(device_t dev)
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(u_long)intrmap, (u_long)SYSIO_READ8(sc, intrmap),
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(u_long)intrmap, (u_long)SYSIO_READ8(sc, intrmap),
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(u_long)intrclr);
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(u_long)intrclr);
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#endif
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#endif
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if (intr_controller_register(INTMAP_VEC(sc->sc_ign, i),
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j = intr_controller_register(INTMAP_VEC(sc->sc_ign, i),
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&sbus_ic, sica) != 0)
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&sbus_ic, sica);
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panic("%s: could not register interrupt controller "
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if (j != 0)
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"for INO %d", __func__, i);
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device_printf(dev, "could not register interrupt "
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"controller for INO %d (%d)\n", i, j);
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}
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}
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/* Enable the over-temperature and power-fail interrupts. */
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/* Enable the over-temperature and power-fail interrupts. */
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rid = 4;
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i = 4;
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sc->sc_ot_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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sc->sc_ot_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
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RF_ACTIVE);
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RF_ACTIVE);
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if (sc->sc_ot_ires == NULL ||
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if (sc->sc_ot_ires == NULL ||
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INTIGN(vec = rman_get_start(sc->sc_ot_ires)) != sc->sc_ign ||
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INTIGN(vec = rman_get_start(sc->sc_ot_ires)) != sc->sc_ign ||
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INTVEC(SYSIO_READ8(sc, SBR_THERM_INT_MAP)) != vec ||
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INTVEC(SYSIO_READ8(sc, SBR_THERM_INT_MAP)) != vec ||
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intr_vectors[vec].iv_ic != &sbus_ic ||
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intr_vectors[vec].iv_ic != &sbus_ic ||
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bus_setup_intr(dev, sc->sc_ot_ires, INTR_TYPE_MISC,
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bus_setup_intr(dev, sc->sc_ot_ires, INTR_TYPE_MISC | INTR_FAST,
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NULL, sbus_overtemp, sc, &sc->sc_ot_ihand) != 0)
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NULL, sbus_overtemp, sc, &sc->sc_ot_ihand) != 0)
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panic("%s: failed to set up temperature interrupt", __func__);
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panic("%s: failed to set up temperature interrupt", __func__);
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rid = 3;
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i = 3;
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sc->sc_pf_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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sc->sc_pf_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
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RF_ACTIVE);
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RF_ACTIVE);
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if (sc->sc_pf_ires == NULL ||
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if (sc->sc_pf_ires == NULL ||
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INTIGN(vec = rman_get_start(sc->sc_pf_ires)) != sc->sc_ign ||
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INTIGN(vec = rman_get_start(sc->sc_pf_ires)) != sc->sc_ign ||
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INTVEC(SYSIO_READ8(sc, SBR_POWER_INT_MAP)) != vec ||
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INTVEC(SYSIO_READ8(sc, SBR_POWER_INT_MAP)) != vec ||
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intr_vectors[vec].iv_ic != &sbus_ic ||
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intr_vectors[vec].iv_ic != &sbus_ic ||
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bus_setup_intr(dev, sc->sc_pf_ires, INTR_TYPE_MISC,
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bus_setup_intr(dev, sc->sc_pf_ires, INTR_TYPE_MISC | INTR_FAST,
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NULL, sbus_pwrfail, sc, &sc->sc_pf_ihand) != 0)
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NULL, sbus_pwrfail, sc, &sc->sc_pf_ihand) != 0)
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panic("%s: failed to set up power fail interrupt", __func__);
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panic("%s: failed to set up power fail interrupt", __func__);
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@ -849,8 +852,8 @@ sbus_activate_resource(device_t bus, device_t child, int type, int rid,
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}
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}
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if (type == SYS_RES_MEMORY) {
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if (type == SYS_RES_MEMORY) {
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/*
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/*
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* Need to memory-map the device space, as some drivers depend
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* Need to memory-map the device space, as some drivers
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* on the virtual address being set and useable.
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* depend on the virtual address being set and usable.
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*/
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*/
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error = sparc64_bus_mem_map(rman_get_bustag(r),
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error = sparc64_bus_mem_map(rman_get_bustag(r),
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rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
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rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
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@ -77,7 +77,7 @@
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*/
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*/
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#ifndef _SPARC64_SBUS_SBUSVAR_H_
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#ifndef _SPARC64_SBUS_SBUSVAR_H_
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#define _SPARC64_SBUS_SBUSVAR_H_
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#define _SPARC64_SBUS_SBUSVAR_H_
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/*
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/*
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* Macros for probe order
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* Macros for probe order
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@ -88,18 +88,24 @@
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/*
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/*
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* PROM-reported DMA burst sizes for the SBus
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* PROM-reported DMA burst sizes for the SBus
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*/
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*/
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#define SBUS_BURST_1 0x1
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#define SBUS_BURST_1 (1 << 0)
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#define SBUS_BURST_2 0x2
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#define SBUS_BURST_2 (1 << 1)
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#define SBUS_BURST_4 0x4
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#define SBUS_BURST_4 (1 << 2)
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#define SBUS_BURST_8 0x8
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#define SBUS_BURST_8 (1 << 3)
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#define SBUS_BURST_16 0x10
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#define SBUS_BURST_16 (1 << 4)
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#define SBUS_BURST_32 0x20
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#define SBUS_BURST_32 (1 << 5)
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#define SBUS_BURST_64 0x40
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#define SBUS_BURST_64 (1 << 6)
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#define SBUS_BURST_MASK ((1 << SBUS_BURST_SIZE) - 1)
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#define SBUS_BURST_SIZE 16
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#define SBUS_BURST64_MASK (SBUS_BURST_MASK << SBUS_BURST64_SHIFT)
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#define SBUS_BURST64_SHIFT 16
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/* Used if no burst sizes are specified for the bus. */
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/* Used if no burst sizes are specified for the bus. */
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#define SBUS_BURST_DEF \
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#define SBUS_BURST_DEF \
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(SBUS_BURST_1 | SBUS_BURST_2 | SBUS_BURST_4 | SBUS_BURST_8 | \
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(SBUS_BURST_1 | SBUS_BURST_2 | SBUS_BURST_4 | SBUS_BURST_8 | \
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SBUS_BURST_16)
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SBUS_BURST_16 | SBUS_BURST_32 | SBUS_BURST_64)
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#define SBUS_BURST64_DEF \
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(SBUS_BURST_8 | SBUS_BURST_16 | SBUS_BURST_32 | SBUS_BURST_64)
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enum sbus_device_ivars {
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enum sbus_device_ivars {
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SBUS_IVAR_BURSTSZ,
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SBUS_IVAR_BURSTSZ,
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@ -111,7 +117,7 @@ enum sbus_device_ivars {
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/*
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/*
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* Simplified accessors for sbus devices
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* Simplified accessors for sbus devices
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*/
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*/
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#define SBUS_ACCESSOR(var, ivar, type) \
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#define SBUS_ACCESSOR(var, ivar, type) \
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__BUS_ACCESSOR(sbus, var, SBUS, ivar, type)
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__BUS_ACCESSOR(sbus, var, SBUS, ivar, type)
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SBUS_ACCESSOR(burstsz, BURSTSZ, int)
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SBUS_ACCESSOR(burstsz, BURSTSZ, int)
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