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Increase the TSS limit by one byte. The processor requires an additional byte

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with all bits set to 1 beyond the I/O permission bitmap.

Prior to this change accessing I/O ports [0xFFF8-0xFFFF] would trigger a
#GP fault even though the I/O bitmap allowed access to those ports.

For more details see section "I/O Permission Bit Map" in the Intel SDM, Vol 1.

Reviewed by:	kib
This commit is contained in:
Neel Natu 2014-05-14 22:24:09 +00:00
parent b6d2fa3ed3
commit f3db4c53e6
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=266093
4 changed files with 10 additions and 8 deletions
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5
sys/amd64/amd64/machdep.c
View File

@ -1147,7 +1147,7 @@ struct soft_segment_descriptor gdt_segs[] = {
.ssd_gran = 1 }, .ssd_gran = 1 },
/* GPROC0_SEL 9 Proc 0 Tss Descriptor */ /* GPROC0_SEL 9 Proc 0 Tss Descriptor */
{ .ssd_base = 0x0, { .ssd_base = 0x0,
.ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, .ssd_limit = sizeof(struct amd64tss) + IOPERM_BITMAP_SIZE - 1,
.ssd_type = SDT_SYSTSS, .ssd_type = SDT_SYSTSS,
.ssd_dpl = SEL_KPL, .ssd_dpl = SEL_KPL,
.ssd_p = 1, .ssd_p = 1,
@ -2003,8 +2003,7 @@ hammer_time(u_int64_t modulep, u_int64_t physfree)
common_tss[0].tss_ist2 = (long) np; common_tss[0].tss_ist2 = (long) np;
/* Set the IO permission bitmap (empty due to tss seg limit) */ /* Set the IO permission bitmap (empty due to tss seg limit) */
common_tss[0].tss_iobase = sizeof(struct amd64tss) + common_tss[0].tss_iobase = sizeof(struct amd64tss) + IOPERM_BITMAP_SIZE;
IOPAGES * PAGE_SIZE;
gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
ltr(gsel_tss); ltr(gsel_tss);

2
sys/amd64/amd64/mp_machdep.c
View File

@ -637,7 +637,7 @@ init_secondary(void)
common_tss[cpu] = common_tss[0]; common_tss[cpu] = common_tss[0];
common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */ common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */
common_tss[cpu].tss_iobase = sizeof(struct amd64tss) + common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
IOPAGES * PAGE_SIZE; IOPERM_BITMAP_SIZE;
common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE]; common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
/* The NMI stack runs on IST2. */ /* The NMI stack runs on IST2. */

5
sys/amd64/amd64/sys_machdep.c
View File

@ -338,7 +338,6 @@ amd64_set_ioperm(td, uap)
char *iomap; char *iomap;
struct amd64tss *tssp; struct amd64tss *tssp;
struct system_segment_descriptor *tss_sd; struct system_segment_descriptor *tss_sd;
u_long *addr;
struct pcb *pcb; struct pcb *pcb;
if ((error = priv_check(td, PRIV_IO)) != 0) if ((error = priv_check(td, PRIV_IO)) != 0)
@ -361,9 +360,7 @@ amd64_set_ioperm(td, uap)
if (tssp == NULL) if (tssp == NULL)
return (ENOMEM); return (ENOMEM);
iomap = (char *)&tssp[1]; iomap = (char *)&tssp[1];
addr = (u_long *)iomap; memset(iomap, 0xff, IOPERM_BITMAP_SIZE);
for (i = 0; i < (ctob(IOPAGES) + 1) / sizeof(u_long); i++)
*addr++ = ~0;
critical_enter(); critical_enter();
/* Takes care of tss_rsp0. */ /* Takes care of tss_rsp0. */
memcpy(tssp, &common_tss[PCPU_GET(cpuid)], memcpy(tssp, &common_tss[PCPU_GET(cpuid)],

6
sys/amd64/include/param.h
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@ -120,6 +120,12 @@
#define MAXPAGESIZES 3 /* maximum number of supported page sizes */ #define MAXPAGESIZES 3 /* maximum number of supported page sizes */
#define IOPAGES 2 /* pages of i/o permission bitmap */ #define IOPAGES 2 /* pages of i/o permission bitmap */
/*
* I/O permission bitmap has a bit for each I/O port plus an additional
* byte at the end with all bits set. See section "I/O Permission Bit Map"
* in the Intel SDM for more details.
*/
#define IOPERM_BITMAP_SIZE (IOPAGES * PAGE_SIZE + 1)
#ifndef KSTACK_PAGES #ifndef KSTACK_PAGES
#define KSTACK_PAGES 4 /* pages of kstack (with pcb) */ #define KSTACK_PAGES 4 /* pages of kstack (with pcb) */