mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-14 10:09:48 +00:00
MFp4:
o Add memory barrier to bus space o Allow for up to 3 IRQs per device o Move to table driven population of children devices. o Add support for usb ohci memory mapped controller resource allocation. o Clean up a bunch of extra writes to disable interrupts that are now done elsewhere. o Force all system interrupt handlers be fast. We get deadlock if they aren't.
This commit is contained in:
Warner Losh
parent
5bcedfaa73
commit
f3de38a73d
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=156828
@ -84,6 +84,12 @@ at91_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
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return (0);
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}
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static void
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at91_barrier(void *t, bus_space_handle_t bsh, bus_size_t size, bus_size_t b,
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int a)
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{
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}
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bs_protos(generic);
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bs_protos(generic_armv4);
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@ -101,7 +107,7 @@ struct bus_space at91_bs_tag = {
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NULL,
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/* barrier */
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NULL,
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at91_barrier,
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/* read (single) */
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generic_bs_r_1,
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@ -189,7 +195,7 @@ extern void irq_entry(void);
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static void
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at91_add_child(device_t dev, int prio, const char *name, int unit,
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bus_addr_t addr, bus_size_t size, int irq)
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bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2)
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{
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device_t kid;
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struct at91_ivar *ivar;
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@ -204,12 +210,176 @@ at91_add_child(device_t dev, int prio, const char *name, int unit,
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}
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device_set_ivars(kid, ivar);
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resource_list_init(&ivar->resources);
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if (irq != -1)
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bus_set_resource(kid, SYS_RES_IRQ, 0, irq, 1);
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if (irq0 != -1)
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bus_set_resource(kid, SYS_RES_IRQ, 0, irq0, 1);
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if (irq1 != 0)
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bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1);
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if (irq2 != 0)
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bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1);
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if (addr != 0)
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bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size);
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}
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struct cpu_devs
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{
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const char *name;
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int unit;
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bus_addr_t mem_base;
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bus_size_t mem_len;
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int irq0;
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int irq1;
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int irq2;
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};
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struct cpu_devs at91rm9200_devs[] =
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{
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// All the "system" devices
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{
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"at91_st", 0,
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AT91RM92_BASE + AT91RM92_ST_BASE, AT91RM92_ST_SIZE,
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AT91RM92_IRQ_SYSTEM
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},
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{
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"at91_pio", 0,
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AT91RM92_BASE + AT91RM92_PIOA_BASE, AT91RM92_PIO_SIZE,
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AT91RM92_IRQ_SYSTEM
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},
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{
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"at91_pio", 1,
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AT91RM92_BASE + AT91RM92_PIOB_BASE, AT91RM92_PIO_SIZE,
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AT91RM92_IRQ_SYSTEM
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},
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{
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"at91_pio", 2,
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AT91RM92_BASE + AT91RM92_PIOC_BASE, AT91RM92_PIO_SIZE,
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AT91RM92_IRQ_SYSTEM
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},
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{
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"at91_pio", 3,
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AT91RM92_BASE + AT91RM92_PIOD_BASE, AT91RM92_PIO_SIZE,
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AT91RM92_IRQ_SYSTEM
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},
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{
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"at91_pmc", 0,
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AT91RM92_BASE + AT91RM92_PMC_BASE, AT91RM92_PMC_SIZE,
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AT91RM92_IRQ_SYSTEM
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},
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{
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"at91_aic", 0,
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AT91RM92_BASE + AT91RM92_AIC_BASE, AT91RM92_AIC_SIZE,
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0 // Interrupt controller has no interrupts!
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},
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{
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"at91_rtc", 0,
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AT91RM92_BASE + AT91RM92_RTC_BASE, AT91RM92_RTC_SIZE,
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AT91RM92_IRQ_SYSTEM
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},
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{
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"at91_mc", 0,
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AT91RM92_BASE + AT91RM92_MC_BASE, AT91RM92_MC_SIZE,
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AT91RM92_IRQ_SYSTEM
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},
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// All other devices
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{
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"at91_tc", 0,
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AT91RM92_BASE + AT91RM92_TC0_BASE, AT91RM92_TC_SIZE,
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AT91RM92_IRQ_TC0, AT91RM92_IRQ_TC1, AT91RM92_IRQ_TC2
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},
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{
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"at91_tc", 1,
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AT91RM92_BASE + AT91RM92_TC1_BASE, AT91RM92_TC_SIZE,
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AT91RM92_IRQ_TC3, AT91RM92_IRQ_TC4, AT91RM92_IRQ_TC5
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},
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{
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"at91_udp", 0,
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AT91RM92_BASE + AT91RM92_UDP_BASE, AT91RM92_UDP_SIZE,
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AT91RM92_IRQ_UDP
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},
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{
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"at91_mci", 0,
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AT91RM92_BASE + AT91RM92_MCI_BASE, AT91RM92_MCI_SIZE,
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AT91RM92_IRQ_MCI
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},
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{
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"at91_twi", 0,
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AT91RM92_BASE + AT91RM92_TWI_BASE, AT91RM92_TWI_SIZE,
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AT91RM92_IRQ_TWI
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},
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{
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"ate", 0,
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AT91RM92_BASE + AT91RM92_EMAC_BASE, AT91RM92_EMAC_SIZE,
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AT91RM92_IRQ_EMAC
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},
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{
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"uart", 0,
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AT91RM92_BASE + AT91RM92_DBGU_BASE, AT91RM92_DBGU_SIZE,
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AT91RM92_IRQ_SYSTEM
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},
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{
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"uart", 1,
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AT91RM92_BASE + AT91RM92_USART0_BASE, AT91RM92_USART_SIZE,
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AT91RM92_IRQ_USART0
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},
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{
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"uart", 2,
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AT91RM92_BASE + AT91RM92_USART1_BASE, AT91RM92_USART_SIZE,
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AT91RM92_IRQ_USART1
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},
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{
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"uart", 3,
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AT91RM92_BASE + AT91RM92_USART2_BASE, AT91RM92_USART_SIZE,
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AT91RM92_IRQ_USART2
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},
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{
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"uart", 4,
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AT91RM92_BASE + AT91RM92_USART3_BASE, AT91RM92_USART_SIZE,
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AT91RM92_IRQ_USART3
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},
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{
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"at91_ssc", 0,
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AT91RM92_BASE + AT91RM92_SSC0_BASE, AT91RM92_SSC_SIZE,
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AT91RM92_IRQ_SSC0
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},
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{
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"at91_ssc", 1,
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AT91RM92_BASE + AT91RM92_SSC1_BASE, AT91RM92_SSC_SIZE,
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AT91RM92_IRQ_SSC1
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},
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{
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"at91_ssc", 2,
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AT91RM92_BASE + AT91RM92_SSC2_BASE, AT91RM92_SSC_SIZE,
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AT91RM92_IRQ_SSC2
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},
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{
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"at91_spi", 0,
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AT91RM92_BASE + AT91RM92_SPI_BASE, AT91RM92_SPI_SIZE,
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AT91RM92_IRQ_SPI
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},
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{
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"ohci", 0,
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AT91RM92_OHCI_BASE, AT91RM92_OHCI_SIZE,
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AT91RM92_IRQ_UHP
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},
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{ 0, 0, 0, 0, 0 }
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};
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static void
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at91_cpu_add_builtin_children(device_t dev, struct at91_softc *sc)
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{
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int i;
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struct cpu_devs *walker;
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// XXX should look at the device id in the DBGU register and
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// XXX based on the CPU load in these devices
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for (i = 0, walker = at91rm9200_devs; walker->name; i++, walker++) {
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at91_add_child(dev, i, walker->name, walker->unit,
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walker->mem_base, walker->mem_len, walker->irq0,
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walker->irq1, walker->irq2);
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}
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}
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#define NORMDEV 50
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static int
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at91_attach(device_t dev)
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@ -228,13 +398,20 @@ at91_attach(device_t dev)
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sc->sc_irq_rman.rm_descr = "AT91RM92 IRQs";
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sc->sc_mem_rman.rm_type = RMAN_ARRAY;
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sc->sc_mem_rman.rm_descr = "AT91RM92 Memory";
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#if 0
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sc->sc_usbmem_rman.rm_type = RMAN_ARRAY;
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sc->sc_usbmem_rman.rm_descr = "AT91RM92 USB Memory-mapped regs";
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#endif
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if (rman_init(&sc->sc_irq_rman) != 0 ||
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rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
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panic("at91_attach: failed to set up IRQ rman");
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if (rman_init(&sc->sc_mem_rman) != 0 ||
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rman_manage_region(&sc->sc_mem_rman, 0xfff00000ul,
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0xfffffffful) != 0)
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0xfffffffful) != 0)
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panic("at91_attach: failed to set up memory rman");
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if (rman_manage_region(&sc->sc_mem_rman, AT91RM92_OHCI_BASE,
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AT91RM92_OHCI_BASE + AT91RM92_OHCI_SIZE - 1) != 0)
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panic("at91_attach: failed to set up ohci memory");
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for (i = 0; i < 32; i++) {
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_SVR +
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@ -258,52 +435,13 @@ at91_attach(device_t dev)
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/* XXX */
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/* Disable all interrupts for RTC (0xe24 == RTC_IDR) */
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xe24, 0xffffffff);
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/* Disable all interrupts for PMC (0xc64 == PMC_IDR) */
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xc64, 0xffffffff);
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/* Disable all interrupts for ST */
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xd18, 0xffffffff);
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/* DIsable all interrupts for DBGU */
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0x20c, 0xffffffff);
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/* Disable all interrupts for PIOA */
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0x444, 0xffffffff);
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/* Disable all interrupts for PIOB */
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0x644, 0xffffffff);
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/* Disable all interrupts for PIOC */
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0x844, 0xffffffff);
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/* Disable all interrupts for PIOD */
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xa44, 0xffffffff);
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/* Disable all interrupts for the SDRAM controller */
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff);
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at91_add_child(dev, 0, "at91_st", 0, 0, 0, 1);
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at91_add_child(dev, 10, "at91_udp", 0, AT91RM92_BASE + // UDP
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AT91RM92_UDP_BASE, AT91RM92_UDP_SIZE, AT91RM92_IRQ_UDP);
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at91_add_child(dev, 10, "at91_mci", 0, AT91RM92_BASE + // MCI
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AT91RM92_MCI_BASE, AT91RM92_MCI_SIZE, AT91RM92_IRQ_MCI);
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at91_add_child(dev, 10, "at91_twi", 0, AT91RM92_BASE + // TWI
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AT91RM92_TWI_BASE, AT91RM92_TWI_SIZE, AT91RM92_IRQ_TWI);
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at91_add_child(dev, 10, "ate", 0, AT91RM92_BASE + // EMAC
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AT91RM92_EMAC_BASE, AT91RM92_EMAC_SIZE, AT91RM92_IRQ_EMAC);
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at91_add_child(dev, 10, "uart", 0, AT91RM92_BASE + // DBGU
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AT91RM92_SYS_BASE + DBGU, DBGU_SIZE, AT91RM92_IRQ_SYSTEM);
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at91_add_child(dev, 10, "uart", 1, AT91RM92_BASE + // USART0
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AT91RM92_USART0_BASE, AT91RM92_USART_SIZE, AT91RM92_IRQ_USART0);
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at91_add_child(dev, 10, "uart", 2, AT91RM92_BASE + // USART1
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AT91RM92_USART1_BASE, AT91RM92_USART_SIZE, AT91RM92_IRQ_USART1);
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at91_add_child(dev, 10, "uart", 3, AT91RM92_BASE + // USART2
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AT91RM92_USART2_BASE, AT91RM92_USART_SIZE, AT91RM92_IRQ_USART2);
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at91_add_child(dev, 10, "uart", 4, AT91RM92_BASE + // USART3
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AT91RM92_USART3_BASE, AT91RM92_USART_SIZE, AT91RM92_IRQ_USART3);
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at91_add_child(dev, 10, "at91_ssc", 0, AT91RM92_BASE + // SSC0
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AT91RM92_SSC0_BASE, AT91RM92_SSC_SIZE, AT91RM92_IRQ_SSC0);
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at91_add_child(dev, 10, "at91_ssc", 1, AT91RM92_BASE + // SSC1
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AT91RM92_SSC1_BASE, AT91RM92_SSC_SIZE, AT91RM92_IRQ_SSC1);
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at91_add_child(dev, 10, "at91_ssc", 2, AT91RM92_BASE + // SSC2
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AT91RM92_SSC2_BASE, AT91RM92_SSC_SIZE, AT91RM92_IRQ_SSC2);
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at91_add_child(dev, 10, "at91_spi", 0, AT91RM92_BASE + // SPI
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AT91RM92_SPI_BASE, AT91RM92_SPI_SIZE, AT91RM92_IRQ_SPI);
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// Not sure that the following belongs on this bus.
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at91_add_child(dev, 10, "ohci", 0, // UHP
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AT91RM92_OHCI_BASE, AT91RM92_OHCI_SIZE, AT91RM92_IRQ_UHP);
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at91_cpu_add_builtin_children(dev, sc);
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bus_generic_probe(dev);
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bus_generic_attach(dev);
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enable_interrupts(I32_bit | F32_bit);
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@ -340,8 +478,14 @@ at91_alloc_resource(device_t dev, device_t child, int type, int *rid,
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start, end, count, flags, child);
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break;
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case SYS_RES_MEMORY:
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rle->res = rman_reserve_resource(&sc->sc_mem_rman,
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start, end, count, flags, child);
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#if 0
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if (start >= 0x00300000 && start <= 0x003fffff)
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rle->res = rman_reserve_resource(&sc->sc_usbmem_rman,
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start, end, count, flags, child);
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else
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#endif
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rle->res = rman_reserve_resource(&sc->sc_mem_rman,
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start, end, count, flags, child);
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rman_set_bustag(rle->res, &at91_bs_tag);
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rman_set_bushandle(rle->res, start);
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break;
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@ -388,6 +532,8 @@ at91_setup_intr(device_t dev, device_t child,
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{
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struct at91_softc *sc = device_get_softc(dev);
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if (rman_get_start(ires) == AT91RM92_IRQ_SYSTEM && !(flags & INTR_FAST))
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panic("All system interrupt ISRs must be type INTR_FAST");
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BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, intr, arg,
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cookiep);
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bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_IECR,
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