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This won't be needed. There is already userland infrastructure for fpu emulation
for sparc64.
This commit is contained in:
Kip Macy
parent
c94d217091
commit
f53c03a0e3
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=163261
@ -1,191 +0,0 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/* FPop1 */
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#define FMOVQ 0x0003
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#define FNEGQ 0x0007
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#define FADDQ 0x0403
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#define FADDQ 0x0407
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#define FQTOI 0x0D03
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#define FABSQ 0x000B
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#define FSQRTS 0x0209
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#define FSQRTD 0x020A
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#define FSQRTQ 0x020B
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#define FMULQ 0x040B
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#define FDIVQ 0x040F
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#define FDMULQ 0x060E
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#define FXTOQ 0x080C
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#define FQTOD 0x0C0B
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#define FITOQ 0x0C0D
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#define FSTOQ 0x0C0E
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/* FPop2 */
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#define FMOVQZ 0x027
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#define FMOVQLE 0x047
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#define FCMPQ 0x053
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#define FCMPEQ 0x057
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#define FMOVQLZ 0x067
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#define FMOVQNZ 0x0A7
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#define FMOVQ0 0x003
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#define FMOVQ1 0x043
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#define FMOVQ2 0x083
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#define FMOVQ3 0x0C3
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#define FMOVQI 0x103
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#define FMOVQX 0x183
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#define REGINFO(ftt, rd, rdu, rs2, rs2u, rs1, rs1u) \
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reginfo = (rs1u << 2) | (rs1 << 0) | (rs2u << 5) | (rs2 << 3) \
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| (rdu << 8) | (rd << 6) | (ftt << 9)
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void fpemu(struct trapframe *tf, uint64_t type, uint64_t fsr)
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{
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uint32_t insn;
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if (tf->tf_tstate & TSTATE_PRIV)
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panic("unimplemented FPop in kernel");
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if (copyin(tf->tf_tpc, &insn) != EFAULT) {
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if ((insn & FPOP_MASK) == FPOP1) {
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switch ((insn >> 5) & 0x1ff) {
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case FMOVQ:
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case FNEGQ:
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case FABSQ: REGINFO(3,3,0,3,0,0,0); break;
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case FSQRTQ: REGINFO(3,3,1,3,1,0,0); break;
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case FADDQ:
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case FSUBQ:
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case FMULQ:
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case FDIVQ: REGINFO(3,3,1,3,1,3,1); break;
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case FDMULQ: REGINFO(3,3,1,2,1,2,1); break;
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case FQTOX: REGINFO(3,2,0,3,1,0,0); break;
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case FXTOQ: REGINFO(3,3,1,2,0,0,0); break;
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case FQTOS: REGINFO(3,1,1,3,1,0,0); break;
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case FQTOD: REGINFO(3,2,1,3,1,0,0); break;
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case FITOQ: REGINFO(3,3,1,1,0,0,0); break;
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case FSTOQ: REGINFO(3,3,1,1,1,0,0); break;
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case FDTOQ: REGINFO(3,3,1,2,1,0,0); break;
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case FQTOI: REGINFO(3,1,0,3,1,0,0); break;
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/* SUBNORMAL - ftt == 2 */
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case FSQRTS: REGINFO(2,1,1,1,1,0,0); break;
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case FSQRTD: REGINFO(2,2,1,2,1,0,0); break;
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case FADDD:
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case FSUBD:
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case FMULD:
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case FDIVD: REGINFO(2,2,1,2,1,2,1); break;
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case FADDS:
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case FSUBS:
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case FMULS:
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case FDIVS: REGINFO(2,1,1,1,1,1,1); break;
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case FSMULD: REGINFO(2,2,1,1,1,1,1); break;
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case FSTOX: REGINFO(2,2,0,1,1,0,0); break;
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case FDTOX: REGINFO(2,2,0,2,1,0,0); break;
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case FDTOS: REGINFO(2,1,1,2,1,0,0); break;
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case FSTOD: REGINFO(2,2,1,1,1,0,0); break;
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case FSTOI: REGINFO(2,1,0,1,1,0,0); break;
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case FDTOI: REGINFO(2,1,0,2,1,0,0); break;
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}
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} else if ((insn & FPOP_MASK) == FPOP2) {
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IR = 2;
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switch ((insn >> 5) & 0x1ff) {
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case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
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case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
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/* Now the conditional fmovq support */
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case FMOVQ0:
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case FMOVQ1:
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case FMOVQ2:
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case FMOVQ3:
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/* fmovq %fccX, %fY, %fZ */
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if (!((insn >> 11) & 3))
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XR = tf->tf_fsr >> 10;
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else
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XR = tf->tf_fsr >> (30 + ((insn >> 10) & 0x6));
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XR &= 3;
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IR = 0;
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switch ((insn >> 14) & 0x7) {
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/* case 0: IR = 0; break; *//* Never */
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case 1: if (XR) IR = 1; break;/* Not Equal */
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case 2: if (XR == 1 || XR == 2) IR = 1; break;/* Less or Greater */
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case 3: if (XR & 1) IR = 1; break;/* Unordered or Less */
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case 4: if (XR == 1) IR = 1; break;/* Less */
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case 5: if (XR & 2) IR = 1; break;/* Unordered or Greater */
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case 6: if (XR == 2) IR = 1; break;/* Greater */
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case 7: if (XR == 3) IR = 1; break;/* Unordered */
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}
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if ((insn >> 14) & 8)
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IR ^= 1;
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break;
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case FMOVQI:
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case FMOVQX:
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/* fmovq %[ix]cc, %fY, %fZ */
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XR = tf->tf_tstate >> 32;
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if ((insn >> 5) & 0x80)
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XR >>= 4;
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XR &= 0xf;
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IR = 0;
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freg = ((XR >> 2) ^ XR) & 2;
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switch ((insn >> 14) & 0x7) {
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/* case 0: IR = 0; break; *//* Never */
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case 1: if (XR & 4) IR = 1; break;/* Equal */
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case 2: if ((XR & 4) || freg) IR = 1; break;/* Less or Equal */
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case 3: if (freg) IR = 1; break;/* Less */
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case 4: if (XR & 5) IR = 1; break;/* Less or Equal Unsigned */
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case 5: if (XR & 1) IR = 1; break;/* Carry Set */
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case 6: if (XR & 8) IR = 1; break;/* Negative */
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case 7: if (XR & 2) IR = 1; break;/* Overflow Set */
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}
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if ((insn >> 14) & 8)
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IR ^= 1;
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break;
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case FMOVQZ:
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case FMOVQLE:
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case FMOVQLZ:
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case FMOVQNZ:
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case FMOVQGZ:
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case FMOVQGE:
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freg = (insn >> 14) & 0x1f;
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KASSERT(freg < 16, ("freg too large"));
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if (!freg)
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XR = 0;
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else if (freg < 16)
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XR = regs->u_regs[freg];
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#if 0
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else if (test_thread_flag(TIF_32BIT)) {
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struct reg_window32 __user *win32;
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flushw_user ();
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win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
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get_user(XR, &win32->locals[freg - 16]);
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} else {
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struct reg_window __user *win;
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flushw_user ();
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win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS);
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get_user(XR, &win->locals[freg - 16]);
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}
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#endif
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IR = 0;
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switch ((insn >> 10) & 3) {
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case 1: if (!XR) IR = 1; break;/* Register Zero */
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case 2: if (XR <= 0) IR = 1; break;/* Register Less Than or Equal to Zero */
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case 3: if (XR < 0) IR = 1; break;/* Register Less Than Zero */
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}
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if ((insn >> 10) & 4)
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IR ^= 1;
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break;
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}
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if (IR == 0) {
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/* The fmov test was false. Do a nop instead */
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tf->tf_fsr &= ~(FSR_CEXC_MASK);
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tf->tf_tpc = tf->tf_tnpc;
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tf->tf_tnpc += 4;
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return 1;
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} else if (IR == 1) {
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/* Change the instruction into plain fmovq */
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insn = (insn & 0x3e00001f) | 0x81a00060;
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REGINFO(3,3,0,3,0,0,0);
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}
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}
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}
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}
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