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Correct the delay durations as in the sample sources provided by Crystal Semiconductor.

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This commit is contained in:
Seigo Tanimura 2000-01-01 09:07:03 +00:00
parent 555fff2109
commit f7e00c54d1
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=55288
1 changed files with 4 additions and 4 deletions
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8
sys/dev/sound/pci/csa.c
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@ -286,7 +286,7 @@ csa_initialize(sc_p scp)
* for a reset. * for a reset.
*/ */
csa_writeio(resp, BA0_ACCTL, 0); csa_writeio(resp, BA0_ACCTL, 0);
DELAY(250); DELAY(100);
csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
/* /*
@ -362,7 +362,7 @@ csa_initialize(sc_p scp)
* First, lets wait a short while to let things settle out a bit, * First, lets wait a short while to let things settle out a bit,
* and to prevent retrying the read too quickly. * and to prevent retrying the read too quickly.
*/ */
DELAY(250); DELAY(125);
/* /*
* Read the AC97 status register to see if we've seen a CODEC READY * Read the AC97 status register to see if we've seen a CODEC READY
@ -398,7 +398,7 @@ csa_initialize(sc_p scp)
#if notdef #if notdef
DELAY(10000000L); /* clw */ DELAY(10000000L); /* clw */
#else #else
DELAY(2500); DELAY(1000);
#endif /* notdef */ #endif /* notdef */
/* /*
* Read the input slot valid register and see if input slots 3 and * Read the input slot valid register and see if input slots 3 and
@ -477,7 +477,7 @@ csa_clearserialfifos(csa_res *resp)
for (i = 0 ; i < 256 ; i++) { for (i = 0 ; i < 256 ; i++) {
/* Make sure the previous FIFO write operation has completed. */ /* Make sure the previous FIFO write operation has completed. */
for (j = 0 ; j < 5 ; j++) { for (j = 0 ; j < 5 ; j++) {
DELAY(250); DELAY(100);
serbst = csa_readio(resp, BA0_SERBST); serbst = csa_readio(resp, BA0_SERBST);
if ((serbst & SERBST_WBSY) == 0) if ((serbst & SERBST_WBSY) == 0)
break; break;