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Allow external interrupts.
- Set the external pin to interrupt in bus_setup_intr
- Implement bus_config_intr for external interrupts
- Extend arm_{,un}mask_irq to work with external interrupts
Approved by: imp (mentor)
This commit is contained in:
Andrew Turner
parent
34f56898a1
commit
fa94061701
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=210458
@ -118,6 +118,8 @@ static int s3c24x0_setup_intr(device_t, device_t, struct resource *, int,
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driver_filter_t *, driver_intr_t *, void *, void **);
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static int s3c24x0_teardown_intr(device_t, device_t, struct resource *,
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void *);
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static int s3c24x0_config_intr(device_t, int, enum intr_trigger,
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enum intr_polarity);
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static struct resource *s3c24x0_alloc_resource(device_t, device_t, int, int *,
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u_long, u_long, u_long, u_int);
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static int s3c24x0_activate_resource(device_t, device_t, int, int,
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@ -134,6 +136,7 @@ static device_method_t s3c24x0_methods[] = {
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DEVMETHOD(device_identify, s3c24x0_identify),
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DEVMETHOD(bus_setup_intr, s3c24x0_setup_intr),
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DEVMETHOD(bus_teardown_intr, s3c24x0_teardown_intr),
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DEVMETHOD(bus_config_intr, s3c24x0_config_intr),
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DEVMETHOD(bus_alloc_resource, s3c24x0_alloc_resource),
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DEVMETHOD(bus_activate_resource, s3c24x0_activate_resource),
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DEVMETHOD(bus_release_resource, s3c24x0_release_resource),
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@ -176,6 +179,30 @@ s3c24x0_add_child(device_t bus, int prio, const char *name, int unit)
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return (child);
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}
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static void
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s3c24x0_enable_ext_intr(unsigned int irq)
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{
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uint32_t reg, value;
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int offset;
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if (irq <= 7) {
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reg = GPIO_PFCON;
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offset = irq * 2;
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} else if (irq <= 23) {
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reg = GPIO_PGCON;
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offset = (irq - 8) * 2;
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} else
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return;
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/* Make the pin an interrupt source */
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value = bus_space_read_4(s3c2xx0_softc->sc_iot,
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s3c2xx0_softc->sc_gpio_ioh, reg);
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value &= ~(3 << offset);
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value |= 2 << offset;
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bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh,
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reg, value);
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}
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static int
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s3c24x0_setup_intr(device_t dev, device_t child,
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struct resource *ires, int flags, driver_filter_t *filt,
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@ -189,6 +216,10 @@ s3c24x0_setup_intr(device_t dev, device_t child,
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return (error);
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for (irq = rman_get_start(ires); irq <= rman_get_end(ires); irq++) {
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if (irq >= S3C24X0_EXTIRQ_MIN && irq <= S3C24X0_EXTIRQ_MAX) {
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/* Enable the external interrupt pin */
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s3c24x0_enable_ext_intr(irq - S3C24X0_EXTIRQ_MIN);
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}
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arm_unmask_irq(irq);
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}
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return (0);
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@ -201,6 +232,59 @@ s3c24x0_teardown_intr(device_t dev, device_t child, struct resource *res,
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return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
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}
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static int
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s3c24x0_config_intr(device_t dev, int irq, enum intr_trigger trig,
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enum intr_polarity pol)
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{
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uint32_t mask, reg, value;
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int offset;
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/* Only external interrupts can be configured */
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if (irq < S3C24X0_EXTIRQ_MIN || irq > S3C24X0_EXTIRQ_MAX)
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return (EINVAL);
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/* There is no standard trigger or polarity for the bus */
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if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM)
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return (EINVAL);
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irq -= S3C24X0_EXTIRQ_MIN;
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/* Get the bits to set */
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mask = 0;
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if (pol == INTR_POLARITY_LOW) {
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mask = 2;
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} else if (pol == INTR_POLARITY_HIGH) {
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mask = 4;
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}
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if (trig == INTR_TRIGGER_LEVEL) {
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mask >>= 2;
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}
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/* Get the register to set */
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if (irq <= 7) {
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reg = GPIO_EXTINT(0);
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offset = irq * 4;
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} else if (irq <= 15) {
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reg = GPIO_EXTINT(1);
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offset = (irq - 8) * 4;
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} else if (irq <= 23) {
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reg = GPIO_EXTINT(2);
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offset = (irq - 16) * 4;
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} else {
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return (EINVAL);
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}
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/* Set the new signaling method */
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value = bus_space_read_4(s3c2xx0_softc->sc_iot,
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s3c2xx0_softc->sc_gpio_ioh, reg);
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value &= ~(7 << offset);
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value |= mask << offset;
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bus_space_write_4(s3c2xx0_softc->sc_iot,
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s3c2xx0_softc->sc_gpio_ioh, reg, value);
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return (0);
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}
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static struct resource *
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s3c24x0_alloc_resource(device_t bus, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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@ -356,6 +440,7 @@ s3c24x0_attach(device_t dev)
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bus_space_tag_t iot;
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device_t child;
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unsigned int i, j;
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u_long irqmax;
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s3c2xx0_softc = &(sc->sc_sx);
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sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag;
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@ -363,10 +448,6 @@ s3c24x0_attach(device_t dev)
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s3c2xx0_softc->s3c2xx0_irq_rman.rm_descr = "S3C24X0 IRQs";
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s3c2xx0_softc->s3c2xx0_mem_rman.rm_type = RMAN_ARRAY;
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s3c2xx0_softc->s3c2xx0_mem_rman.rm_descr = "S3C24X0 Device Registers";
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if (rman_init(&s3c2xx0_softc->s3c2xx0_irq_rman) != 0 ||
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rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman, 0,
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S3C2410_SUBIRQ_MAX) != 0) /* XXX Change S3C2440_SUBIRQ_MAX depending on micro */
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panic("s3c24x0_attach: failed to set up IRQ rman");
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/* Manage the registor memory space */
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if ((rman_init(&s3c2xx0_softc->s3c2xx0_mem_rman) != 0) ||
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(rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman,
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@ -388,6 +469,22 @@ s3c24x0_attach(device_t dev)
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*/
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s3c24x0_identify_cpu(dev);
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/*
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* Manage the interrupt space.
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* We need to put this after s3c24x0_identify_cpu as the avaliable
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* interrupts change depending on which CPU we have.
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*/
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if (sc->sc_sx.sc_cpu == CPU_S3C2410)
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irqmax = S3C2410_SUBIRQ_MAX;
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else
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irqmax = S3C2440_SUBIRQ_MAX;
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if (rman_init(&s3c2xx0_softc->s3c2xx0_irq_rman) != 0 ||
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rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman, 0,
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irqmax) != 0 ||
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rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman,
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S3C24X0_EXTIRQ_MIN, S3C24X0_EXTIRQ_MAX))
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panic("s3c24x0_attach: failed to set up IRQ rman");
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/* calculate current clock frequency */
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s3c24x0_clock_freq(&sc->sc_sx);
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device_printf(dev, "fclk %d MHz hclk %d MHz pclk %d MHz\n",
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@ -607,6 +704,33 @@ arm_get_next_irq(int last __unused)
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return (irq);
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return (S3C24X0_SUBIRQ_MIN + subirq);
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case S3C24X0_INT_0:
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case S3C24X0_INT_1:
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case S3C24X0_INT_2:
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case S3C24X0_INT_3:
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/* There is a 1:1 mapping to the IRQ we are handling */
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return S3C24X0_INT_EXT(irq);
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case S3C24X0_INT_4_7:
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case S3C24X0_INT_8_23:
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/* Find the external interrupt being called */
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subirq = 0x7fffff;
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subirq &= bus_space_read_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTPEND);
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subirq &= ~bus_space_read_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK);
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if (subirq == 0)
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return (irq);
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subirq = ffs(subirq) - 1;
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/* Clear the external irq pending bit */
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bus_space_write_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTPEND,
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(1 << subirq));
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return S3C24X0_INT_EXT(subirq);
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}
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return (irq);
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@ -619,18 +743,28 @@ arm_mask_irq(uintptr_t irq)
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{
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u_int32_t mask;
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if (irq >= S3C24X0_INT_EXT(0) && irq <= S3C24X0_INT_EXT(3)) {
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/* External interrupt 0..3 are directly mapped to irq 0..3 */
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irq -= S3C24X0_EXTIRQ_MIN;
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}
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if (irq < S3C24X0_SUBIRQ_MIN) {
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mask = bus_space_read_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK);
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mask |= (1 << irq);
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bus_space_write_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask);
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} else {
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} else if (irq < S3C24X0_EXTIRQ_MIN) {
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mask = bus_space_read_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK);
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mask |= (1 << (irq - S3C24X0_SUBIRQ_MIN));
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bus_space_write_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask);
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} else {
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mask = bus_space_read_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK);
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mask |= (1 << (irq - S3C24X0_EXTIRQ_MIN));
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bus_space_write_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_intctl_ioh, GPIO_EINTMASK, mask);
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}
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}
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@ -639,17 +773,27 @@ arm_unmask_irq(uintptr_t irq)
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{
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u_int32_t mask;
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if (irq >= S3C24X0_INT_EXT(0) && irq <= S3C24X0_INT_EXT(3)) {
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/* External interrupt 0..3 are directly mapped to irq 0..3 */
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irq -= S3C24X0_EXTIRQ_MIN;
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}
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if (irq < S3C24X0_SUBIRQ_MIN) {
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mask = bus_space_read_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK);
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mask &= ~(1 << irq);
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bus_space_write_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask);
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} else {
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} else if (irq < S3C24X0_EXTIRQ_MIN) {
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mask = bus_space_read_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK);
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mask &= ~(1 << (irq - S3C24X0_SUBIRQ_MIN));
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bus_space_write_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask);
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} else {
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mask = bus_space_read_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK);
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mask &= ~(1 << (irq - S3C24X0_EXTIRQ_MIN));
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bus_space_write_4(&s3c2xx0_bs_tag,
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s3c2xx0_softc->sc_intctl_ioh, GPIO_EINTMASK, mask);
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}
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}
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@ -207,7 +207,10 @@
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#define S3C24X0_INT_BFLT 7 /* Battery fault */
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#define S3C24X0_INT_8_23 5 /* Ext int 8..23 */
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#define S3C24X0_INT_4_7 4 /* Ext int 4..7 */
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#define S3C24X0_INT_EXT(n) (n) /* External interrupt [3:0] for 24{1,4}0 */
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#define S3C24X0_INT_3 3
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#define S3C24X0_INT_2 2
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#define S3C24X0_INT_1 1
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#define S3C24X0_INT_0 0
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/* 24{1,4}0 has more than 32 interrupt sources. These are sub-sources
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* that are OR-ed into main interrupt sources, and controlled via
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@ -230,6 +233,15 @@
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#define S3C24X0_INT_TXD0 (S3C24X0_SUBIRQ_MIN+1) /* UART0 Tx */
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#define S3C24X0_INT_RXD0 (S3C24X0_SUBIRQ_MIN+0) /* UART0 Rx */
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/*
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* Support for external interrupts. We use values from 48
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* to allow new CPU's to allocate new subirq's.
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*/
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#define S3C24X0_EXTIRQ_MIN 48
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#define S3C24X0_EXTIRQ_COUNT 24
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#define S3C24X0_EXTIRQ_MAX (S3C24X0_EXTIRQ_MIN + S3C24X0_EXTIRQ_COUNT - 1)
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#define S3C24X0_INT_EXT(n) (S3C24X0_EXTIRQ_MIN + (n))
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/* DMA controller */
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/* XXX */
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