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Don't access the reserved registers %dr4 and %dr5 on i386.
On the original i386, %dr[4-5] were unimplemented but not very clearly reserved, so debuggers read them to print them. i386 was still doing this. On the original athlon64, %dr[4-5] are documented as reserved but are aliased to %dr[6-7] unless CR4_DE is set, when accessing them traps. On 2 of my systems, accessing %dr[4-5] trapped sometimes. On my Haswell system, the apparent randomness was because the boot CPU starts with CR4_DE set while all other CPUs start with CR4_DE clear. FreeBSD doesn't support the data breakpoints enabled by CR4_DE and it never changes this flag, so the flag remains different across CPUs and the behaviour seemed inconsistent except while booting when the CPU doesn't change. The invalid accesses broke: - read access for printing the registers in ddb "show watches" on CPUs with CR4_DE set - read accesses in fill_dbregs() on CPUs with CR4_DE set. This didn't implement panic(3) since the user case always skipped %dr[4-5]. - write accesses in set_dbregs(). This also didn't affect userland. When it didn't trap, the aliasing made it fragile. Don't print the dummy (zero) values of %dr[4-5] in "show watches" for i386 or amd64. Fix style bugs near this printing. amd64 also has space in the dbregs struct for the reserved %dr[8-15] and already didn't print the dummy values for these, and never accessed any of the 10 reserved debug registers. Remove cpufuncs for making the invalid accesses. Even amd64 had these.
This commit is contained in:
Bruce Evans
parent
469ec1eb6a
commit
ff17a6773e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=315454
@ -575,7 +575,7 @@ watchtype_str(type)
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void
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db_md_list_watchpoints()
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db_md_list_watchpoints(void)
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{
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struct dbreg d;
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int i, len, type;
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@ -595,7 +595,7 @@ db_md_list_watchpoints()
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len++;
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db_printf(" %-5d %-8s %10s %3d ",
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i, "enabled", watchtype_str(type), len);
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db_printsym((db_addr_t)DBREG_DRX((&d), i), DB_STGY_ANY);
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db_printsym((db_addr_t)DBREG_DRX(&d, i), DB_STGY_ANY);
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db_printf("\n");
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} else {
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db_printf(" %-5d disabled\n", i);
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@ -603,9 +603,9 @@ db_md_list_watchpoints()
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}
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db_printf("\ndebug register values:\n");
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for (i = 0; i < 8; i++) {
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db_printf(" dr%d 0x%016lx\n", i, DBREG_DRX((&d), i));
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}
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for (i = 0; i < 8; i++)
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if (i != 4 && i != 5)
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db_printf(" dr%d 0x%016lx\n", i, DBREG_DRX(&d, i));
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db_printf("\n");
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}
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@ -758,34 +758,6 @@ load_dr3(uint64_t dr3)
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__asm __volatile("movq %0,%%dr3" : : "r" (dr3));
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}
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static __inline uint64_t
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rdr4(void)
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{
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uint64_t data;
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__asm __volatile("movq %%dr4,%0" : "=r" (data));
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return (data);
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}
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static __inline void
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load_dr4(uint64_t dr4)
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{
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__asm __volatile("movq %0,%%dr4" : : "r" (dr4));
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}
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static __inline uint64_t
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rdr5(void)
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{
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uint64_t data;
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__asm __volatile("movq %%dr5,%0" : "=r" (data));
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return (data);
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}
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static __inline void
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load_dr5(uint64_t dr5)
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{
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__asm __volatile("movq %0,%%dr5" : : "r" (dr5));
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}
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static __inline uint64_t
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rdr6(void)
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{
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@ -863,8 +835,6 @@ void load_dr0(uint64_t dr0);
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void load_dr1(uint64_t dr1);
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void load_dr2(uint64_t dr2);
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void load_dr3(uint64_t dr3);
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void load_dr4(uint64_t dr4);
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void load_dr5(uint64_t dr5);
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void load_dr6(uint64_t dr6);
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void load_dr7(uint64_t dr7);
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void load_fs(u_short sel);
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@ -887,8 +857,6 @@ uint64_t rdr0(void);
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uint64_t rdr1(void);
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uint64_t rdr2(void);
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uint64_t rdr3(void);
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uint64_t rdr4(void);
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uint64_t rdr5(void);
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uint64_t rdr6(void);
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uint64_t rdr7(void);
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uint64_t rdtsc(void);
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@ -735,7 +735,7 @@ watchtype_str(type)
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void
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db_md_list_watchpoints()
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db_md_list_watchpoints(void)
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{
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struct dbreg d;
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int i, len, type;
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@ -751,7 +751,7 @@ db_md_list_watchpoints()
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len = DBREG_DR7_LEN(d.dr[7], i);
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db_printf(" %-5d %-8s %10s %3d ",
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i, "enabled", watchtype_str(type), len + 1);
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db_printsym((db_addr_t)DBREG_DRX((&d), i), DB_STGY_ANY);
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db_printsym((db_addr_t)DBREG_DRX(&d, i), DB_STGY_ANY);
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db_printf("\n");
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} else {
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db_printf(" %-5d disabled\n", i);
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@ -759,10 +759,8 @@ db_md_list_watchpoints()
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}
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db_printf("\ndebug register values:\n");
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for (i = 0; i < 8; i++) {
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db_printf(" dr%d 0x%08x\n", i, DBREG_DRX((&d), i));
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}
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for (i = 0; i < 8; i++)
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if (i != 4 && i != 5)
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db_printf(" dr%d 0x%08x\n", i, DBREG_DRX(&d, i));
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db_printf("\n");
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}
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@ -2901,8 +2901,6 @@ fill_dbregs(struct thread *td, struct dbreg *dbregs)
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dbregs->dr[1] = rdr1();
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dbregs->dr[2] = rdr2();
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dbregs->dr[3] = rdr3();
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dbregs->dr[4] = rdr4();
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dbregs->dr[5] = rdr5();
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dbregs->dr[6] = rdr6();
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dbregs->dr[7] = rdr7();
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} else {
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@ -2911,11 +2909,11 @@ fill_dbregs(struct thread *td, struct dbreg *dbregs)
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dbregs->dr[1] = pcb->pcb_dr1;
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dbregs->dr[2] = pcb->pcb_dr2;
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dbregs->dr[3] = pcb->pcb_dr3;
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dbregs->dr[4] = 0;
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dbregs->dr[5] = 0;
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dbregs->dr[6] = pcb->pcb_dr6;
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dbregs->dr[7] = pcb->pcb_dr7;
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}
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dbregs->dr[4] = 0;
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dbregs->dr[5] = 0;
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return (0);
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}
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@ -2930,8 +2928,6 @@ set_dbregs(struct thread *td, struct dbreg *dbregs)
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load_dr1(dbregs->dr[1]);
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load_dr2(dbregs->dr[2]);
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load_dr3(dbregs->dr[3]);
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load_dr4(dbregs->dr[4]);
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load_dr5(dbregs->dr[5]);
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load_dr6(dbregs->dr[6]);
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load_dr7(dbregs->dr[7]);
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} else {
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@ -631,34 +631,6 @@ load_dr3(u_int dr3)
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__asm __volatile("movl %0,%%dr3" : : "r" (dr3));
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}
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static __inline u_int
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rdr4(void)
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{
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u_int data;
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__asm __volatile("movl %%dr4,%0" : "=r" (data));
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return (data);
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}
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static __inline void
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load_dr4(u_int dr4)
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{
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__asm __volatile("movl %0,%%dr4" : : "r" (dr4));
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}
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static __inline u_int
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rdr5(void)
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{
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u_int data;
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__asm __volatile("movl %%dr5,%0" : "=r" (data));
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return (data);
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}
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static __inline void
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load_dr5(u_int dr5)
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{
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__asm __volatile("movl %0,%%dr5" : : "r" (dr5));
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}
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static __inline u_int
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rdr6(void)
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{
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@ -750,8 +722,6 @@ void load_dr0(u_int dr0);
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void load_dr1(u_int dr1);
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void load_dr2(u_int dr2);
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void load_dr3(u_int dr3);
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void load_dr4(u_int dr4);
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void load_dr5(u_int dr5);
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void load_dr6(u_int dr6);
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void load_dr7(u_int dr7);
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void load_fs(u_short sel);
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@ -773,8 +743,6 @@ u_int rdr0(void);
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u_int rdr1(void);
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u_int rdr2(void);
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u_int rdr3(void);
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u_int rdr4(void);
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u_int rdr5(void);
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u_int rdr6(void);
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u_int rdr7(void);
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uint64_t rdtsc(void);
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