rounding (impl. dep. #55), the SPARC JPS1 responsible for SPARC64 and
UltraSPARC processors defines that in all cases tinyness is detected
before rounding, therefore rounding up to the smallest normalised
number should set the underflow flag.
- If an infinite result is rounded down, the result should have an
exponent 1 less than the value for infinity.
PR: 144900
Submitted by: Peter Jeremy
MFC after: 3 days
operands but not for double and extended double ones. Instead of trying
to fix the macro just nuke it and unroll the loops in the correct way
though as extended double operands turn out to be the only special case.
- For FxTO{s,d,q} the source operand is int64 so rs2 has to be re-decoded
after setting type accordingly as it's generally decoded using the low
2 bits as the type, which are 0 for these three instructions.
- Similarly, in case of F{s,d,q}TOx the target is int64 so rd has to be
re-decoded using not only the operand mask appropriate for int64 but
also the correct register number encoding.
- Use const where appropriate.
- Wrap long lines.
Submitted by: Peter Jeremy (partly)
MFC after: 3 days
flags appropriately. The next step is to make it raise a SIGFPE if
any exceptions are unmasked.
Thanks to remko for access to a sparc64 box for testing.
conversion of negative numbers to always result in -1.
While at it, rearrange the nearby comment so it fits in 80 chars per line,
like the rest of this file does.
PR: 107130
MFC after: 1 day
Compliance Definition. On sparc64, GCC emits _Qp_cmp() calls for its
__builtin_isfoo() functions which are used for C99's isfoo() macros.
Approved by: re(dwhite)
PR: 73782
long (and unsigned long long) to long double conversions.
- Add a parameter that specifies the position of the sign bit to the _QP_TTOQ
macro, previously it always looked at bit 31. Pass a negative number to
disable sign inspection for unsigned types. This fixes _Qp_xtoq(),
_Qp_uitoq() and _Qp_uxtoq().
- In the functions __fpu_itof() and __fpu_xtof(), look at the sign bit to
decide whether we're doing a conversion from an unsigned type. If so, don't
negate the mantissa if the integer exceeds the biggest signed number.
PR: 55773
Patch by: Stephen Paskaluk (based upon)
MFC after: 2 weeks
a floating point instruction into a 6-bit register number for
double and quad arguments.
Make use of the new INSFPdq_RN macro where apporpriate; this
is required for correctly handling the "high" fp registers
(>= %f32).
Fix a number of bugs related to the handling of the high registers
which were caused by using __fpu_[gs]etreg() where __fpu_[gs]etreg64()
should be used (the former can only access the low, single-precision,
registers).
Submitted by: tmm
on long double, which are not implemented in hardware on any UltraSPARC
chip that I know of. This just calls into the existing floating point
emulator, which is still needed to emulate other floating point operations
in certain conditions. Without this gcc has to generate the quad floating
point instructions directly, which sometimes causes internal compiler
errors.
Reviewed by: tmm
using these to load long doubles, but they aren't implemented in hardware
on (at least) UltraSPARC I and II machines.
Emulate popc in the user trap handler as well.
Re-arrange slightly to make support functions more accessible.
Reviewed by: tmm
and add some compatibility defines. Add fields for ins and locals to
struct reg also for the same reason; these aren't filled in yet because
getting at those registers sucks and I'd rather not save them in the
trapframe just for this. Reorder struct reg to be ABI compatible as
well. Add needed include of machine/emul.h.
This gets pmdb (poor man's debugger) from OpenBSD mostly compiling but it
doesn't work yet :(
support for fcmp and fcmpe instructions with a condition code
specification other than %fcc0.
This (primarily the first part) seems to fix a lot of problems that
people were seeing, e.g. perl and gawk failures.
Reported and analyzed by: wollman
