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Commit Graph

1919 Commits

Author SHA1 Message Date
Andrew Turner
3184de419d Stop calling fdt_immr_addr from the xlp startup code. It's used to set
fdt_immr_{va,pa,size}, but these are not used outside a single ARM SoC.
2016-01-22 12:00:56 +00:00
Brooks Davis
bd3f34d4ba Shift saved floating point registers up in jmp_buf.
sigmask_t is 128-bits so requires two slots.

Approved by:	CheriBSD (93699cb9b6e73980ac369e379cea9772c9494ccc)
MFC after:	1 week
Sponsored by:	DARPA, AFRL
2016-01-20 22:23:08 +00:00
Dmitry Chagin
038c720553 Implement vsyscall hack. Prior to 2.13 glibc uses vsyscall
instead of vdso. An upcoming linux_base-c6 needs it.

Differential Revision:  https://reviews.freebsd.org/D1090

Reviewed by:	kib, trasz
MFC after:	1 week
2016-01-09 20:18:53 +00:00
Ian Lepore
69dcb7e771 Make the 'env' directive described in config(5) work on all architectures,
providing compiled-in static environment data that is used instead of any
data passed in from a boot loader.

Previously 'env' worked only on i386 and arm xscale systems, because it
required the MD startup code to examine the global envmode variable and
decide whether to use static_env or an environment obtained from the boot
loader, and set the global kern_envp accordingly.  Most startup code wasn't
doing so.  Making things even more complex, some mips startup code uses an
alternate scheme that involves calling init_static_kenv() to pass an empty
buffer and its size, then uses a series of kern_setenv() calls to populate
that buffer.

Now all MD startup code calls init_static_kenv(), and that routine provides
a single point where envmode is checked and the decision is made whether to
use the compiled-in static_kenv or the values provided by the MD code.

The routine also continues to serve its original purpose for mips; if a
non-zero buffer size is passed the routine installs the empty buffer ready
to accept kern_setenv() values.  Now if the size is zero, the provided buffer
full of existing env data is installed.  A NULL pointer can be passed if the
boot loader provides no env data; this allows the static env to be installed
if envmode is set to do so.

Most of the work here is a near-mechanical change to call the init function
instead of directly setting kern_envp.  A notable exception is in xen/pv.c;
that code was originally installing a buffer full of preformatted env data
along with its non-zero size (like mips code does), which would have allowed
kern_setenv() calls to wipe out the preformatted data.  Now it passes a zero
for the size so that the buffer of data it installs is treated as
non-writeable.
2016-01-02 02:53:48 +00:00
Adrian Chadd
50bf167022 Fix missing path conversion from the previous commit to shuffle mdio around.
It turns out the recent work to cut down the number of atheros kernels built
didnt include one with ARGE_MDIO defined..
2015-12-27 07:39:44 +00:00
Kevin Lo
ddb1359877 Fix typo (s/harware/hardware/) 2015-12-25 14:51:36 +00:00
Adrian Chadd
d5c2c0134b Add initial configuration files for the MT7620 and RT5350 SoCs.
These are all works in progress.  Notably - no wifi support just yet!

I've booted the MT7620 on a TP-Link Archer C2 via tftpboot.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-25 00:58:41 +00:00
Adrian Chadd
43747185a0 Add missing device rename. 2015-12-24 22:27:00 +00:00
Adrian Chadd
ba1ae59a17 [rt305x] Add initial RT5350 and MT7620 glue.
* Add in chipset awareness to the obio bus layout (ie, which devices are
  where);
* Add in some USB OTG changes to be aware of the newer stuff;
* Add in a configurable primary console - some chips use the normal UART,
  some use UARTLITE.

Tested (by Stanislav);

* RT3050 (NFS)
* RT5350 (NFS, MFS)
* MT7620 (USB)

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-24 18:40:10 +00:00
Adrian Chadd
f9133e1d31 [MT7620] add ehci/ohci USB support.
The newer chips don't use OTG; they're more traditional USB.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-24 18:36:08 +00:00
Adrian Chadd
0f4da49e43 [MT7620] add SPI device support.
Submitted by:	Alexander A. Mityaev <sansan@adm.ua>
2015-12-24 18:34:46 +00:00
Adrian Chadd
f3213f44b2 [rt305x] add PCI bus / resource allocation code for the MT7620.
This is based on the sys/arm/mv/ pci resource/allocation code.

Submitted by:	Stanislav Galabov <galabov@gmail.com>
2015-12-24 18:33:08 +00:00
Adrian Chadd
c40db2e376 [rt305x] add register space definitions for later generation chips.
This adds definitions for the MT5350 and MT7620 SoCs.

Submitted by:	Stanislav Galabov <galabov@gmail.com>
2015-12-24 18:31:55 +00:00
Adrian Chadd
1bbf40fab5 [rt305x] Prepare for the upcoming regime change - add RT305x options.
Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-24 18:30:04 +00:00
Adrian Chadd
d06ccd84b3 Begin the initial support for the mips1004kc core.
* add build option;
* add initial coherence manager config register bits;
* use the right hazard instruction (ehb);
* add page attributes.

Tested:

* MT7621A SoC (not yet in-tree)

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-24 15:52:21 +00:00
Adrian Chadd
67f670190f Add missing \n.
Otherwise you end up with:

Cache info:
  picache_stride    = 4096
  picache_loopcount = 16
  pdcache_stride    = 4096
  pdcache_loopcount = 8
cpu0: MIPS Technologies processor v80.150
  MMU: Standard TLB, 32 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes)
  L1 i-cache: 4 ways of 512 sets, 32 bytes per line
  L1 d-cache: 4 ways of 256 sets, 32 bytes per line
  L2 cache: disabled  Config1=0xbee3519e<PerfCount,WatchRegs,MIPS16,EJTAG>
  Config2=0x80000000
  Config3=0x2420

Tested:

* MT7620 SoC
2015-12-24 04:37:19 +00:00
Adrian Chadd
7b61491a8d [mips] Add TLB pagemask probing code, and print out the allowable page sizes.
This is from Stacey's work on larger kernel stack sizes for MIPS.  Thanks!

Submitted by:	sson
2015-12-22 15:59:41 +00:00
Ian Lepore
9b4d9c162a Add a mips implementation of OF_decode_addr(). 2015-12-21 18:19:14 +00:00
Adrian Chadd
aefdcce869 [mips] print out l2 cache configuration if it exists.
The Ingenic JZ7480 SoC that is on the Imagination Technologies CI20 board
has an L2 cache:

Cache info:
  picache_stride    = 4096
  picache_loopcount = 8
  pdcache_stride    = 4096
  pdcache_loopcount = 8
cpu0: Ingenic Xburst processor v79.2
  MMU: Standard TLB, 32 entries
  L1 i-cache: 8 ways of 128 sets, 32 bytes per line
  L1 d-cache: 8 ways of 128 sets, 32 bytes per line
  L2 cache: 8 ways of 256 sets, 128 bytes per line, 256 KiB total size
  Config1=0xbe67338b<WatchRegs,EJTAG,FPU>
  Config2=0x80000267
  Config3=0x20
2015-12-21 01:48:16 +00:00
Ian Lepore
f3be407b23 Tidy up mips ofw_machdep.h. Don't include openfirm.h because openfirm.h
is what includes machine/ofw_machdep.h.  Don't declare OF_decode_addr();
it isn't implemented yet on mips and the declaration for it is about to
be commonized into openfirm.h.
2015-12-20 19:09:12 +00:00
Alan Cox
c869e67208 Introduce a new mechanism for relocating virtual pages to a new physical
address and use this mechanism when:

1. kmem_alloc_{attr,contig}() can't find suitable free pages in the physical
   memory allocator's free page lists.  This replaces the long-standing
   approach of scanning the inactive and inactive queues, converting clean
   pages into PG_CACHED pages and laundering dirty pages.  In contrast, the
   new mechanism does not use PG_CACHED pages nor does it trigger a large
   number of I/O operations.

2. on 32-bit MIPS processors, uma_small_alloc() and the pmap can't find
   free pages in the physical memory allocator's free page lists that are
   covered by the direct map.  Tested by: adrian

3. ttm_bo_global_init() and ttm_vm_page_alloc_dma32() can't find suitable
   free pages in the physical memory allocator's free page lists.

In the coming months, I expect that this new mechanism will be applied in
other places.  For example, balloon drivers should use relocation to
minimize fragmentation of the guest physical address space.

Make vm_phys_alloc_contig() a little smarter (and more efficient in some
cases).  Specifically, use vm_phys_segs[] earlier to avoid scanning free
page lists that can't possibly contain suitable pages.

Reviewed by:	kib, markj
Glanced at:	jhb
Discussed with:	jeff
Sponsored by:	EMC / Isilon Storage Division
Differential Revision:	https://reviews.freebsd.org/D4444
2015-12-19 18:42:50 +00:00
Adrian Chadd
191f543e29 [qca953x] remove unneeded initialisation.
This was copied from another chip file and it's not required on Honeybee.

Tested:

* AP143, QCA9531 SoC.

Obtained from: OpenWRT
2015-12-15 04:45:00 +00:00
Adrian Chadd
2365b69ef7 [ar71xx] always count interrupts, spurious or otherwise.
This aids in debugging.
2015-12-15 04:44:06 +00:00
Adrian Chadd
ae3f04a5df [arge] add a comment about needing mdio busses in order to use the interface.
This is a holdover from how reset is handled in the ARGE_MDIO world.
You need to define the mdio bus device if you want to use the ethernet
device or the arge setup path doesn't bring the MAC out of reset.
2015-12-15 04:43:28 +00:00
Warner Losh
14f4e15704 Correct the CONFIG0_VI value. According to
http://www.t-es-t.hu/download/mips/md00090c.pdf this is bit 3 of the
config0 word, not bit 2.  This should fix virtually indexed caches
(relatively new in the MIPS world, so no current platforms used this
and current code just uses it as an optimization). It was causing
false positives on newer platforms that default to large values for
the kseg0 cache coherency attribute.

Submitted by: Stanislav Galabov
PR:	205249
2015-12-11 16:51:04 +00:00
Mark Johnston
711fbd17ec Add helper functions proc_readmem() and proc_writemem().
These helper functions can be used to read in or write a buffer from or to
an arbitrary process' address space. Without them, this can only be done
using proc_rwmem(), which requires the caller to fill out a uio. This is
onerous and results in code duplication; the new functions provide a simpler
interface which is sufficient for most existing callers of proc_rwmem().

This change also adds a manual page for proc_rwmem() and the new functions.

Reviewed by:	jhb, kib
Differential Revision:	https://reviews.freebsd.org/D4245
2015-12-07 21:33:15 +00:00
Adrian Chadd
cd15736797 Add support for the integrated wifi for the QCA953x base config and
AP143.

Tested:

* AP143 reference design board
2015-11-29 05:49:49 +00:00
Konstantin Belousov
724f4b62b0 Remove sv_prepsyscall, sv_sigsize and sv_sigtbl members of the struct
sysent.

sv_prepsyscall is unused.

sv_sigsize and sv_sigtbl translate signal number from the FreeBSD
namespace into the ABI domain.  It is only utilized on i386 for iBCS2
binaries.  The issue with this approach is that signals for iBCS2 were
delivered with the FreeBSD signal frame layout, which does not follow
iBCS2.  The same note is true for any other potential user if
sv_sigtbl.  In other words, if ABI needs signal number translation, it
really needs custom sv_sendsig method instead.

Sponsored by:	The FreeBSD Foundation
2015-11-28 08:49:07 +00:00
Svatopluk Kraus
eae22c4430 Revert r291142.
The not quite consistent logic for bounce pages allocation is utilizited
by re(4) interface which can hang now.

Approved by:	kib (mentor)
2015-11-23 11:19:00 +00:00
Adrian Chadd
181f3573ee [mips]: Don't hard-code PHYS_AVAIL_ENTRIES. 2015-11-22 02:40:19 +00:00
Svatopluk Kraus
6fa7734d6f Fix BUS_DMA_MIN_ALLOC_COMP flag logic. When bus_dmamap_t map is being
created for bus_dma_tag_t tag, bounce pages should be allocated
only if needed.

Before the fix, they were allocated always if BUS_DMA_COULD_BOUNCE flag
was set but BUS_DMA_MIN_ALLOC_COMP not. As bounce pages are never freed,
it could cause memory exhaustion when a lot of such tags together with
their maps were created.

Note that there could be more maps in one tag by current design.
However BUS_DMA_MIN_ALLOC_COMP flag is tag's flag. It's set after
bounce pages are allocated. Thus, they are allocated only for first
tag's map which needs them.

Approved by:	kib (mentor)
2015-11-21 19:55:01 +00:00
Adrian Chadd
d6ebaf0a5e mips: teach the malta platform about extended memory.
Extended memory here is "physical memory above 256MB".
"memsize" in the environment only grows to 256MB; "ememsize" is the entire
memory range.  Extended memory shows up at physical address 0x90000000.

This allows for malta64 VMs to be created with > 256MB RAM, all the way
up to 2GB RAM.

Tested:

* qemu-devel package; qemu-system-mips64 -m 2048 (and -m 256 to test the
  no-ememsize case.)

TODO:

* testing mips32 with > 256MB RAM.

Reviewed by:	imp
2015-11-21 00:22:47 +00:00
Warner Losh
29d1144aeb Mark the mostly redundant kernels that just pull
in something from _BASE as NO_UNIVERSE

Differential Revision: https://reviews.freebsd.org/D4200
2015-11-19 01:58:12 +00:00
Adrian Chadd
e69ad1c9b3 Add the QCA9533 base configuration file and an example configuration
for the AP143.

Wifi doesn't work on the QCA9533 board, but basic ethernet/ethernet
and ethernet switch support does work.

The AP143 has 32MB RAM and 4MB flash, so this was tested with a USB
rootfs.

Tested:

* QCA9533v2, AP143 reference design board.
2015-11-18 06:25:25 +00:00
Allan Jude
a065797aa4 Add a kernel config for the Onion Omega
Small $25 IoT device, 400mhz Atheros cpu, Atheros WiFi and Ethernet
18 GPIOs, and support for Relay, Servo, and OLED expansion
https://onion.io/omega/

Reviewed by:	adrian
Approved by:	bapt (mentor)
Relnotes:	yes
Sponsored by:	ScaleEngine Inc.
Differential Revision:	https://reviews.freebsd.org/D4188
2015-11-17 21:02:27 +00:00
Adrian Chadd
27ddeed4a3 Add QCA9533 to the list of SoCs that require IRQ's be ACKed. 2015-11-16 06:15:01 +00:00
Adrian Chadd
d6141d33bc Add initial support for the QCA953x ("Honeybee") from Qualcomm Atheros.
The QCA953x SoC is an integrated 2x2 2GHz 11n + MIPS24k core, with
a 5 port FE switch, gige WAN port, and all the same stuff you'd find on
its predecessor - the AR9331.

However, buried deep in here somewhere is also a PCIe EP/RC for various
applications and some other weird bits I don't yet know about.

This is enough to get the reference board up and booting.  I haven't yet
had it pass lots of packets - I need to finalise the ethernet switch
bits and the GMAC configuration (ie, how the ethernet ports and switch
are wired up) and I'll bring that in when I commit the base configuration
files to use the thing.

The wifi stuff will come much later.  I have to port that support from
Linux ath9k and extend our vendor HAL to support it.

The reference board (AP143) comes with 32MB RAM and 4MB flash, so in order
to use it I need to get USB working fully so I can run root from there.

Thankyou to Qualcomm Atheros for access to the reference design board.

Details:

* Add register definitions from openwrt;
* It looks like a QCA955x but shrunk down to a QCA933x footprint, so
  use the QCA955x bits and fix up the clock detection code to do the
  QCA953x bits (they're very subtly different);
* Teach GPIO about it;
* Teach EHCI about it;
* Teach if_arge about it;
* Teach the CPU detection code about it.

Tested:

* AP143, QCA9533v2 SoC

Obtained from:	Linux, Linux OpenWRT
2015-11-16 04:28:00 +00:00
Adrian Chadd
3036d0128e Remove this; it's also in sys/conf/files.mips. 2015-11-03 21:03:26 +00:00
Adrian Chadd
d24766cc51 mips: rate limit the trap handler output; add pid/tid/program name.
I discovered that we're logging each trap, which gets pretty spendy;
and there wasn't any further information on the pid/tid/progname involved.

I originally noticed this because I don't attach anything to /dev/log and so
the log() output stays going to the kernel.  That's an oops on my part, but
I'm glad I did it.

This commit adds the following:

* a rate limiter, which could do with some eyeballs/ideas on how to
  make it more predictable on SMP;
* log pid, tid, progname (comm) as part of the output.

I now get output like this:

Unaligned Load Word: pid=621 (pmcstat), tid=100060, pc=0xffffffff803ae898, badvaddr=0x40a10055
Unaligned Load Word: pid=621 (pmcstat), tid=100060, pc=0xffffffff803ae898, badvaddr=0x40a10051
Unaligned Load Word: pid=621 (pmcstat), tid=100060, pc=0xffffffff803ae898, badvaddr=0x40a1004d
Unaligned Load Word: pid=602 (login), tid=100042, pc=0xffffffff803ae898, badvaddr=0x401159
Unaligned Load Word: pid=602 (login), tid=100042, pc=0xffffffff803ae898, badvaddr=0x401155
Unaligned Load Word: pid=602 (login), tid=100042, pc=0xffffffff803ae898, badvaddr=0x401151

.. which makes it much easier to start figuring out what/where to fix.

The pc looks suss (it looks like it's in kernel space); I'll dig into that one next.

Tested:

* AR9331 SoC (Carambola2)
2015-11-02 03:36:15 +00:00
Adrian Chadd
f2c42f690f mips: do mips_sync() on sync operations to uncachable memory.
mips24k/mips74k document that we need an explicit SYNC so to order
things correctly, even with access to uncachable memory.
We were doing calls to SYNC in the cache ops (inv, wbinv) but we
weren't doing it for uncachable memory.
2015-10-31 00:29:26 +00:00
Adrian Chadd
941f53b9a9 mips74k: use cache-writeback for memory, not writethrough.
When I ported this code from netbsd I was .. slightly mips74k greener.
I used writethrough because (a) it's what netbsd did, and (b) if I used
writethrough then things "didn't work."

Fast-forward a couple years, more MIPS hacking and a whole lot more
understanding of the bus APIs (the last few commits notwithstanding;
it's been a long week, ok?) and I have this working for arge,
argemdio, spi and ath.  Hans has it working for USB.  The ath barrier
code will come in a later commit.

This gets the routing throughput up from 220mbit -> 337mbit.
I'm sure the bridging throughput will be similarly improved.

Tested:

* QCA955x SoC, routing workload.
2015-10-31 00:04:44 +00:00
Adrian Chadd
f17acb5fbe arge_mdio: fix barriers; correctly check MII indicator register.
* use barriers in a slightly better fashion.  You can blame this
  glass of whiskey on putting barriers in the wrong spot.  Grr adrian.

* steal/rewrite the mdio busy check from ag7100 from openwrt and
  refactor the existing code out.  This is .. more correct.

This seems to fix the boot-to-boot variation that I've been seeing
and it quietens the switch port status flapping.

Tested:

* QCA9558 SoC (AP135.)

Obtained from:	Linux OpenWRT
2015-10-30 23:59:52 +00:00
Adrian Chadd
78e1370bbc arge: fix barrier macro. 2015-10-30 23:57:20 +00:00
Adrian Chadd
29f88ae706 arge: attempt to close a transmit race by only enabling the descriptor at the end of setup.
This driver and the linux ag71xx driver both treat the transmit ring
as a circular linked list of descriptors.  There's no "end" pointer
that is ever NULL - instead, it expects the MAC to hit a finished
descriptor (ARGE_DESC_EMPTY) and stop.

Now, since it's a circular buffer, we may end up with the hardware
hitting the beginning of our multi-descriptor frame before we've finished
setting it up. It then DMA's it in, starts sending it, and we finish
writing out the new descriptor.  The hardware may then write its
completion for the next descriptor out; then we do, and when we next
read it it'll show up as "not done" and transmit completion stops.

This unfortunately manifests itself as the transmit queue always
being active and a massive TX interrupt storm.  We need to actively
ACK packets back from the transmit engine and if we don't (eg because
we think the transmit isn't finished but it is) then the unit will
just keep generating interrupts.

I hit this finally with the below testing setup.  This fixed it for me.

Strictly speaking I should put in a sync in between writing out all of
the descriptors and writing out that final descriptor.

Tested:

* QCA9558 SoC (AP135 reference board) w/ arge1 + vlans acting as a
  router, and iperf -d (tcp, bidirectional traffic.)

Obtained from:	Linux OpenWRT (ag71xx_main.c.)
2015-10-30 23:18:02 +00:00
Adrian Chadd
70487bd29b arge: just use 1U since it's a 32 bit unsigned destination value. 2015-10-30 23:09:08 +00:00
Adrian Chadd
a73d5cc09f arge: do an explicit flush between updating the TX ring and starting transmit.
The MIPS busdma sync operations currently are a big no-op on coherent memory.
This isn't strictly correct behaviour as we need a SYNC in here to ensure that
the writes have finished and are visible in main memory before the MMIO accesses
occur.  This will have to be addressed in a later commit.

But, before that happens, let's at least do a flush here to make things
more "correct".

This is required for even remotely sensible behaviour on mips74k with
write-through memory enabled.
2015-10-30 23:07:32 +00:00
Adrian Chadd
ab2477c2c1 arge_mdio: add explicit read barriers for MDIO_READs.
The mips74k programmers guide notes that reads can be re-ordered, even
uncached ones, so we need an explicit SYNC between them.

Yes, this is a case of a driver author actively doing a bus barrier
operation.

This ends up being necessary when the mips74k core is run in write-back
mode rather than write-through mode.  That's coming in an upcoming
commit.

Tested:

* mips74k, QCA9558 SoC (AP135 reference board), arge<->arge interface
  routing traffic tests.
2015-10-30 23:00:47 +00:00
Adrian Chadd
47ed24efe2 arge: ensure there's enough space in the TX ring before attempting to
send frames.

This matches the other check for space.

"enough" is a misnomer, for "reasons".  The biggest reason is that
the TX ring is actually a circular linked list, with no head/tail pointers.
This is just a bit more headroom between head/tail so we have time to
schedule frames before we hit where the hardware is at.

Ideally this would be tunable and a little larger.
2015-10-30 22:55:41 +00:00
Adrian Chadd
3b8a3b85eb arge: do a read-after-write on all arge register writes, not just MDIO writes.
This flushes out the write to the system before anything continues.

The mips74k guide, chapter 3.3.3 (write gathering) notes that writes
can be buffered in FIFOs - even uncached ones - so we can't guarantee
the device has felt its effects.  Now, since we're all lazy driver
authors and don't pepper read/write barriers everywhere, fake it here.

tested:

* mips74k - QCA9558 SoC (AP135 reference board)
2015-10-30 22:53:30 +00:00
Adrian Chadd
948457f1be Oops - use the wrong array offset. 2015-10-28 23:39:33 +00:00