and hardware.
There is now another simple_lock around clock data/hardware accesses in
clock.c and microtime.s. It is my belief that this is the only area
sio/cy might stumble into during an unblocked INTerrupt. Thus I separated
the sio/cy code from the generic disable_intr()/enable_intr() routines.
Controlled by smptests.h: USE_COMLOCK, ON by default.
Add a simplelock to deal with disable_intr()/enable_intr() as used in UP kernel.
UP kernel expects that this is enough to guarantee exclusive access to
regions of code bracketed by these 2 functions.
Add a simplelock to bracket clock accesses in clock.c: clock_lock.
Help from: Bruce Evans <bde@zeta.org.au>
Several new fine-grained locks.
New FAST_INTR() methods:
- separate simplelock for FAST_INTR, no more giant lock.
- FAST_INTR()s no longer checks ipending on way out of ISR.
sio made MP-safe (I hope).
speed using the boot blocks, instead of a hardcoded value stuck in the
kernel. This way, you can have systems using the same kernel but different
console speeds.
Add a sysctl entry for changing the system console speed.
Lock the user tty speed to match the system console speed.
Nuke CONSPEED.
Reviewed by: bde
There are various options documented in i386/conf/LINT, there is more to
come over the next few days.
The kernel should run pretty much "as before" without the options to
activate SMP mode.
There are a handful of known "loose ends" that need to be fixed, but
have been put off since the SMP kernel is in a moderately good condition
at the moment.
This commit is the result of the tinkering and testing over the last 14
months by many people. A special thanks to Steve Passe for implementing
the APIC code!
(see LINT). There is a new low-level console type that is more suitable
for use with gdb-remote.
Fixed setting of speed at probe time for the serial console (if any).
Reviewed by: dfr
with <= 100 usec between each character arrival time. This didn't happen
until rev.1.75 of clock.c because DELAY(100) used to delay for closer to
80 usec than 100 usec, and the minimum time between character arrivals is
87.8 usec at the maximum supported speed of 115200 bps 8N1.
Clear DCD timestamp flag on close (the input timestamp flag is already
cleared).
- don't uselessly initialize the fifo "DMA" bit at attach time.
- initialize the fifo "DMA" bit at open time. Without this, the device
interrupts for every character received, reducing input performance
to that of an 8250.
- don't uselessly initialize the fifo trigger level to 8 (scaled to
256) at attach time.
- don't scale the fifo trigger level to 512 bytes. The driver's pseudo-
dma buffer has size 256, so it can't handle bursts of size 512 or 256.
It should be able to handle the second lowest ftl (2 scaled to 64).
- don't reset the fifos in siostop(). Reset triggers a hardware bug
involving wedging of the output interrupt bit This workaround
unfortunately requires ESP support to be configured.
This will make a number of things easier in the future, as well as (finally!)
avoiding the Id-smashing problem which has plagued developers for so long.
Boy, I'm glad we're not using sup anymore. This update would have been
insane otherwise.
are always together with Framing Errors and they were incorrectly
treated as FE's and discarded.
Reorganized the BREAK/FE/PE tests.
Found by: NIST-PCTS
with sio devices (not perfectly, since there is no way to flush the tx
holding register on 8250-16450's. I'm not sure if resetting the fifos
flushes the tx shift register).
Reminded by: NIST-PCTS
is completely empty. There is no interrupt for output completion, so
poll for it every 10 ms after output is nearly complete. Now ttywait()
works right.
Reminded by: NIST-PCTS
almost complete control over RTS (control of its initial value is still
missing).
This fixes PR 1644 for sio.
The author of PR 1644 wants it in 2.1.6 and 2.2. This may be safe since
the complications are only in rarely used cases that I hope I've covered.
divisor latch registers if the registers wouldn't change.
Use the default console cfcr setting while setting the divisor
latch registers for console i/o. Input may be messed up by
transiently changing the cfcr.
Use a usual cfcr setting while setting the divisor latch registers
in the probe. This shouldn't matter, but this is not the place to
test the UART's handling of 5 bit words.
Removed a stale devfs comment.
instead of 0 if there is no input.
syscons.c:
Added missing spl locking in sccncheckc(). Return the same value as
sccngetc() would. It is wrong for sccngetc() to return non-ASCII, but
stripping the non-ASCII bits doesn't help.
Original version by John Hay.
Simplified timestamp code by reading the time exactly when necessary.
This may slow down the interrupt handler with extra calls to microtime(),
but only in bad configurations - the input fifo should normally be
disabled if timestamps on input are being used, since otherwise the
timestamp won't be precisely associated with any particular input event.
The interrupt handler remains slowed down by one test and branch for
each input (and now DCD change) event - avoiding this is not practical
yet.
The simplifications also fixed:
- timestamps for input sometimes being clobbered by output and modem
status interrupts.
- valid timestamps not being available unless the port is configured with
vector siointrts. siointrts no longer exists.
- compiler warnings about siointr* in some configurations.
Simplified timestamp and probe code by depending on recent changes in
microtime() and DELAY() to preserve the interrupt enable flag.
