this is is crucial at least for the latter.
What happens is that attaching uart(4) to scc(4) causes the SAB 82532 to
"receive" something and trigger a SER_INT_RXREADY interrupt, given that
at least fast/filter interrupts are already enabled. Prior to r253161,
uart_bus_ihand() was set up at this point and handled that condition,
i. e. read the RX FIFO and issued a Receive Message Complete.
Now, uart_bus_ihand() and uart_intr() are setup after attaching uart(4),
leaving the SER_INT_RXREADY interrupt triggered during the latter to
be handled by the iclear method. However, with that method not implement,
this in turn causes SAB 82532 to not issue any further SER_INT_RXREADY
interrupts until the RX FIFO is full again. Thus, 15 received bytes go
to nowhere, given that "the other half" of the RX FIFO is used for status
information. Hence, implementing sab82532_bfe_iclear() fixes things again.
Potentially, the same problem exists for QUICC.
- Remove unnecessary __RMAN_RESOURCE_VISIBLE.
- Remove a superfluous header.
- Use KOBJMETHOD_END.
- Mark unused arguments as such.
- Remove variables unused after initialization.
Reviewed by: marcel (earlier version)
one. Interestingly, these are actually the default for quite some time
(bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9)
since r52045) but even recently added device drivers do this unnecessarily.
Discussed with: jhb, marcel
- While at it, use DEVMETHOD_END.
Discussed with: jhb
- Also while at it, use __FBSDID.
total of 6 interrupt resources for scc(4) on macio(4). This
is 3 per channel, of which the 1st of each channel is the
interrupt associated with the SCC. The other 2 are for DMA
operation.
Change scc_bfe_attach() to accept an argument that's the
number of interrupts per channel (ipc) and change each bus
front-end (bfe) to pass that argument through a wrapper
for the device_attach method.
For now, we only allocate the 1st interrupt of each channel
to perserve behaviour.
The QUICC engine is found on various Freescale parts including MPC85xx, and
provides multiple generic time-division serial channel resources, which are in
turn muxed/demuxed by the Serial Communications Controller (SCC).
Along with core QUICC/SCC functionality a uart(4)-compliant device driver is
provided which allows for serial ports over QUICC/SCC.
Approved by: cognet (mentor)
Obtained from: Juniper
MFp4: e500
by driver backends to mark individual channels as enabled or not.
The default implementation of this method always mark channels as
enabled.
This method is currently not used, but is added with the PowerQUICC
in mind where the 2nd SCC channel can be disabled.
space range per channel, but rather the unshifted range. The
shifting depends on the bus. The hardcoded shift was specific
to the SBus on sparc64. The shifted range is now determined at
run-time. This fixes the mac-io attachment.
mac-io bus, we cannot setup FAST interrupt handlers. This because we
use spinlocks to protect the hardware and all interrupt resources are
assigned the same interrupt handler. When the interrupt handler is
invoked for interrupt X, it could be preempted for interrupt Y while
it was holding the lock (where X and Y are the interrupt resources
corresponding a single instance of this driver). This is a deadlock.
By only using a MPSAFE handler in that case we prevent preemption.
a different register shift and is fed by a different clock than
we use for UltraSPARC hardware. To deal with this, the regshft and
rclk fields in the class structure are removed and bus frontends
now pass the right regshft and rclk to the probe function where
they're put in the BAS and passed in to subordinate drivers.
controllers typically have multiple channels and support a number
of serial communications protocols. The scc(4) driver is itself
an umbrella driver that delegates the control over each channel
and mode to a subordinate driver (like uart(4)).
The scc(4) driver supports the Siemens SAB 82532 and the Zilog
Z8530 and replaces puc(4) for these devices.
