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10 Commits

Author SHA1 Message Date
Gleb Smirnoff
c8dfaf382f Mechanically convert to if_inc_counter(). 2014-09-19 03:51:26 +00:00
Gleb Smirnoff
1bffa9511f Use define from if_var.h to access a field inside struct if_data, 
that resides in struct ifnet.

Sponsored by:	Nginx, Inc.
 2014-08-30 19:55:54 +00:00
Bjoern A. Zeeb
eb665cf9e9 Fix whitspace indentation from spaces to tabs. 
No functional changes.

MFC after:	2 weeks
 2014-06-26 17:26:33 +00:00
Bjoern A. Zeeb
62820660cc Introduce opt_netfpga.h and allow setting NF10BMAC_64BIT from mips kernel 
configs.  Switch the BERI_NETFPGA_MDROOT to 64bit by default.

Give we have working interrupts also cleanup the extra polling CFLAGS from
the module Makefile.

MFC after:	2 weeks
 2014-06-26 17:20:45 +00:00
Bjoern A. Zeeb
4d8492c790 Allow switching between 32bit and 64bit bus width data access at compile 
time by setting NF10BMAC_64BIT and using a REGWTYPE #define to set correct
variable and return value widths.

Adjust comments to indicate the 32 or 64bit register widths.

MFC after:	2 weeks
 2014-06-26 17:10:07 +00:00
Bjoern A. Zeeb
7f55061017 Rather than using a constant use sizeof(val) allowing for the length 
to automatically change as we switch between 32/64bit.

MFC after:	2 weeks
 2014-06-26 17:03:08 +00:00
Bjoern A. Zeeb
68c332d3b9 In preparation for 64bit mode remove all the _4 from the function and 
macro names, rename val4 to val, and m4 to md.

No functional change.

MFC after:	2 weeks
 2014-06-26 16:49:45 +00:00
Bjoern A. Zeeb
3fd18f3945 Adjust the register layout to allow for 64bit registers in the 
future for nf10bmac(4).  Also, add support for and enable RX interrupts.

MFC after:	2 weeks
 2014-05-09 12:59:38 +00:00
Bjoern A. Zeeb
cb18b57c6d Now that I figured out where the ethernet addresses come from 
on NetFPGA-10G, assign one to the interface by default in a very
similar way.

MFC after:		6 days
X-Easter-Egg-Hunt:	yes
 2014-04-18 14:21:10 +00:00
Bjoern A. Zeeb
4a9af7d53f Add the initial version of if_nf10bmac(4), a driver to support an 
NetFPGA-10G Embedded CPU Ethernet Core.

The current version operates on a simple PIO based interface connected
to a NetFPGA-10G port.

To avoid confusion: this driver operates on a CPU running on the FPGA,
e.g. BERI/mips, and is not suited for the PCI host interface.

MFC after:	1 week
Relnotes:	yes
Sponsored by:	DARPA/AFRL
 2014-04-17 12:33:26 +00:00