from DWLPX to PCI space. Just a methods holder such that we have a parent
which is a "pcib" and we create a child which is a "pci". Add the appropriate
ivar code (which is for a hose #).
based upon presence/absence of ISA (there is no ISA bus on an 8200- okay,
well, there *could* be one in a DWLPX tray, but we don't support it)).
Most importantly change the interrupt resource map to cover a whole 16
bits. The 8200 uses 16 bit interrupt vectors which we construct that
contain the I/O-board, hose, an pci slot in them, and then we write these
vectors into the appropriate DWLPX registers. At any rate, a flat array
of 64 'IRQs' isn't enough.
to begin with. Redo newbus attachment code so that all the DMA mapping
and further pci attachment is done right. Insert config space functions
(jeez- how do you do type 1 cycles?). Do the interrupt setups, etc.
Basically, this is the core I/O module for 8200s, even though logically
it's the 3rd level down from the nominal principle backplane bus
(turbolaser). Still to be done here: S/G code isn't done yet, so we
better live with 2GB or less primary memory.
code (merge in progress made in NetBSD since the initial import to
FreeBSD). Create dwlpx as the child device. Of course, if we had
more h/w and time, we could find out whether the child device was
a FutureBus module, etc...Anyone ever actually seen one?
clean MI/MD driver, but it *does* actually work at this time. Updated
to use new make_dev stuff. A CONS_DRIVER declaration is also put in
so that this can be the real console for the 8200s.
with the known bogus currtpriority. This undoes the previous changes to
sys/i386/i386/trap.c, sys/alpha/alpha/trap.c, sys/sys/systm.h
Now we have the patch set approved by bde.
Approved by: bde
just the first one.
* Don't reserve extra memory for the prom console unless the platform
actually uses it.
* Fix some historical confusion and a minor bug in the message buffer
initialisation.
Submitted by: gallatin for the prom console part
Approved by: jkh
First, it was failing to reset the PCB's pcb_onfault member to NULL.
Under some really obscure circumstances this might cause a wild jump
within the kernel when a panic would otherwise occur. Second, the
handler was loading the GP register needlessly and with an incorrect
value.
Reviewed by: Doug Rabson <dfr>
Approved by: Jordan Hubbard <jkh>
was needed to make attach/detach of devices work, which is
needed for the PCCARD support.
(PCCARD support is still not working though, more to come on that)
Support the CMD646 chip which is used on many alphas, sadly only
in WDMA2 mode, as the silicon is broken beyond belief for UDMA modes.
Lots of cosmetic fixes here and there.
Sorry for the size of this megapatchfromhell but it was not
possible otherwise...
newbus patches based on work from: dfr (Doug Rabson)
fixes some namespace pollution in general and breakage of modules that
aren't in the sys tree in particular (<machine/ipl.h> includes further
headers that aren't installed under /usr/include).
Reimplemented SPLASSERT() so that it is more machine independent and
less bloated and doesn't require the <machine/ipl.h> include spam.
In particular, don't assume that `cpl' can be printed using %08x
format. The alpha arch doesn't even have `cpl'. SPLASSERT() was
harmless on alphas because it isn't actually used.
code & it survives a buildworld. So remove the dire warnings about
Noritake support being untested.
o Remove a disconserting printf() left over from NetBSD
Approved by: jkh
- only allocate rusage struct when caller wants rusage info
- fix a stupid paren mismatch bug that was causing EPERM to get returned
to callers rather then ECHILD
o Drop all broadcast and multicast source addresses in tcp_input.
o Enable ICMP_BANDLIM in GENERIC.
o Change default to 200/s from 100/s. This will still stop the attack, but
is conservative enough to do this close to code freeze.
This is not the optimal patch for the problem, but is likely the least
intrusive patch that can be made for this.
Obtained from: Don Lewis and Matt Dillon.
Reviewed by: freebsd-security
I was wagering on DEC being elegant & numbering PCI buses normally on
machines with one pchip. It looks like they went with consistent -- buses
behind ppbs begin with bus 2.
