mirror of
https://git.FreeBSD.org/src.git
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ebeaf70342
Obtained from: Semihalf
196 lines
5.6 KiB
C
196 lines
5.6 KiB
C
/*-
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* Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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#include <arm/mv/mvwin.h>
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extern const struct obio_pci_irq_map pci_irq_map[];
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struct obio_device obio_devices[] = {
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{ "ic", MV_IC_BASE, MV_IC_SIZE,
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{ -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "timer", MV_TIMERS_BASE, MV_TIMERS_SIZE,
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{ MV_INT_BRIDGE, -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "gpio", MV_GPIO_BASE, MV_GPIO_SIZE,
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{ MV_INT_GPIO7_0, MV_INT_GPIO15_8,
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MV_INT_GPIO23_16, MV_INT_GPIO31_24, -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "uart", MV_UART0_BASE, MV_UART_SIZE,
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{ MV_INT_UART0, -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "uart", MV_UART1_BASE, MV_UART_SIZE,
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{ MV_INT_UART1, -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "idma", MV_IDMA_BASE, MV_IDMA_SIZE,
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{ MV_INT_IDMA_ERR, MV_INT_IDMA0, MV_INT_IDMA1,
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MV_INT_IDMA2, MV_INT_IDMA3, -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "ehci", MV_USB0_BASE, MV_USB_SIZE,
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{ MV_INT_USB_BERR, MV_INT_USB_CI, -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "mge", MV_ETH0_BASE, MV_ETH_SIZE,
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{ MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC,
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MV_INT_GBESUM, MV_INT_GBEERR, -1 },
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{ -1 },
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CPU_PM_CTRL_NONE
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},
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{ "twsi", MV_TWSI0_BASE, MV_TWSI_SIZE,
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{ -1 }, { -1 },
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CPU_PM_CTRL_NONE
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},
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{ "sata", MV_SATAHC_BASE, MV_SATAHC_SIZE,
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{ MV_INT_SATA, -1 }, { -1 },
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CPU_PM_CTRL_NONE
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},
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{ NULL, 0, 0, { 0 } }
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};
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const struct obio_pci mv_pci_info[] = {
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{ MV_TYPE_PCIE,
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MV_PCIE_BASE, MV_PCIE_SIZE,
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MV_PCIE_IO_BASE, MV_PCIE_IO_SIZE, 4, 0x51,
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MV_PCIE_MEM_BASE, MV_PCIE_MEM_SIZE, 4, 0x59,
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NULL, MV_INT_PEX0
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},
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{ MV_TYPE_PCI,
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MV_PCI_BASE, MV_PCI_SIZE,
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MV_PCI_IO_BASE, MV_PCI_IO_SIZE, 3, 0x51,
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MV_PCI_MEM_BASE, MV_PCI_MEM_SIZE, 3, 0x59,
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pci_irq_map, -1
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},
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{ 0, 0, 0 }
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};
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struct resource_spec mv_gpio_res[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ SYS_RES_IRQ, 2, RF_ACTIVE },
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{ SYS_RES_IRQ, 3, RF_ACTIVE },
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{ -1, 0 }
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};
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const struct decode_win cpu_win_tbl[] = {
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/* Device bus BOOT */
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{ 1, 0x0f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 },
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/* Device bus CS0 */
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{ 1, 0x1e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 },
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/* Device bus CS1 */
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{ 1, 0x1d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 },
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/* Device bus CS2 */
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{ 1, 0x1b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 },
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};
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const struct decode_win *cpu_wins = cpu_win_tbl;
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int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win);
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/*
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* Note: the decode windows table for IDMA does not explicitly have DRAM
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* entries, which are not statically defined: active DDR banks (== windows)
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* are established in run time from actual DDR windows settings. All active
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* DDR banks are mapped into IDMA decode windows, so at least one IDMA decode
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* window is occupied by the DDR bank; in case when all (MV_WIN_DDR_MAX)
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* DDR banks are active, the remaining available IDMA decode windows for other
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* targets is only MV_WIN_IDMA_MAX - MV_WIN_DDR_MAX.
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*/
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const struct decode_win idma_win_tbl[] = {
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/* PCIE MEM */
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{ 4, 0x59, MV_PCIE_MEM_PHYS_BASE, MV_PCIE_MEM_SIZE, -1 },
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/* PCI MEM */
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{ 3, 0x59, MV_PCI_MEM_PHYS_BASE, MV_PCI_MEM_SIZE, -1 },
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/* Device bus BOOT */
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{ 1, 0x0f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 },
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/* Device bus CS0 */
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{ 1, 0x1e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 },
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/* Device bus CS1 */
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{ 1, 0x1d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 },
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/* Device bus CS2 */
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{ 1, 0x1b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 },
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};
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const struct decode_win *idma_wins = idma_win_tbl;
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int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win);
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uint32_t
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get_tclk(void)
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{
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uint32_t sar;
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/*
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* On Orion TCLK is can be configured to 150 MHz or 166 MHz.
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* Current setting is read from Sample At Reset register.
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*/
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sar = bus_space_read_4(obio_tag, MV_MPP_BASE, SAMPLE_AT_RESET);
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sar = (sar & TCLK_MASK) >> TCLK_SHIFT;
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switch (sar) {
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case 1:
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return (TCLK_150MHZ);
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case 2:
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return (TCLK_166MHZ);
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default:
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panic("Unknown TCLK settings!");
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}
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}
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