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7c45c9e4b5
This driver does not yet handle multiple chip selects properly. Note that the NAND infrastructure does not perform full page reads or writes, which means that this driver cannot make use of the hardware ECC that is otherwise present.
98 lines
3.5 KiB
C
98 lines
3.5 KiB
C
/*-
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* Copyright (C) 2012 Juniper Networks, Inc.
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* Copyright (C) 2009-2012 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _NAND_NFC_FSL_H_
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#define _NAND_NFC_FSL_H_
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/* LBC BR/OR Registers layout definitions */
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#define BR_V 0x00000001
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#define BR_V_SHIFT 0
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#define BR_MSEL 0x000000E0
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#define BR_MSEL_SHIFT 5
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#define BR_DECC_CHECK_MODE 0x00000600
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#define BR_DECC_CHECK_GEN 0x00000400
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#define OR_FCM_PAGESIZE 0x00000400
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/* Options definitions */
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#define NAND_OPT_ECC_MODE_HW 1
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#define NAND_OPT_ECC_MODE_SOFT (1 << 1)
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/* FMR - Flash Mode Register */
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#define FMR_CWTO 0xF000
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#define FMR_CWTO_SHIFT 12
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#define FMR_BOOT 0x0800
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#define FMR_ECCM 0x0100
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#define FMR_AL 0x0030
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#define FMR_AL_SHIFT 4
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#define FMR_OP 0x0003
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#define FMR_OP_SHIFT 0
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#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
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#define FIR_OP_CA 0x1 /* Issue current column address */
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#define FIR_OP_PA 0x2 /* Issue current block+page address */
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#define FIR_OP_UA 0x3 /* Issue user defined address */
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#define FIR_OP_CM(x) (4 + (x)) /* Issue command from FCR[CMD(x)] */
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#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
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#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
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#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
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#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
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#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
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#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
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#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
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#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
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/* LTESR - Transfer Error Status Register */
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#define LTESR_BM 0x80000000
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#define LTESR_FCT 0x40000000
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#define LTESR_PAR 0x20000000
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#define LTESR_WP 0x04000000
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#define LTESR_ATMW 0x00800000
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#define LTESR_ATMR 0x00400000
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#define LTESR_CS 0x00080000
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#define LTESR_CC 0x00000001
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#define LTESR_NAND_MASK (LTESR_FCT | LTESR_CC | LTESR_CS)
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/* FPAR - Flash Page Address Register */
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#define FPAR_SP_PI 0x00007C00
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#define FPAR_SP_PI_SHIFT 10
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#define FPAR_SP_MS 0x00000200
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#define FPAR_SP_CI 0x000001FF
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#define FPAR_SP_CI_SHIFT 0
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#define FPAR_LP_PI 0x0003F000
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#define FPAR_LP_PI_SHIFT 12
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#define FPAR_LP_MS 0x00000800
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#define FPAR_LP_CI 0x000007FF
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#define FPAR_LP_CI_SHIFT 0
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#define FSL_FCM_WAIT_TIMEOUT 10
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#endif /* _NAND_NFC_FSL_H_ */
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