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e2b03d4d48
still exists as a cell in the Macio asic on Apples, and is used to communicate through the shift register with the external PMU microcontroller.
106 lines
4.2 KiB
C
106 lines
4.2 KiB
C
/*
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* Copyright 2004 by Peter Grehan. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _VIA6522REG_H_
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#define _VIA6522REG_H_
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/* Registers */
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#define REG_OIRB 0 /* Input/output register B */
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#define REG_OIRA 1 /* Input/output register A */
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#define REG_DDRB 2 /* Data direction register B */
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#define REG_DDRA 3 /* Data direction register A */
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#define REG_T1CL 4 /* T1 low-order latch/low-order counter */
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#define REG_T1CH 5 /* T1 high-order counter */
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#define REG_T1LL 6 /* T1 low-order latches */
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#define REG_T1LH 7 /* T1 high-order latches */
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#define REG_T2CL 8 /* T2 low-order latch/low-order counter */
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#define REG_T2CH 9 /* T2 high-order counter */
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#define REG_SR 10 /* Shift register */
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#define REG_ACR 11 /* Auxiliary control register */
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#define REG_PCR 12 /* Peripheral control register */
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#define REG_IFR 13 /* Interrupt flag register */
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#define REG_IER 14 /* Interrupt-enable register */
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#define REG_OIRA_NH 15 /* Input/output register A: no handshake */
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/* Auxiliary control register (11) */
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#define ACR_SR_NONE 0x0 /* Disabled */
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#define ACR_SR_DIR 0x4 /* Bit for shift-register direction 1=out */
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#define ACR_SRI_T2 0x1 /* Shift in under control of T2 */
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#define ACR_SRI_PHI2 0x2 /* " " " " " PHI2 */
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#define ACR_SRI_EXTCLK 0x3 /* " " " " " external clk */
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#define ACR_SRO 0x4 /* Shift out free running at T2 rate */
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#define ACR_SRO_T2 0x5 /* Shift out under control of T2 */
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#define ACR_SRO_PHI2 0x6 /* " " " " " PHI2 */
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#define ACR_SRO_EXTCLK 0x7 /* " " " " " external clk */
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#define ACR_T1_SHIFT 5 /* bits 7-5 */
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#define ACR_SR_SHIFT 2 /* bits 4-2 */
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/* Peripheral control register (12) */
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#define PCR_INTCNTL 0x01 /* interrupt active edge: +ve=1, -ve=0 */
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#define PCR_CNTL_MASK 0x3 /* 3 bits */
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#define PCR_CNTL_NEDGE 0x0 /* Input - negative active edge */
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#define PCR_CNTL_INEDGE 0x1 /* Interrupt - negative active edge */
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#define PCR_CNTL_PEDGE 0x2 /* Input - positive active edge */
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#define PCR_CNTL_IPEDGE 0x3 /* Interrupt - positive active edge */
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#define PCR_CNTL_HSHAKE 0x4 /* Handshake output */
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#define PCR_CNTL_PULSE 0x5 /* Pulse output */
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#define PCR_CNTL_LOW 0x6 /* Low output */
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#define PCR_CNTL_HIGH 0x7 /* High output */
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#define PCR_CB2_SHIFT 5 /* bits 7-5 */
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#define PCR_CB1_SHIFT 4 /* bit 4 */
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#define PCR_CA2_SHIFT 1 /* bits 3-1 */
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#define PCR_CA1_SHIFT 0 /* bit 0 */
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/* Interrupt flag register (13) */
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#define IFR_CA2 0x01
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#define IFR_CA1 0x02
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#define IFR_SR 0x04
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#define IFR_CB2 0x08
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#define IFR_CB1 0x10
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#define IFR_T2 0x20
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#define IFR_T1 0x40
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#define IFR_IRQB 0x80 /* status of IRQB output pin */
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/* Interrupt enable register (14) */
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#define IER_CA2 IFR_CA2
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#define IER_CA1 IFR_CA1
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#define IER_SR IFR_SR
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#define IER_CB2 IFR_CB2
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#define IER_CB1 IFR_CB1
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#define IER_T2 IFR_T2
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#define IER_T1 IFR_T1
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#define IER_IRQB IFR_IRQB
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#endif /* _VIA6522REG_H_ */
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