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e557c1dd90
As a prerequisite for multiple queues, the guest must have MSIX enabled. Unfortunately, to work around device passthrough bugs, FreeBSD disables MSIX when running as a VMWare guest due to the hw.pci.honor_msi_blacklist tunable; this tunable must be disabled for multiple queues. Also included is various minor changes from the projects/vmxnet branch. MFC after: 1 month
344 lines
9.0 KiB
C
344 lines
9.0 KiB
C
/*-
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* Copyright (c) 2013 Tsubai Masanari
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $OpenBSD: src/sys/dev/pci/if_vmxreg.h,v 1.2 2013/06/12 01:07:33 uebayasi Exp $
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*
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* $FreeBSD$
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*/
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#ifndef _IF_VMXREG_H
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#define _IF_VMXREG_H
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struct UPT1_TxStats {
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uint64_t TSO_packets;
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uint64_t TSO_bytes;
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uint64_t ucast_packets;
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uint64_t ucast_bytes;
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uint64_t mcast_packets;
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uint64_t mcast_bytes;
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uint64_t bcast_packets;
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uint64_t bcast_bytes;
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uint64_t error;
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uint64_t discard;
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} __packed;
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struct UPT1_RxStats {
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uint64_t LRO_packets;
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uint64_t LRO_bytes;
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uint64_t ucast_packets;
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uint64_t ucast_bytes;
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uint64_t mcast_packets;
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uint64_t mcast_bytes;
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uint64_t bcast_packets;
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uint64_t bcast_bytes;
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uint64_t nobuffer;
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uint64_t error;
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} __packed;
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/* Interrupt moderation levels */
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#define UPT1_IMOD_NONE 0 /* No moderation */
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#define UPT1_IMOD_HIGHEST 7 /* Least interrupts */
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#define UPT1_IMOD_ADAPTIVE 8 /* Adaptive interrupt moderation */
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/* Hardware features */
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#define UPT1_F_CSUM 0x0001 /* Rx checksum verification */
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#define UPT1_F_RSS 0x0002 /* Receive side scaling */
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#define UPT1_F_VLAN 0x0004 /* VLAN tag stripping */
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#define UPT1_F_LRO 0x0008 /* Large receive offloading */
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#define VMXNET3_BAR0_IMASK(irq) (0x000 + (irq) * 8) /* Interrupt mask */
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#define VMXNET3_BAR0_TXH(q) (0x600 + (q) * 8) /* Tx head */
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#define VMXNET3_BAR0_RXH1(q) (0x800 + (q) * 8) /* Ring1 Rx head */
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#define VMXNET3_BAR0_RXH2(q) (0xA00 + (q) * 8) /* Ring2 Rx head */
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#define VMXNET3_BAR1_VRRS 0x000 /* VMXNET3 revision report selection */
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#define VMXNET3_BAR1_UVRS 0x008 /* UPT version report selection */
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#define VMXNET3_BAR1_DSL 0x010 /* Driver shared address low */
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#define VMXNET3_BAR1_DSH 0x018 /* Driver shared address high */
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#define VMXNET3_BAR1_CMD 0x020 /* Command */
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#define VMXNET3_BAR1_MACL 0x028 /* MAC address low */
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#define VMXNET3_BAR1_MACH 0x030 /* MAC address high */
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#define VMXNET3_BAR1_INTR 0x038 /* Interrupt status */
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#define VMXNET3_BAR1_EVENT 0x040 /* Event status */
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#define VMXNET3_CMD_ENABLE 0xCAFE0000 /* Enable VMXNET3 */
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#define VMXNET3_CMD_DISABLE 0xCAFE0001 /* Disable VMXNET3 */
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#define VMXNET3_CMD_RESET 0xCAFE0002 /* Reset device */
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#define VMXNET3_CMD_SET_RXMODE 0xCAFE0003 /* Set interface flags */
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#define VMXNET3_CMD_SET_FILTER 0xCAFE0004 /* Set address filter */
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#define VMXNET3_CMD_VLAN_FILTER 0xCAFE0005 /* Set VLAN filter */
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#define VMXNET3_CMD_GET_STATUS 0xF00D0000 /* Get queue errors */
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#define VMXNET3_CMD_GET_STATS 0xF00D0001 /* Get queue statistics */
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#define VMXNET3_CMD_GET_LINK 0xF00D0002 /* Get link status */
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#define VMXNET3_CMD_GET_MACL 0xF00D0003 /* Get MAC address low */
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#define VMXNET3_CMD_GET_MACH 0xF00D0004 /* Get MAC address high */
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#define VMXNET3_CMD_GET_INTRCFG 0xF00D0008 /* Get interrupt config */
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#define VMXNET3_DMADESC_ALIGN 128
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#define VMXNET3_INIT_GEN 1
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struct vmxnet3_txdesc {
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uint64_t addr;
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uint32_t len:14;
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uint32_t gen:1; /* Generation */
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uint32_t pad1:1;
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uint32_t dtype:1; /* Descriptor type */
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uint32_t pad2:1;
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uint32_t offload_pos:14; /* Offloading position */
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uint32_t hlen:10; /* Header len */
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uint32_t offload_mode:2; /* Offloading mode */
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uint32_t eop:1; /* End of packet */
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uint32_t compreq:1; /* Completion request */
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uint32_t pad3:1;
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uint32_t vtag_mode:1; /* VLAN tag insertion mode */
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uint32_t vtag:16; /* VLAN tag */
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} __packed;
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/* Offloading modes */
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#define VMXNET3_OM_NONE 0
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#define VMXNET3_OM_CSUM 2
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#define VMXNET3_OM_TSO 3
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struct vmxnet3_txcompdesc {
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uint32_t eop_idx:12; /* EOP index in Tx ring */
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uint32_t pad1:20;
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uint32_t pad2:32;
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uint32_t pad3:32;
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uint32_t rsvd:24;
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uint32_t type:7;
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uint32_t gen:1;
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} __packed;
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struct vmxnet3_rxdesc {
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uint64_t addr;
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uint32_t len:14;
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uint32_t btype:1; /* Buffer type */
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uint32_t dtype:1; /* Descriptor type */
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uint32_t rsvd:15;
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uint32_t gen:1;
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uint32_t pad1:32;
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} __packed;
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/* Buffer types */
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#define VMXNET3_BTYPE_HEAD 0 /* Head only */
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#define VMXNET3_BTYPE_BODY 1 /* Body only */
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struct vmxnet3_rxcompdesc {
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uint32_t rxd_idx:12; /* Rx descriptor index */
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uint32_t pad1:2;
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uint32_t eop:1; /* End of packet */
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uint32_t sop:1; /* Start of packet */
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uint32_t qid:10;
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uint32_t rss_type:4;
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uint32_t no_csum:1; /* No checksum calculated */
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uint32_t pad2:1;
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uint32_t rss_hash:32; /* RSS hash value */
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uint32_t len:14;
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uint32_t error:1;
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uint32_t vlan:1; /* 802.1Q VLAN frame */
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uint32_t vtag:16; /* VLAN tag */
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uint32_t csum:16;
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uint32_t csum_ok:1; /* TCP/UDP checksum ok */
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uint32_t udp:1;
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uint32_t tcp:1;
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uint32_t ipcsum_ok:1; /* IP checksum OK */
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uint32_t ipv6:1;
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uint32_t ipv4:1;
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uint32_t fragment:1; /* IP fragment */
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uint32_t fcs:1; /* Frame CRC correct */
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uint32_t type:7;
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uint32_t gen:1;
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} __packed;
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#define VMXNET3_RCD_RSS_TYPE_NONE 0
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#define VMXNET3_RCD_RSS_TYPE_IPV4 1
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#define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2
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#define VMXNET3_RCD_RSS_TYPE_IPV6 3
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#define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4
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#define VMXNET3_REV1_MAGIC 0XBABEFEE1
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#define VMXNET3_GOS_UNKNOWN 0x00
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#define VMXNET3_GOS_LINUX 0x04
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#define VMXNET3_GOS_WINDOWS 0x08
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#define VMXNET3_GOS_SOLARIS 0x0C
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#define VMXNET3_GOS_FREEBSD 0x10
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#define VMXNET3_GOS_PXE 0x14
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#define VMXNET3_GOS_32BIT 0x01
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#define VMXNET3_GOS_64BIT 0x02
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#define VMXNET3_MAX_TX_QUEUES 8
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#define VMXNET3_MAX_RX_QUEUES 16
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#define VMXNET3_MAX_INTRS \
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(VMXNET3_MAX_TX_QUEUES + VMXNET3_MAX_RX_QUEUES + 1)
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#define VMXNET3_ICTRL_DISABLE_ALL 0x01
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#define VMXNET3_RXMODE_UCAST 0x01
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#define VMXNET3_RXMODE_MCAST 0x02
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#define VMXNET3_RXMODE_BCAST 0x04
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#define VMXNET3_RXMODE_ALLMULTI 0x08
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#define VMXNET3_RXMODE_PROMISC 0x10
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#define VMXNET3_EVENT_RQERROR 0x01
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#define VMXNET3_EVENT_TQERROR 0x02
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#define VMXNET3_EVENT_LINK 0x04
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#define VMXNET3_EVENT_DIC 0x08
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#define VMXNET3_EVENT_DEBUG 0x10
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#define VMXNET3_MIN_MTU 60
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#define VMXNET3_MAX_MTU 9000
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/* Interrupt mask mode. */
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#define VMXNET3_IMM_AUTO 0x00
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#define VMXNET3_IMM_ACTIVE 0x01
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#define VMXNET3_IMM_LAZY 0x02
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/* Interrupt type. */
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#define VMXNET3_IT_AUTO 0x00
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#define VMXNET3_IT_LEGACY 0x01
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#define VMXNET3_IT_MSI 0x02
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#define VMXNET3_IT_MSIX 0x03
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struct vmxnet3_driver_shared {
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uint32_t magic;
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uint32_t pad1;
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/* Misc. control */
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uint32_t version; /* Driver version */
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uint32_t guest; /* Guest OS */
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uint32_t vmxnet3_revision; /* Supported VMXNET3 revision */
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uint32_t upt_version; /* Supported UPT version */
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uint64_t upt_features;
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uint64_t driver_data;
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uint64_t queue_shared;
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uint32_t driver_data_len;
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uint32_t queue_shared_len;
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uint32_t mtu;
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uint16_t nrxsg_max;
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uint8_t ntxqueue;
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uint8_t nrxqueue;
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uint32_t reserved1[4];
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/* Interrupt control */
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uint8_t automask;
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uint8_t nintr;
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uint8_t evintr;
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uint8_t modlevel[VMXNET3_MAX_INTRS];
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uint32_t ictrl;
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uint32_t reserved2[2];
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/* Receive filter parameters */
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uint32_t rxmode;
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uint16_t mcast_tablelen;
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uint16_t pad2;
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uint64_t mcast_table;
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uint32_t vlan_filter[4096 / 32];
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struct {
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uint32_t version;
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uint32_t len;
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uint64_t paddr;
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} rss, pm, plugin;
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uint32_t event;
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uint32_t reserved3[5];
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} __packed;
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struct vmxnet3_txq_shared {
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/* Control */
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uint32_t npending;
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uint32_t intr_threshold;
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uint64_t reserved1;
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/* Config */
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uint64_t cmd_ring;
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uint64_t data_ring;
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uint64_t comp_ring;
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uint64_t driver_data;
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uint64_t reserved2;
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uint32_t cmd_ring_len;
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uint32_t data_ring_len;
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uint32_t comp_ring_len;
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uint32_t driver_data_len;
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uint8_t intr_idx;
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uint8_t pad1[7];
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/* Queue status */
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uint8_t stopped;
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uint8_t pad2[3];
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uint32_t error;
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struct UPT1_TxStats stats;
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uint8_t pad3[88];
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} __packed;
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struct vmxnet3_rxq_shared {
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uint8_t update_rxhead;
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uint8_t pad1[7];
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uint64_t reserved1;
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uint64_t cmd_ring[2];
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uint64_t comp_ring;
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uint64_t driver_data;
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uint64_t reserved2;
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uint32_t cmd_ring_len[2];
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uint32_t comp_ring_len;
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uint32_t driver_data_len;
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uint8_t intr_idx;
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uint8_t pad2[7];
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uint8_t stopped;
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uint8_t pad3[3];
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uint32_t error;
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struct UPT1_RxStats stats;
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uint8_t pad4[88];
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} __packed;
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#define UPT1_RSS_HASH_TYPE_NONE 0x00
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#define UPT1_RSS_HASH_TYPE_IPV4 0x01
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#define UPT1_RSS_HASH_TYPE_TCP_IPV4 0x02
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#define UPT1_RSS_HASH_TYPE_IPV6 0x04
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#define UPT1_RSS_HASH_TYPE_TCP_IPV6 0x08
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#define UPT1_RSS_HASH_FUNC_NONE 0x00
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#define UPT1_RSS_HASH_FUNC_TOEPLITZ 0x01
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#define UPT1_RSS_MAX_KEY_SIZE 40
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#define UPT1_RSS_MAX_IND_TABLE_SIZE 128
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struct vmxnet3_rss_shared {
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uint16_t hash_type;
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uint16_t hash_func;
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uint16_t hash_key_size;
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uint16_t ind_table_size;
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uint8_t hash_key[UPT1_RSS_MAX_KEY_SIZE];
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uint8_t ind_table[UPT1_RSS_MAX_IND_TABLE_SIZE];
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} __packed;
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#endif /* _IF_VMXREG_H */
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