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ac0797c3d1
TNT5004 IC. This involved a major rewrite of a number of things, as this chip no longer supports the NAT7210 legacy mode but requires the host to use the (more modern) FIFO mode. In theory, this also ought to work on the older TNT4882C chip. I'll probably add this as optional support (perhaps by a device.hints flag) later on. By now, FIFO mode is *only* activates iff a TNT5004 chip has been detected (where the old code didn't work at all), while everything else is supposed to use the old code. MFC after: 2 weeks
1120 lines
26 KiB
C
1120 lines
26 KiB
C
/*-
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* Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
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* Copyright (c) 2010 Joerg Wunsch <joerg@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* High-level driver for µPD7210 based GPIB cards.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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# define IBDEBUG
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# undef IBDEBUG
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/limits.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/uio.h>
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#include <sys/time.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <isa/isavar.h>
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#include <dev/ieee488/ugpib.h>
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#define UPD7210_SW_DRIVER
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#include <dev/ieee488/upd7210.h>
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#include <dev/ieee488/tnt4882.h>
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static MALLOC_DEFINE(M_IBFOO, "IBFOO", "IBFOO");
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/* ibfoo API */
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#include <dev/ieee488/ibfoo_int.h>
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/* XXX: This is really a bitmap */
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enum h_kind {
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H_DEV = 1,
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H_BOARD = 2,
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H_EITHER = 3
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};
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struct handle {
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LIST_ENTRY(handle) list;
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int handle;
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enum h_kind kind;
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int pad;
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int sad;
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struct timeval timeout;
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int eot;
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int eos;
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int dma;
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};
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struct ibfoo {
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struct upd7210 *u;
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LIST_HEAD(,handle) handles;
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struct unrhdr *unrhdr;
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struct callout callout;
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struct handle *h;
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struct ibarg *ap;
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enum {
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IDLE,
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BUSY,
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PIO_IDATA,
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PIO_ODATA,
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PIO_CMD,
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DMA_IDATA,
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FIFO_IDATA,
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FIFO_ODATA,
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FIFO_CMD
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} mode;
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struct timeval deadline;
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struct handle *rdh; /* addressed for read */
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struct handle *wrh; /* addressed for write */
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int doeoi;
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u_char *buf;
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u_int buflen;
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};
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typedef int ibhandler_t(struct ibfoo *ib);
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static struct timeval timeouts[] = {
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[TNONE] = { 0, 0},
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[T10us] = { 0, 10},
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[T30us] = { 0, 30},
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[T100us] = { 0, 100},
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[T300us] = { 0, 300},
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[T1ms] = { 0, 1000},
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[T3ms] = { 0, 3000},
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[T10ms] = { 0, 10000},
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[T30ms] = { 0, 30000},
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[T100ms] = { 0, 100000},
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[T300ms] = { 0, 300000},
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[T1s] = { 1, 0},
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[T3s] = { 3, 0},
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[T10s] = { 10, 0},
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[T30s] = { 30, 0},
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[T100s] = { 100, 0},
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[T300s] = { 300, 0},
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[T1000s] = { 1000, 0}
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};
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static const u_int max_timeouts = sizeof timeouts / sizeof timeouts[0];
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static int ibdebug;
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static int
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ib_set_error(struct ibarg *ap, int error)
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{
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if (ap->__iberr == 0)
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ap->__iberr = error;
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ap->__ibsta |= ERR;
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ap->__retval = ap->__ibsta;
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return (0);
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}
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static int
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ib_had_timeout(struct ibarg *ap)
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{
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ib_set_error(ap, EABO);
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ap->__ibsta |= TIMO;
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ap->__retval = ap->__ibsta;
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return (0);
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}
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static int
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ib_set_errno(struct ibarg *ap, int errno)
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{
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if (ap->__iberr == 0) {
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ap->__iberr = EDVR;
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ap->__ibcnt = errno;
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}
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ap->__ibsta |= ERR;
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ap->__retval = ap->__ibsta;
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return (0);
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}
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static int
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gpib_ib_irq(struct upd7210 *u, int isr_3)
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{
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struct ibfoo *ib;
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ib = u->ibfoo;
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mtx_assert(&u->mutex, MA_OWNED);
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switch (ib->mode) {
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case PIO_CMD:
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if (!(u->rreg[ISR2] & IXR2_CO))
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return (0);
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if (ib->buflen == 0)
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break;
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upd7210_wr(u, CDOR, *ib->buf);
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ib->buf++;
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ib->buflen--;
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return (1);
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case PIO_IDATA:
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if (!(u->rreg[ISR1] & IXR1_DI))
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return (0);
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*ib->buf = upd7210_rd(u, DIR);
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ib->buf++;
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ib->buflen--;
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if (ib->buflen == 0 || (u->rreg[ISR1] & IXR1_ENDRX))
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break;
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return (1);
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case PIO_ODATA:
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if (!(u->rreg[ISR1] & IXR1_DO))
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return (0);
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if (ib->buflen == 0)
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break;
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if (ib->buflen == 1 && ib->doeoi)
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upd7210_wr(u, AUXMR, AUXMR_SEOI);
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upd7210_wr(u, CDOR, *ib->buf);
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ib->buf++;
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ib->buflen--;
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return (1);
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case DMA_IDATA:
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if (!(u->rreg[ISR1] & IXR1_ENDRX))
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return (0);
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break;
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case FIFO_IDATA:
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if (!(isr_3 & 0x15))
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return (0);
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while (ib->buflen != 0 && (isr_3 & 0x04 /* NEF */) != 0) {
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*ib->buf = bus_read_1(u->reg_res[0], fifob);
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ib->buf++;
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ib->buflen--;
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isr_3 = bus_read_1(u->reg_res[0], isr3);
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}
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if ((isr_3 & 0x01) != 0 /* xfr done */ ||
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(u->rreg[ISR1] & IXR1_ENDRX) != 0 ||
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ib->buflen == 0)
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break;
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if (isr_3 & 0x10)
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/* xfr stopped */
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bus_write_1(u->reg_res[0], cmdr, 0x04); /* GO */
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upd7210_wr(u, AUXMR, AUXMR_RFD);
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return (1);
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case FIFO_CMD:
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case FIFO_ODATA:
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if (!(isr_3 & 0x19))
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return (0);
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if (ib->buflen == 0)
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/* xfr DONE */
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break;
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while (ib->buflen != 0 && (isr_3 & 0x08 /* NFF */) != 0) {
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bus_write_1(u->reg_res[0], fifob, *ib->buf);
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ib->buf++;
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ib->buflen--;
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isr_3 = bus_read_1(u->reg_res[0], isr3);
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}
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if (isr_3 & 0x10)
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/* xfr stopped */
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bus_write_1(u->reg_res[0], cmdr, 0x04); /* GO */
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if (ib->buflen == 0)
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/* no more NFF interrupts wanted */
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bus_write_1(u->reg_res[0], imr3, 0x11); /* STOP IE, DONE IE */
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return (1);
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default:
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return (0);
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}
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upd7210_wr(u, IMR1, 0);
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upd7210_wr(u, IMR2, 0);
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if (u->use_fifo) {
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bus_write_1(u->reg_res[0], imr3, 0x00);
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bus_write_1(u->reg_res[0], cmdr, 0x22); /* soft RESET */
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}
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ib->mode = BUSY;
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wakeup(&ib->buflen);
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return (1);
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}
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static void
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gpib_ib_timeout(void *arg)
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{
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struct upd7210 *u;
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struct ibfoo *ib;
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struct timeval tv;
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u_int isr_3;
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u = arg;
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ib = u->ibfoo;
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mtx_lock(&u->mutex);
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if (ib->mode == DMA_IDATA && isa_dmatc(u->dmachan)) {
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KASSERT(u->dmachan >= 0, ("Bogus dmachan = %d", u->dmachan));
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upd7210_wr(u, IMR1, 0);
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upd7210_wr(u, IMR2, 0);
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ib->mode = BUSY;
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wakeup(&ib->buflen);
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}
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if (ib->mode > BUSY) {
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upd7210_rd(u, ISR1);
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upd7210_rd(u, ISR2);
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if (u->use_fifo)
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isr_3 = bus_read_1(u->reg_res[0], isr3);
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else
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isr_3 = 0;
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gpib_ib_irq(u, isr_3);
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}
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if (ib->mode != IDLE && timevalisset(&ib->deadline)) {
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getmicrouptime(&tv);
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if (timevalcmp(&ib->deadline, &tv, <)) {
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ib_had_timeout(ib->ap);
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upd7210_wr(u, IMR1, 0);
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upd7210_wr(u, IMR2, 0);
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if (u->use_fifo) {
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bus_write_1(u->reg_res[0], imr3, 0x00);
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bus_write_1(u->reg_res[0], cmdr, 0x22); /* soft RESET */
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}
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ib->mode = BUSY;
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wakeup(&ib->buflen);
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}
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}
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if (ib->mode != IDLE)
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callout_reset(&ib->callout, hz / 5, gpib_ib_timeout, arg);
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mtx_unlock(&u->mutex);
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}
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static void
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gpib_ib_wait_xfer(struct upd7210 *u, struct ibfoo *ib)
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{
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int i;
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mtx_assert(&u->mutex, MA_OWNED);
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while (ib->mode > BUSY) {
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i = msleep(&ib->buflen, &u->mutex,
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PZERO | PCATCH, "ibwxfr", 0);
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if (i == EINTR) {
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ib_set_errno(ib->ap, i);
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break;
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}
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if (u->rreg[ISR1] & IXR1_ERR) {
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ib_set_error(ib->ap, EABO); /* XXX ? */
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break;
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}
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}
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ib->mode = BUSY;
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ib->buf = NULL;
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upd7210_wr(u, IMR1, 0);
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upd7210_wr(u, IMR2, 0);
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if (u->use_fifo)
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bus_write_1(u->reg_res[0], imr3, 0x00);
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}
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static void
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config_eos(struct upd7210 *u, struct handle *h)
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{
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int i;
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i = 0;
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if (h->eos & REOS) {
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upd7210_wr(u, EOSR, h->eos & 0xff);
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i |= AUXA_REOS;
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}
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if (h->eos & XEOS) {
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upd7210_wr(u, EOSR, h->eos & 0xff);
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i |= AUXA_XEOS;
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}
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if (h->eos & BIN)
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i |= AUXA_BIN;
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upd7210_wr(u, AUXRA, C_AUXA | i);
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}
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/*
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* Look up the handle, and set the deadline if the handle has a timeout.
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*/
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static int
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gethandle(struct upd7210 *u, struct ibarg *ap, struct handle **hp)
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{
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struct ibfoo *ib;
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struct handle *h;
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KASSERT(ap->__field & __F_HANDLE, ("gethandle without __F_HANDLE"));
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ib = u->ibfoo;
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LIST_FOREACH(h, &ib->handles, list) {
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if (h->handle == ap->handle) {
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*hp = h;
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return (0);
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}
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}
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ib_set_error(ap, EARG);
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return (1);
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}
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static int
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pio_cmd(struct upd7210 *u, u_char *cmd, int len)
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{
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struct ibfoo *ib;
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ib = u->ibfoo;
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if (ib->rdh != NULL || ib->wrh != NULL) {
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upd7210_take_ctrl_async(u);
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ib->rdh = NULL;
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ib->wrh = NULL;
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}
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mtx_lock(&u->mutex);
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ib->buf = cmd;
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ib->buflen = len;
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if (u->use_fifo) {
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/* TNT5004 or TNT4882 in FIFO mode */
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ib->mode = FIFO_CMD;
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upd7210_wr(u, AUXMR, 0x51); /* holdoff immediately */
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bus_write_1(u->reg_res[0], cmdr, 0x10); /* reset FIFO */
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bus_write_1(u->reg_res[0], cfg, 0x80); /* CMD, xfer OUT, 8-bit FIFO */
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bus_write_1(u->reg_res[0], imr3, 0x19); /* STOP IE, NFF IE, DONE IE */
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bus_write_1(u->reg_res[0], cnt0, -len);
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bus_write_1(u->reg_res[0], cnt1, (-len) >> 8);
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bus_write_1(u->reg_res[0], cnt2, (-len) >> 16);
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bus_write_1(u->reg_res[0], cnt3, (-len) >> 24);
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bus_write_1(u->reg_res[0], cmdr, 0x04); /* GO */
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} else {
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ib->mode = PIO_CMD;
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upd7210_wr(u, IMR2, IXR2_CO);
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gpib_ib_irq(u, 0);
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}
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gpib_ib_wait_xfer(u, ib);
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if (u->use_fifo)
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bus_write_1(u->reg_res[0], cmdr, 0x08); /* STOP */
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mtx_unlock(&u->mutex);
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return (len - ib->buflen);
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}
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static int
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pio_odata(struct upd7210 *u, u_char *data, int len)
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{
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struct ibfoo *ib;
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ib = u->ibfoo;
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if (len == 0)
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return (0);
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mtx_lock(&u->mutex);
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ib->buf = data;
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ib->buflen = len;
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if (u->use_fifo) {
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/* TNT5004 or TNT4882 in FIFO mode */
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ib->mode = FIFO_ODATA;
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bus_write_1(u->reg_res[0], cmdr, 0x10); /* reset FIFO */
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if (ib->doeoi)
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bus_write_1(u->reg_res[0], cfg, 0x08); /* CCEN */
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else
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bus_write_1(u->reg_res[0], cfg, 0x00); /* xfer OUT, 8-bit FIFO */
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bus_write_1(u->reg_res[0], imr3, 0x19); /* STOP IE, NFF IE, DONE IE */
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bus_write_1(u->reg_res[0], cnt0, -len);
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bus_write_1(u->reg_res[0], cnt1, (-len) >> 8);
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bus_write_1(u->reg_res[0], cnt2, (-len) >> 16);
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bus_write_1(u->reg_res[0], cnt3, (-len) >> 24);
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bus_write_1(u->reg_res[0], cmdr, 0x04); /* GO */
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} else {
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ib->mode = PIO_ODATA;
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upd7210_wr(u, IMR1, IXR1_DO);
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}
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gpib_ib_wait_xfer(u, ib);
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if (u->use_fifo)
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bus_write_1(u->reg_res[0], cmdr, 0x08); /* STOP */
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mtx_unlock(&u->mutex);
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return (len - ib->buflen);
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}
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static int
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pio_idata(struct upd7210 *u, u_char *data, int len)
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{
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struct ibfoo *ib;
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ib = u->ibfoo;
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mtx_lock(&u->mutex);
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ib->buf = data;
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ib->buflen = len;
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if (u->use_fifo) {
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/* TNT5004 or TNT4882 in FIFO mode */
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ib->mode = FIFO_IDATA;
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bus_write_1(u->reg_res[0], cmdr, 0x10); /* reset FIFO */
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bus_write_1(u->reg_res[0], cfg, 0x20); /* xfer IN, 8-bit FIFO */
|
|
bus_write_1(u->reg_res[0], cnt0, -len);
|
|
bus_write_1(u->reg_res[0], cnt1, (-len) >> 8);
|
|
bus_write_1(u->reg_res[0], cnt2, (-len) >> 16);
|
|
bus_write_1(u->reg_res[0], cnt3, (-len) >> 24);
|
|
bus_write_1(u->reg_res[0], cmdr, 0x04); /* GO */
|
|
upd7210_wr(u, AUXMR, AUXMR_RFD);
|
|
bus_write_1(u->reg_res[0], imr3, 0x15); /* STOP IE, NEF IE, DONE IE */
|
|
} else {
|
|
ib->mode = PIO_IDATA;
|
|
upd7210_wr(u, IMR1, IXR1_DI);
|
|
}
|
|
|
|
gpib_ib_wait_xfer(u, ib);
|
|
|
|
if (u->use_fifo)
|
|
bus_write_1(u->reg_res[0], cmdr, 0x08); /* STOP */
|
|
|
|
mtx_unlock(&u->mutex);
|
|
return (len - ib->buflen);
|
|
}
|
|
|
|
static int
|
|
dma_idata(struct upd7210 *u, u_char *data, int len)
|
|
{
|
|
int j;
|
|
struct ibfoo *ib;
|
|
|
|
KASSERT(u->dmachan >= 0, ("Bogus dmachan %d", u->dmachan));
|
|
ib = u->ibfoo;
|
|
ib->mode = DMA_IDATA;
|
|
isa_dmastart(ISADMA_READ, data, len, u->dmachan);
|
|
mtx_lock(&u->mutex);
|
|
upd7210_wr(u, IMR1, IXR1_ENDRX);
|
|
upd7210_wr(u, IMR2, IMR2_DMAI);
|
|
gpib_ib_wait_xfer(u, ib);
|
|
mtx_unlock(&u->mutex);
|
|
j = isa_dmastatus(u->dmachan);
|
|
isa_dmadone(ISADMA_READ, data, len, u->dmachan);
|
|
return (len - j);
|
|
}
|
|
|
|
static int
|
|
ib_send_msg(struct ibfoo *ib, int msg)
|
|
{
|
|
u_char buf[10];
|
|
int i, j;
|
|
|
|
i = 0;
|
|
buf[i++] = UNT;
|
|
buf[i++] = UNL;
|
|
buf[i++] = LAD | ib->h->pad;
|
|
if (ib->h->sad)
|
|
buf[i++] = LAD | TAD | ib->h->sad;
|
|
buf[i++] = TAD | 0;
|
|
buf[i++] = msg;
|
|
j = pio_cmd(ib->u, buf, i);
|
|
if (i != j)
|
|
ib_set_error(ib->ap, EABO); /* XXX ? */
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ibask(struct ibfoo *ib)
|
|
{ /* XXX */
|
|
|
|
ibdebug = ib->ap->option;
|
|
return (0);
|
|
}
|
|
|
|
#define ibbna NULL
|
|
#define ibcac NULL
|
|
|
|
static int
|
|
ibclr(struct ibfoo *ib)
|
|
{
|
|
|
|
return (ib_send_msg(ib, SDC));
|
|
}
|
|
|
|
#define ibcmd NULL
|
|
#define ibcmda NULL
|
|
#define ibconfig NULL
|
|
|
|
static int
|
|
ibdev(struct ibfoo *ib)
|
|
{ /* TBD */
|
|
struct handle *h;
|
|
|
|
h = malloc(sizeof *h, M_IBFOO, M_ZERO | M_WAITOK);
|
|
h->handle = alloc_unr(ib->unrhdr);
|
|
h->kind = H_DEV;
|
|
h->pad = ib->ap->pad;
|
|
h->sad = ib->ap->sad;
|
|
h->timeout = timeouts[ib->ap->tmo];
|
|
h->eot = ib->ap->eot;
|
|
h->eos = ib->ap->eos;
|
|
mtx_lock(&ib->u->mutex);
|
|
LIST_INSERT_HEAD(&ib->handles, h, list);
|
|
mtx_unlock(&ib->u->mutex);
|
|
ib->ap->__retval = h->handle;
|
|
return (0);
|
|
}
|
|
|
|
#define ibdiag NULL
|
|
|
|
static int
|
|
ibdma(struct ibfoo *ib)
|
|
{
|
|
|
|
if (ib->u->dmachan < 0 && ib->ap->v)
|
|
return (ib_set_error(ib->ap, EARG));
|
|
ib->h->dma = ib->ap->v;
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ibeos(struct ibfoo *ib)
|
|
{
|
|
|
|
ib->ap->__iberr = ib->h->eos;
|
|
ib->h->eos = ib->ap->eos;
|
|
if (ib->rdh == ib->h)
|
|
config_eos(ib->u, ib->h);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ibeot(struct ibfoo *ib)
|
|
{
|
|
|
|
ib->h->eot = ib->ap->eot;
|
|
return (0);
|
|
}
|
|
|
|
#define ibevent NULL
|
|
#define ibfind NULL
|
|
#define ibgts NULL
|
|
#define ibist NULL
|
|
#define iblines NULL
|
|
#define ibllo NULL
|
|
#define ibln NULL
|
|
|
|
static int
|
|
ibloc(struct ibfoo *ib)
|
|
{ /* XXX */
|
|
|
|
if (ib->h->kind == H_BOARD)
|
|
return (EOPNOTSUPP); /* XXX */
|
|
return (ib_send_msg(ib, GTL));
|
|
}
|
|
|
|
static int
|
|
ibonl(struct ibfoo *ib)
|
|
{ /* XXX */
|
|
|
|
if (ib->ap->v)
|
|
return (EOPNOTSUPP); /* XXX */
|
|
mtx_lock(&ib->u->mutex);
|
|
LIST_REMOVE(ib->h, list);
|
|
mtx_unlock(&ib->u->mutex);
|
|
free(ib->h, M_IBFOO);
|
|
ib->h = NULL;
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ibpad(struct ibfoo *ib)
|
|
{
|
|
|
|
ib->h->pad = ib->ap->pad;
|
|
return (0);
|
|
}
|
|
|
|
#define ibpct NULL
|
|
#define ibpoke NULL
|
|
#define ibppc NULL
|
|
|
|
static int
|
|
ibrd(struct ibfoo *ib)
|
|
{ /* TBD */
|
|
u_char buf[10], *bp;
|
|
int i, j, error, bl, bc;
|
|
u_char *dp;
|
|
|
|
if (ib->h->kind == H_BOARD)
|
|
return (EOPNOTSUPP); /* XXX */
|
|
bl = ib->ap->cnt;
|
|
if (bl > PAGE_SIZE)
|
|
bl = PAGE_SIZE;
|
|
bp = malloc(bl, M_IBFOO, M_WAITOK);
|
|
|
|
if (ib->rdh != ib->h) {
|
|
i = 0;
|
|
buf[i++] = UNT;
|
|
buf[i++] = UNL;
|
|
buf[i++] = LAD | 0;
|
|
buf[i++] = TAD | ib->h->pad;
|
|
if (ib->h->sad)
|
|
buf[i++] = ib->h->sad;
|
|
i = pio_cmd(ib->u, buf, i);
|
|
config_eos(ib->u, ib->h);
|
|
ib->rdh = ib->h;
|
|
ib->wrh = NULL;
|
|
}
|
|
upd7210_goto_standby(ib->u);
|
|
dp = ib->ap->buffer;
|
|
bc = ib->ap->cnt;
|
|
error = 0;
|
|
while (bc > 0 && ib->ap->__iberr == 0) {
|
|
j = imin(bc, PAGE_SIZE);
|
|
if (ib->h->dma)
|
|
i = dma_idata(ib->u, bp, j);
|
|
else
|
|
i = pio_idata(ib->u, bp, j);
|
|
error = copyout(bp, dp , i);
|
|
if (error)
|
|
break;
|
|
ib->ap->__ibcnt += i;
|
|
if (i != j)
|
|
break;
|
|
bc -= i;
|
|
dp += i;
|
|
}
|
|
upd7210_take_ctrl_async(ib->u);
|
|
free(bp, M_IBFOO);
|
|
return (error);
|
|
}
|
|
|
|
#define ibrda NULL
|
|
#define ibrdf NULL
|
|
#define ibrdkey NULL
|
|
#define ibrpp NULL
|
|
#define ibrsc NULL
|
|
#define ibrsp NULL
|
|
#define ibrsv NULL
|
|
|
|
static int
|
|
ibsad(struct ibfoo *ib)
|
|
{
|
|
|
|
ib->h->sad = ib->ap->sad;
|
|
return (0);
|
|
}
|
|
|
|
#define ibsgnl NULL
|
|
|
|
static int
|
|
ibsic(struct ibfoo *ib)
|
|
{ /* TBD */
|
|
|
|
upd7210_wr(ib->u, AUXMR, AUXMR_SIFC);
|
|
DELAY(100);
|
|
upd7210_wr(ib->u, AUXMR, AUXMR_CIFC);
|
|
return (0);
|
|
}
|
|
|
|
#define ibsre NULL
|
|
#define ibsrq NULL
|
|
#define ibstop NULL
|
|
|
|
static int
|
|
ibtmo(struct ibfoo *ib)
|
|
{
|
|
|
|
ib->h->timeout = timeouts[ib->ap->tmo];
|
|
return (0);
|
|
}
|
|
|
|
#define ibtrap NULL
|
|
|
|
static int
|
|
ibtrg(struct ibfoo *ib)
|
|
{
|
|
|
|
return (ib_send_msg(ib, GET));
|
|
}
|
|
|
|
#define ibwait NULL
|
|
|
|
static int
|
|
ibwrt(struct ibfoo *ib)
|
|
{ /* XXX */
|
|
u_char buf[10], *bp;
|
|
int i;
|
|
|
|
if (ib->h->kind == H_BOARD)
|
|
return (EOPNOTSUPP);
|
|
bp = malloc(ib->ap->cnt, M_IBFOO, M_WAITOK);
|
|
/* XXX: bigger than PAGE_SIZE handling */
|
|
i = copyin(ib->ap->buffer, bp, ib->ap->cnt);
|
|
if (i) {
|
|
free(bp, M_IBFOO);
|
|
return (i);
|
|
}
|
|
if (ib->wrh != ib->h) {
|
|
i = 0;
|
|
buf[i++] = UNT;
|
|
buf[i++] = UNL;
|
|
buf[i++] = LAD | ib->h->pad;
|
|
if (ib->h->sad)
|
|
buf[i++] = LAD | TAD | ib->h->sad;
|
|
buf[i++] = TAD | 0;
|
|
i = pio_cmd(ib->u, buf, i);
|
|
ib->rdh = NULL;
|
|
ib->wrh = ib->h;
|
|
config_eos(ib->u, ib->h);
|
|
}
|
|
upd7210_goto_standby(ib->u);
|
|
ib->doeoi = ib->h->eot;
|
|
i = pio_odata(ib->u, bp, ib->ap->cnt);
|
|
upd7210_take_ctrl_async(ib->u);
|
|
ib->ap->__ibcnt = i;
|
|
free(bp, M_IBFOO);
|
|
return (0);
|
|
}
|
|
|
|
#define ibwrta NULL
|
|
#define ibwrtf NULL
|
|
#define ibwrtkey NULL
|
|
#define ibxtrc NULL
|
|
|
|
static struct ibhandler {
|
|
const char *name;
|
|
enum h_kind kind;
|
|
ibhandler_t *func;
|
|
u_int args;
|
|
} ibhandlers[] = {
|
|
[__ID_IBASK] = { "ibask", H_EITHER, ibask, __F_HANDLE | __F_OPTION | __F_RETVAL },
|
|
[__ID_IBBNA] = { "ibbna", H_DEV, ibbna, __F_HANDLE | __F_BDNAME },
|
|
[__ID_IBCAC] = { "ibcac", H_BOARD, ibcac, __F_HANDLE | __F_V },
|
|
[__ID_IBCLR] = { "ibclr", H_DEV, ibclr, __F_HANDLE },
|
|
[__ID_IBCMD] = { "ibcmd", H_BOARD, ibcmd, __F_HANDLE | __F_BUFFER | __F_CNT },
|
|
[__ID_IBCMDA] = { "ibcmda", H_BOARD, ibcmda, __F_HANDLE | __F_BUFFER | __F_CNT },
|
|
[__ID_IBCONFIG] = { "ibconfig", H_EITHER, ibconfig, __F_HANDLE | __F_OPTION | __F_VALUE },
|
|
[__ID_IBDEV] = { "ibdev", 0, ibdev, __F_BOARDID | __F_PAD | __F_SAD | __F_TMO | __F_EOT | __F_EOS },
|
|
[__ID_IBDIAG] = { "ibdiag", H_EITHER, ibdiag, __F_HANDLE | __F_BUFFER | __F_CNT },
|
|
[__ID_IBDMA] = { "ibdma", H_EITHER, ibdma, __F_HANDLE | __F_V },
|
|
[__ID_IBEOS] = { "ibeos", H_EITHER, ibeos, __F_HANDLE | __F_EOS },
|
|
[__ID_IBEOT] = { "ibeot", H_EITHER, ibeot, __F_HANDLE | __F_EOT },
|
|
[__ID_IBEVENT] = { "ibevent", H_BOARD, ibevent, __F_HANDLE | __F_EVENT },
|
|
[__ID_IBFIND] = { "ibfind", 0, ibfind, __F_BDNAME },
|
|
[__ID_IBGTS] = { "ibgts", H_BOARD, ibgts, __F_HANDLE | __F_V },
|
|
[__ID_IBIST] = { "ibist", H_BOARD, ibist, __F_HANDLE | __F_V },
|
|
[__ID_IBLINES] = { "iblines", H_BOARD, iblines, __F_HANDLE | __F_LINES },
|
|
[__ID_IBLLO] = { "ibllo", H_EITHER, ibllo, __F_HANDLE },
|
|
[__ID_IBLN] = { "ibln", H_BOARD, ibln, __F_HANDLE | __F_PADVAL | __F_SADVAL | __F_LISTENFLAG },
|
|
[__ID_IBLOC] = { "ibloc", H_EITHER, ibloc, __F_HANDLE },
|
|
[__ID_IBONL] = { "ibonl", H_EITHER, ibonl, __F_HANDLE | __F_V },
|
|
[__ID_IBPAD] = { "ibpad", H_EITHER, ibpad, __F_HANDLE | __F_PAD },
|
|
[__ID_IBPCT] = { "ibpct", H_DEV, ibpct, __F_HANDLE },
|
|
[__ID_IBPOKE] = { "ibpoke", H_EITHER, ibpoke, __F_HANDLE | __F_OPTION | __F_VALUE },
|
|
[__ID_IBPPC] = { "ibppc", H_EITHER, ibppc, __F_HANDLE | __F_V },
|
|
[__ID_IBRD] = { "ibrd", H_EITHER, ibrd, __F_HANDLE | __F_BUFFER | __F_CNT },
|
|
[__ID_IBRDA] = { "ibrda", H_EITHER, ibrda, __F_HANDLE | __F_BUFFER | __F_CNT },
|
|
[__ID_IBRDF] = { "ibrdf", H_EITHER, ibrdf, __F_HANDLE | __F_FLNAME },
|
|
[__ID_IBRDKEY] = { "ibrdkey", H_EITHER, ibrdkey, __F_HANDLE | __F_BUFFER | __F_CNT },
|
|
[__ID_IBRPP] = { "ibrpp", H_EITHER, ibrpp, __F_HANDLE | __F_PPR },
|
|
[__ID_IBRSC] = { "ibrsc", H_BOARD, ibrsc, __F_HANDLE | __F_V },
|
|
[__ID_IBRSP] = { "ibrsp", H_DEV, ibrsp, __F_HANDLE | __F_SPR },
|
|
[__ID_IBRSV] = { "ibrsv", H_EITHER, ibrsv, __F_HANDLE | __F_V },
|
|
[__ID_IBSAD] = { "ibsad", H_EITHER, ibsad, __F_HANDLE | __F_SAD },
|
|
[__ID_IBSGNL] = { "ibsgnl", H_EITHER, ibsgnl, __F_HANDLE | __F_V },
|
|
[__ID_IBSIC] = { "ibsic", H_BOARD, ibsic, __F_HANDLE },
|
|
[__ID_IBSRE] = { "ibsre", H_BOARD, ibsre, __F_HANDLE | __F_V },
|
|
[__ID_IBSRQ] = { "ibsrq", H_EITHER, ibsrq, __F_FUNC },
|
|
[__ID_IBSTOP] = { "ibstop", H_EITHER, ibstop, __F_HANDLE },
|
|
[__ID_IBTMO] = { "ibtmo", H_EITHER, ibtmo, __F_HANDLE | __F_TMO },
|
|
[__ID_IBTRAP] = { "ibtrap", H_EITHER, ibtrap, __F_MASK | __F_MODE },
|
|
[__ID_IBTRG] = { "ibtrg", H_DEV, ibtrg, __F_HANDLE },
|
|
[__ID_IBWAIT] = { "ibwait", H_EITHER, ibwait, __F_HANDLE | __F_MASK },
|
|
[__ID_IBWRT] = { "ibwrt", H_EITHER, ibwrt, __F_HANDLE | __F_BUFFER | __F_CNT },
|
|
[__ID_IBWRTA] = { "ibwrta", H_EITHER, ibwrta, __F_HANDLE | __F_BUFFER | __F_CNT },
|
|
[__ID_IBWRTF] = { "ibwrtf", H_EITHER, ibwrtf, __F_HANDLE | __F_FLNAME },
|
|
[__ID_IBWRTKEY] = { "ibwrtkey", H_EITHER, ibwrtkey, __F_HANDLE | __F_BUFFER | __F_CNT },
|
|
[__ID_IBXTRC] = { "ibxtrc", H_EITHER, ibxtrc, __F_HANDLE | __F_BUFFER | __F_CNT },
|
|
};
|
|
|
|
static const u_int max_ibhandler = sizeof ibhandlers / sizeof ibhandlers[0];
|
|
|
|
static void
|
|
ib_dump_args(struct ibhandler *ih, struct ibarg *ap)
|
|
{
|
|
|
|
if (ih->name != NULL)
|
|
printf("%s(", ih->name);
|
|
else
|
|
printf("ibinvalid(");
|
|
printf("[0x%x]", ap->__field);
|
|
if (ap->__field & __F_HANDLE) printf(" handle=%d", ap->handle);
|
|
if (ap->__field & __F_EOS) printf(" eos=0x%x", ap->eos);
|
|
if (ap->__field & __F_EOT) printf(" eot=%d", ap->eot);
|
|
if (ap->__field & __F_TMO) printf(" tmo=%d", ap->tmo);
|
|
if (ap->__field & __F_PAD) printf(" pad=0x%x", ap->pad);
|
|
if (ap->__field & __F_SAD) printf(" sad=0x%x", ap->sad);
|
|
if (ap->__field & __F_BUFFER) printf(" buffer=%p", ap->buffer);
|
|
if (ap->__field & __F_CNT) printf(" cnt=%ld", ap->cnt);
|
|
if (ap->__field & __F_V) printf(" v=%d/0x%x", ap->v, ap->v);
|
|
/* XXX more ... */
|
|
printf(")\n");
|
|
}
|
|
|
|
static int
|
|
gpib_ib_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
|
|
{
|
|
struct upd7210 *u;
|
|
struct ibfoo *ib;
|
|
int error = 0;
|
|
|
|
u = dev->si_drv1;
|
|
|
|
mtx_lock(&u->mutex);
|
|
if (u->busy) {
|
|
mtx_unlock(&u->mutex);
|
|
return (EBUSY);
|
|
}
|
|
u->busy = 1;
|
|
mtx_unlock(&u->mutex);
|
|
|
|
if (u->dmachan >= 0) {
|
|
error = isa_dma_acquire(u->dmachan);
|
|
if (!error) {
|
|
error = isa_dma_init(u->dmachan, PAGE_SIZE, M_WAITOK);
|
|
if (error)
|
|
isa_dma_release(u->dmachan);
|
|
}
|
|
}
|
|
|
|
if (error) {
|
|
mtx_lock(&u->mutex);
|
|
u->busy = 0;
|
|
mtx_unlock(&u->mutex);
|
|
return (error);
|
|
}
|
|
|
|
ib = malloc(sizeof *ib, M_IBFOO, M_WAITOK | M_ZERO);
|
|
LIST_INIT(&ib->handles);
|
|
callout_init(&ib->callout, CALLOUT_MPSAFE);
|
|
ib->unrhdr = new_unrhdr(0, INT_MAX, NULL);
|
|
dev->si_drv2 = ib;
|
|
ib->u = u;
|
|
u->ibfoo = ib;
|
|
u->irq = gpib_ib_irq;
|
|
|
|
upd7210_wr(u, AUXMR, AUXMR_CRST);
|
|
DELAY(10000);
|
|
DELAY(1000);
|
|
upd7210_wr(u, IMR1, 0x00);
|
|
upd7210_wr(u, IMR2, 0x00);
|
|
upd7210_wr(u, SPMR, 0x00);
|
|
upd7210_wr(u, ADR, 0x00);
|
|
upd7210_wr(u, ADR, ADR_ARS | ADR_DL | ADR_DT);
|
|
upd7210_wr(u, ADMR, ADMR_ADM0 | ADMR_TRM0 | ADMR_TRM1);
|
|
upd7210_wr(u, EOSR, 0x00);
|
|
upd7210_wr(u, AUXMR, C_ICR | 8);
|
|
upd7210_wr(u, AUXMR, C_PPR | PPR_U);
|
|
upd7210_wr(u, AUXMR, C_AUXA);
|
|
upd7210_wr(u, AUXMR, C_AUXB + 3);
|
|
upd7210_wr(u, AUXMR, C_AUXE + 0);
|
|
upd7210_wr(u, AUXMR, AUXMR_PON);
|
|
if (u->use_fifo) {
|
|
bus_write_1(u->reg_res[0], imr3, 0x00);
|
|
bus_write_1(u->reg_res[0], cmdr, 0x22); /* soft reset */
|
|
bus_write_1(u->reg_res[0], cmdr, 0x03); /* set system
|
|
* controller bit */
|
|
}
|
|
upd7210_wr(u, AUXMR, AUXMR_CIFC);
|
|
DELAY(100);
|
|
upd7210_wr(u, AUXMR, AUXMR_SIFC);
|
|
upd7210_wr(u, AUXMR, AUXMR_SREN);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
gpib_ib_close(struct cdev *dev, int oflags, int devtype, struct thread *td)
|
|
{
|
|
struct upd7210 *u;
|
|
struct ibfoo *ib;
|
|
|
|
u = dev->si_drv1;
|
|
ib = dev->si_drv2;
|
|
/* XXX: assert pointer consistency */
|
|
|
|
u->ibfoo = NULL;
|
|
/* XXX: free handles */
|
|
dev->si_drv2 = NULL;
|
|
free(ib, M_IBFOO);
|
|
|
|
if (u->dmachan >= 0) {
|
|
isa_dma_release(u->dmachan);
|
|
}
|
|
mtx_lock(&u->mutex);
|
|
u->busy = 0;
|
|
ibdebug = 0;
|
|
upd7210_wr(u, IMR1, 0x00);
|
|
upd7210_wr(u, IMR2, 0x00);
|
|
if (u->use_fifo) {
|
|
bus_write_1(u->reg_res[0], imr3, 0x00);
|
|
bus_write_1(u->reg_res[0], cmdr, 0x02); /* clear system
|
|
* controller bit */
|
|
}
|
|
upd7210_wr(u, AUXMR, AUXMR_CRST);
|
|
DELAY(10000);
|
|
mtx_unlock(&u->mutex);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
gpib_ib_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag, struct thread *td)
|
|
{
|
|
struct ibarg *ap;
|
|
struct ibhandler *ih;
|
|
struct handle *h;
|
|
struct upd7210 *u;
|
|
struct ibfoo *ib;
|
|
int error;
|
|
struct timeval deadline, tv;
|
|
|
|
u = dev->si_drv1;
|
|
ib = u->ibfoo;
|
|
|
|
/* We only support a single ioctl, everything else is a mistake */
|
|
if (cmd != GPIB_IBFOO)
|
|
return (ENOIOCTL);
|
|
|
|
/* Check the identifier and field-bitmap in the arguments. */
|
|
ap = (void *)data;
|
|
if (ap->__ident < 0 || ap->__ident >= max_ibhandler)
|
|
return (EINVAL);
|
|
ih = &ibhandlers[ap->__ident];
|
|
if (ap->__field != ih->args)
|
|
return (EINVAL);
|
|
|
|
if (ibdebug)
|
|
ib_dump_args(ih, ap);
|
|
|
|
if (ih->func == NULL)
|
|
return (EOPNOTSUPP);
|
|
|
|
ap->__iberr = 0;
|
|
ap->__ibsta = 0;
|
|
ap->__ibcnt = 0;
|
|
ap->retval = 0;
|
|
|
|
if (ap->__field & __F_TMO) {
|
|
if (ap->tmo < 0 || ap->tmo >= max_timeouts)
|
|
return (ib_set_error(ap, EARG));
|
|
}
|
|
|
|
if (ap->__field & __F_EOS) {
|
|
if ((ap->eos & ~(REOS | XEOS | BIN | 0xff)) ||
|
|
((ap->eos & (BIN | 0x80)) == 0x80))
|
|
return (ib_set_error(ap, EARG));
|
|
}
|
|
if (ap->__field & __F_PAD) {
|
|
if (ap->pad < 0 || ap->pad > 30)
|
|
return (ib_set_error(ap, EARG));
|
|
}
|
|
if (ap->__field & __F_SAD) {
|
|
if (ap->sad != 0 && (ap->sad < 0x60 || ap->sad > 126))
|
|
return (ib_set_error(ap, EARG));
|
|
}
|
|
|
|
|
|
mtx_lock(&u->mutex);
|
|
|
|
|
|
/* Find the handle, if any */
|
|
h = NULL;
|
|
if ((ap->__field & __F_HANDLE) && gethandle(u, ap, &h)) {
|
|
mtx_unlock(&u->mutex);
|
|
return (0);
|
|
}
|
|
|
|
/* Check that the handle is the right kind */
|
|
if (h != NULL && !(h->kind & ih->kind)) {
|
|
mtx_unlock(&u->mutex);
|
|
return (ib_set_error(ap, EARG));
|
|
}
|
|
|
|
/* Set up handle and deadline */
|
|
if (h != NULL && timevalisset(&h->timeout)) {
|
|
getmicrouptime(&deadline);
|
|
timevaladd(&deadline, &h->timeout);
|
|
} else {
|
|
timevalclear(&deadline);
|
|
}
|
|
|
|
/* Wait for the card to be(come) available, respect deadline */
|
|
while(u->busy != 1) {
|
|
error = msleep(ib, &u->mutex,
|
|
PZERO | PCATCH, "gpib_ibioctl", hz / 10);
|
|
if (error == 0)
|
|
continue;
|
|
mtx_unlock(&u->mutex);
|
|
if (error == EINTR)
|
|
return(ib_set_error(ap, EABO));
|
|
if (error == EWOULDBLOCK && timevalisset(&deadline)) {
|
|
getmicrouptime(&tv);
|
|
if (timevalcmp(&deadline, &tv, <))
|
|
return(ib_had_timeout(ap));
|
|
}
|
|
mtx_lock(&u->mutex);
|
|
}
|
|
u->busy = 2;
|
|
mtx_unlock(&u->mutex);
|
|
|
|
/* Hand over deadline handling to the callout routine */
|
|
ib->ap = ap;
|
|
ib->h = h;
|
|
ib->mode = BUSY;
|
|
ib->deadline = deadline;
|
|
callout_reset(&ib->callout, hz / 5, gpib_ib_timeout, u);
|
|
|
|
error = ih->func(ib);
|
|
|
|
/* Release card */
|
|
ib->mode = IDLE;
|
|
ib->ap = NULL;
|
|
ib->h = NULL;
|
|
timevalclear(&deadline);
|
|
callout_stop(&ib->callout);
|
|
|
|
mtx_lock(&u->mutex);
|
|
u->busy = 1;
|
|
wakeup(ib);
|
|
mtx_unlock(&u->mutex);
|
|
|
|
if (error)
|
|
return(ib_set_errno(ap, error));
|
|
return (0);
|
|
}
|
|
|
|
struct cdevsw gpib_ib_cdevsw = {
|
|
.d_version = D_VERSION,
|
|
.d_name = "gpib_ib",
|
|
.d_open = gpib_ib_open,
|
|
.d_ioctl = gpib_ib_ioctl,
|
|
.d_close = gpib_ib_close,
|
|
};
|