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ac0797c3d1
TNT5004 IC. This involved a major rewrite of a number of things, as this chip no longer supports the NAT7210 legacy mode but requires the host to use the (more modern) FIFO mode. In theory, this also ought to work on the older TNT4882C chip. I'll probably add this as optional support (perhaps by a device.hints flag) later on. By now, FIFO mode is *only* activates iff a TNT5004 chip has been detected (where the old code didn't work at all), while everything else is supposed to use the old code. MFC after: 2 weeks
238 lines
8.4 KiB
C
238 lines
8.4 KiB
C
/*-
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* Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
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* Copyright (c) 2010 Joerg Wunsch <joerg@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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* Locating an actual µPD7210 data book has proven quite impossible for me.
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* There are a fair number of newer chips which are supersets of the µPD7210
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* but they are particular eager to comprehensively mark what the extensions
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* are and what is in the base set. Some even give the registers and their
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* bits new names.
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*
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* The following information is based on a description of the µPD7210 found
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* in an old manual for a VME board which used the chip.
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*/
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#ifndef _DEV_IEEE488_UPD7210_H_
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#define _DEV_IEEE488_UPD7210_H_
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#ifdef _KERNEL
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struct upd7210;
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struct ibfoo;
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/* upd7210 interface definitions for HW drivers */
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typedef int upd7210_irq_t(struct upd7210 *, int);
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struct upd7210 {
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struct resource *reg_res[8];
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struct resource *irq_clear_res;
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u_int reg_offset[8];
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int dmachan;
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int unit;
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int use_fifo;
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/* private stuff */
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struct mtx mutex;
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uint8_t rreg[8];
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uint8_t wreg[8 + 8];
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upd7210_irq_t *irq;
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int busy;
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u_char *buf;
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size_t bufsize;
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u_int buf_wp;
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u_int buf_rp;
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struct cdev *cdev;
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struct ibfoo *ibfoo;
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};
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#ifdef UPD7210_HW_DRIVER
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void upd7210intr(void *);
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void upd7210attach(struct upd7210 *);
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void upd7210detach(struct upd7210 *);
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#endif
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#ifdef UPD7210_SW_DRIVER
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/* upd7210 hardware definitions. */
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/* Write registers */
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enum upd7210_wreg {
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CDOR = 0, /* Command/Data Out Register */
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IMR1 = 1, /* Interrupt Mask Register 1 */
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IMR2 = 2, /* Interrupt Mask Register 2 */
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SPMR = 3, /* Serial Poll Mode Register */
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ADMR = 4, /* ADdress Mode Register */
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AUXMR = 5, /* AUXilliary Mode Register */
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ICR = 5, /* Internal Counter Register */
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PPR = 5, /* Parallel Poll Register */
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AUXRA = 5, /* AUXilliary Register A */
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AUXRB = 5, /* AUXilliary Register B */
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AUXRE = 5, /* AUXilliary Register E */
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ADR = 6, /* ADdress Register */
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EOSR = 7, /* End-Of-String Register */
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};
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/* Read registers */
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enum upd7210_rreg {
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DIR = 0, /* Data In Register */
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ISR1 = 1, /* Interrupt Status Register 1 */
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ISR2 = 2, /* Interrupt Status Register 2 */
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SPSR = 3, /* Serial Poll Status Register */
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ADSR = 4, /* ADdress Status Register */
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CPTR = 5, /* Command Pass Though Register */
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ADR0 = 6, /* ADdress Register 0 */
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ADR1 = 7, /* ADdress Register 1 */
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};
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/* Bits for ISR1 and IMR1 */
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#define IXR1_DI (1 << 0) /* Data In */
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#define IXR1_DO (1 << 1) /* Data Out */
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#define IXR1_ERR (1 << 2) /* Error */
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#define IXR1_DEC (1 << 3) /* Device Clear */
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#define IXR1_ENDRX (1 << 4) /* End Received */
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#define IXR1_DET (1 << 5) /* Device Execute Trigger */
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#define IXR1_APT (1 << 6) /* Address Pass-Through */
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#define IXR1_CPT (1 << 7) /* Command Pass-Through */
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/* Bits for ISR2 and IMR2 */
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#define IXR2_ADSC (1 << 0) /* Addressed Status Change */
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#define IXR2_REMC (1 << 1) /* Remote Change */
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#define IXR2_LOKC (1 << 2) /* Lockout Change */
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#define IXR2_CO (1 << 3) /* Command Out */
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#define ISR2_REM (1 << 4) /* Remove */
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#define IMR2_DMAI (1 << 4) /* DMA In Enable */
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#define ISR2_LOK (1 << 5) /* Lockout */
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#define IMR2_DMAO (1 << 5) /* DMA Out Enable */
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#define IXR2_SRQI (1 << 6) /* Service Request Input */
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#define ISR2_INT (1 << 7) /* Interrupt */
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#define SPSR_PEND (1 << 6) /* Pending */
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#define SPMR_RSV (1 << 6) /* Request SerVice */
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#define ADSR_MJMN (1 << 0) /* MaJor MiNor */
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#define ADSR_TA (1 << 1) /* Talker Active */
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#define ADSR_LA (1 << 2) /* Listener Active */
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#define ADSR_TPAS (1 << 3) /* Talker Primary Addr. State */
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#define ADSR_LPAS (1 << 4) /* Listener Primary Addr. State */
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#define ADSR_SPMS (1 << 5) /* Serial Poll Mode State */
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#define ADSR_ATN (1 << 6) /* Attention */
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#define ADSR_CIC (1 << 7) /* Controller In Charge */
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#define ADMR_ADM0 (1 << 0) /* Address Mode 0 */
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#define ADMR_ADM1 (1 << 1) /* Address Mode 1 */
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#define ADMR_TRM0 (1 << 4) /* Transmit/Receive Mode 0 */
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#define ADMR_TRM1 (1 << 5) /* Transmit/Receive Mode 1 */
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#define ADMR_LON (1 << 6) /* Listen Only */
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#define ADMR_TON (1 << 7) /* Talk Only */
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/* Constant part of overloaded write registers */
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#define C_ICR 0x20
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#define C_PPR 0x60
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#define C_AUXA 0x80
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#define C_AUXB 0xa0
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#define C_AUXE 0xc0
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#define AUXMR_PON 0x00 /* Immediate Execute pon */
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#define AUXMR_CPP 0x01 /* Clear Parallel Poll */
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#define AUXMR_CRST 0x02 /* Chip Reset */
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#define AUXMR_RFD 0x03 /* Finish Handshake */
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#define AUXMR_TRIG 0x04 /* Trigger */
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#define AUXMR_RTL 0x05 /* Return to local */
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#define AUXMR_SEOI 0x06 /* Send EOI */
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#define AUXMR_NVSA 0x07 /* Non-Valid Secondary cmd/addr */
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/* 0x08 undefined/unknown */
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#define AUXMR_SPP 0x09 /* Set Parallel Poll */
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/* 0x0a undefined/unknown */
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/* 0x0b undefined/unknown */
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/* 0x0c undefined/unknown */
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/* 0x0d undefined/unknown */
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/* 0x0e undefined/unknown */
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#define AUXMR_VSA 0x0f /* Valid Secondary cmd/addr */
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#define AUXMR_GTS 0x10 /* Go to Standby */
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#define AUXMR_TCA 0x11 /* Take Control Async (pulsed) */
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#define AUXMR_TCS 0x12 /* Take Control Synchronously */
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#define AUXMR_LISTEN 0x13 /* Listen */
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#define AUXMR_DSC 0x14 /* Disable System Control */
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/* 0x15 undefined/unknown */
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#define AUXMR_SIFC 0x16 /* Set IFC */
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#define AUXMR_CREN 0x17 /* Clear REN */
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/* 0x18 undefined/unknown */
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/* 0x19 undefined/unknown */
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#define AUXMR_TCSE 0x1a /* Take Control Sync on End */
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#define AUXMR_LCM 0x1b /* Listen Continuously Mode */
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#define AUXMR_LUNL 0x1c /* Local Unlisten */
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#define AUXMR_EPP 0x1d /* Execute Parallel Poll */
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#define AUXMR_CIFC 0x1e /* Clear IFC */
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#define AUXMR_SREN 0x1f /* Set REN */
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#define PPR_U (1 << 4) /* Unconfigure */
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#define PPR_S (1 << 3) /* Status Polarity */
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#define AUXA_HLDA (1 << 0) /* Holdoff on All */
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#define AUXA_HLDE (1 << 1) /* Holdoff on END */
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#define AUXA_REOS (1 << 2) /* End on EOS received */
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#define AUXA_XEOS (1 << 3) /* Transmit END with EOS */
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#define AUXA_BIN (1 << 4) /* Binary */
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#define AUXB_CPTE (1 << 0) /* Cmd Pass Through Enable */
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#define AUXB_SPEOI (1 << 1) /* Send Serial Poll EOI */
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#define AUXB_TRI (1 << 2) /* Three-State Timing */
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#define AUXB_INV (1 << 3) /* Invert */
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#define AUXB_ISS (1 << 4) /* Individual Status Select */
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#define AUXE_DHDT (1 << 0) /* DAC Holdoff on DTAS */
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#define AUXE_DHDC (1 << 1) /* DAC Holdoff on DCAS */
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#define ADR0_DL0 (1 << 5) /* Disable Listener 0 */
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#define ADR0_DT0 (1 << 6) /* Disable Talker 0 */
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#define ADR_DL (1 << 5) /* Disable Listener */
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#define ADR_DT (1 << 6) /* Disable Talker */
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#define ADR_ARS (1 << 7) /* Address Register Select */
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#define ADR1_DL1 (1 << 5) /* Disable Listener 1 */
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#define ADR1_DT1 (1 << 6) /* Disable Talker 1 */
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#define ADR1_EOI (1 << 7) /* End or Identify */
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/* Stuff from software drivers */
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extern struct cdevsw gpib_ib_cdevsw;
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/* Stuff from upd7210.c */
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void upd7210_print_isr(u_int isr1, u_int isr2);
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u_int upd7210_rd(struct upd7210 *u, enum upd7210_rreg reg);
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void upd7210_wr(struct upd7210 *u, enum upd7210_wreg reg, u_int val);
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int upd7210_take_ctrl_async(struct upd7210 *u);
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int upd7210_goto_standby(struct upd7210 *u);
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#endif /* UPD7210_SW_DRIVER */
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#endif /* _KERNEL */
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#endif /* _DEV_IEEE488_UPD7210_H_ */
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