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eaf86d1678
- Add a new intr_event method ie_assign_cpu() that is invoked when the MI
code wishes to bind an interrupt source to an individual CPU. The MD
code may reject the binding with an error. If an assign_cpu function
is not provided, then the kernel assumes the platform does not support
binding interrupts to CPUs and fails all requests to do so.
- Bind ithreads to CPUs on their next execution loop once an interrupt
event is bound to a CPU. Only shared ithreads are bound. We currently
leave private ithreads for drivers using filters + ithreads in the
INTR_FILTER case unbound.
- A new intr_event_bind() routine is used to bind an interrupt event to
a CPU.
- Implement binding on amd64 and i386 by way of the existing pic_assign_cpu
PIC method.
- For x86, provide a 'intr_bind(IRQ, cpu)' wrapper routine that looks up
an interrupt source and binds its interrupt event to the specified CPU.
MI code can currently (ab)use this by doing:
intr_bind(rman_get_start(irq_res), cpu);
however, I plan to add a truly MI interface (probably a bus_bind_intr(9))
where the implementation in the x86 nexus(4) driver would end up calling
intr_bind() internally.
Requested by: kmacy, gallatin, jeff
Tested on: {amd64, i386} x {regular, INTR_FILTER}
160 lines
5.5 KiB
C
160 lines
5.5 KiB
C
/*-
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* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __MACHINE_INTR_MACHDEP_H__
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#define __MACHINE_INTR_MACHDEP_H__
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#ifdef _KERNEL
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/*
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* The maximum number of I/O interrupts we allow. This number is rather
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* arbitrary as it is just the maximum IRQ resource value. The interrupt
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* source for a given IRQ maps that I/O interrupt to device interrupt
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* source whether it be a pin on an interrupt controller or an MSI interrupt.
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* The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
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* interrupts allocate IDT vectors on demand. Currently we have 191 IDT
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* vectors available for device interrupts. On many systems with I/O APICs,
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* a lot of the IRQs are not used, so this number can be much larger than
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* 191 and still be safe since only interrupt sources in actual use will
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* allocate IDT vectors.
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*
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* The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs.
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* IRQ values beyond 256 are used by MSI. We leave 255 unused to avoid
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* confusion since 255 is used in PCI to indicate an invalid IRQ.
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*/
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#define NUM_MSI_INTS 128
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#define FIRST_MSI_INT 256
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#define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS)
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/*
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* Default base address for MSI messages on x86 platforms.
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*/
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#define MSI_INTEL_ADDR_BASE 0xfee00000
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/*
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* - 1 ??? dummy counter.
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* - 2 counters for each I/O interrupt.
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* - 1 counter for each CPU for lapic timer.
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* - 7 counters for each CPU for IPI counters for SMP.
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*/
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#ifdef SMP
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#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU)
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#else
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#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1)
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#endif
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#ifndef LOCORE
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typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
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#define IDTVEC(name) __CONCAT(X,name)
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struct intsrc;
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/*
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* Methods that a PIC provides to mask/unmask a given interrupt source,
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* "turn on" the interrupt on the CPU side by setting up an IDT entry, and
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* return the vector associated with this source.
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*/
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struct pic {
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void (*pic_enable_source)(struct intsrc *);
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void (*pic_disable_source)(struct intsrc *, int);
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void (*pic_eoi_source)(struct intsrc *);
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void (*pic_enable_intr)(struct intsrc *);
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void (*pic_disable_intr)(struct intsrc *);
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int (*pic_vector)(struct intsrc *);
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int (*pic_source_pending)(struct intsrc *);
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void (*pic_suspend)(struct pic *);
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void (*pic_resume)(struct pic *);
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int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
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enum intr_polarity);
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void (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
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STAILQ_ENTRY(pic) pics;
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};
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/* Flags for pic_disable_source() */
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enum {
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PIC_EOI,
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PIC_NO_EOI,
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};
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/*
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* An interrupt source. The upper-layer code uses the PIC methods to
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* control a given source. The lower-layer PIC drivers can store additional
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* private data in a given interrupt source such as an interrupt pin number
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* or an I/O APIC pointer.
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*/
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struct intsrc {
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struct pic *is_pic;
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struct intr_event *is_event;
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u_long *is_count;
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u_long *is_straycount;
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u_int is_index;
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u_int is_handlers;
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};
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struct trapframe;
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extern struct mtx icu_lock;
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extern int elcr_found;
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/* XXX: The elcr_* prototypes probably belong somewhere else. */
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int elcr_probe(void);
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enum intr_trigger elcr_read_trigger(u_int irq);
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void elcr_resume(void);
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void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
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#ifdef SMP
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void intr_add_cpu(u_int cpu);
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#endif
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int intr_add_handler(const char *name, int vector, driver_filter_t filter,
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driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep);
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#ifdef SMP
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int intr_bind(u_int vector, u_char cpu);
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#endif
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int intr_config_intr(int vector, enum intr_trigger trig,
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enum intr_polarity pol);
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void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
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struct intsrc *intr_lookup_source(int vector);
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int intr_register_pic(struct pic *pic);
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int intr_register_source(struct intsrc *isrc);
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int intr_remove_handler(void *cookie);
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void intr_resume(void);
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void intr_suspend(void);
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void intrcnt_add(const char *name, u_long **countp);
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void nexus_add_irq(u_long irq);
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int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
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void msi_init(void);
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int msi_map(int irq, uint64_t *addr, uint32_t *data);
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int msi_release(int* irqs, int count);
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int msix_alloc(device_t dev, int *irq);
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int msix_release(int irq);
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#endif /* !LOCORE */
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#endif /* _KERNEL */
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#endif /* !__MACHINE_INTR_MACHDEP_H__ */
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