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add35ed5b8
to check the status property in their probe routines. Simplebus used to only instantiate its children whose status="okay" but that was improper behavior, fixed in r261352. Now that it doesn't check anymore and probes all its children; the children all have to do the check because really only the children know how to properly interpret their status property strings. Right now all existing drivers only understand "okay" versus something- that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
363 lines
9.4 KiB
C
363 lines
9.4 KiB
C
/*
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* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* Copyright (c) 2012 Damjan Marion <dmarion@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#define SP804_TIMER1_LOAD 0x00
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#define SP804_TIMER1_VALUE 0x04
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#define SP804_TIMER1_CONTROL 0x08
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#define TIMER_CONTROL_EN (1 << 7)
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#define TIMER_CONTROL_FREERUN (0 << 6)
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#define TIMER_CONTROL_PERIODIC (1 << 6)
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#define TIMER_CONTROL_INTREN (1 << 5)
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#define TIMER_CONTROL_DIV1 (0 << 2)
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#define TIMER_CONTROL_DIV16 (1 << 2)
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#define TIMER_CONTROL_DIV256 (2 << 2)
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#define TIMER_CONTROL_32BIT (1 << 1)
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#define TIMER_CONTROL_ONESHOT (1 << 0)
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#define SP804_TIMER1_INTCLR 0x0C
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#define SP804_TIMER1_RIS 0x10
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#define SP804_TIMER1_MIS 0x14
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#define SP804_TIMER1_BGLOAD 0x18
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#define SP804_TIMER2_LOAD 0x20
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#define SP804_TIMER2_VALUE 0x24
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#define SP804_TIMER2_CONTROL 0x28
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#define SP804_TIMER2_INTCLR 0x2C
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#define SP804_TIMER2_RIS 0x30
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#define SP804_TIMER2_MIS 0x34
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#define SP804_TIMER2_BGLOAD 0x38
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#define SP804_PERIPH_ID0 0xFE0
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#define SP804_PERIPH_ID1 0xFE4
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#define SP804_PERIPH_ID2 0xFE8
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#define SP804_PERIPH_ID3 0xFEC
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#define SP804_PRIMECELL_ID0 0xFF0
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#define SP804_PRIMECELL_ID1 0xFF4
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#define SP804_PRIMECELL_ID2 0xFF8
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#define SP804_PRIMECELL_ID3 0xFFC
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#define DEFAULT_FREQUENCY 1000000
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/*
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* QEMU seems to have problem with full frequency
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*/
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#define DEFAULT_DIVISOR 16
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#define DEFAULT_CONTROL_DIV TIMER_CONTROL_DIV16
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struct sp804_timer_softc {
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struct resource* mem_res;
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struct resource* irq_res;
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void* intr_hl;
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uint32_t sysclk_freq;
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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struct timecounter tc;
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bool et_enabled;
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struct eventtimer et;
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int timer_initialized;
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};
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/* Read/Write macros for Timer used as timecounter */
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#define sp804_timer_tc_read_4(reg) \
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bus_space_read_4(sc->bst, sc->bsh, reg)
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#define sp804_timer_tc_write_4(reg, val) \
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bus_space_write_4(sc->bst, sc->bsh, reg, val)
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static unsigned sp804_timer_tc_get_timecount(struct timecounter *);
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static unsigned
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sp804_timer_tc_get_timecount(struct timecounter *tc)
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{
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struct sp804_timer_softc *sc = tc->tc_priv;
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return 0xffffffff - sp804_timer_tc_read_4(SP804_TIMER1_VALUE);
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}
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static int
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sp804_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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{
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struct sp804_timer_softc *sc = et->et_priv;
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uint32_t count, reg;
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if (first != 0) {
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sc->et_enabled = 1;
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count = ((uint32_t)et->et_frequency * first) >> 32;
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sp804_timer_tc_write_4(SP804_TIMER2_LOAD, count);
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reg = TIMER_CONTROL_32BIT | TIMER_CONTROL_INTREN |
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TIMER_CONTROL_PERIODIC | DEFAULT_CONTROL_DIV |
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TIMER_CONTROL_EN;
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sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);
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return (0);
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}
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if (period != 0) {
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panic("period");
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}
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return (EINVAL);
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}
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static int
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sp804_timer_stop(struct eventtimer *et)
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{
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struct sp804_timer_softc *sc = et->et_priv;
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uint32_t reg;
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sc->et_enabled = 0;
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reg = sp804_timer_tc_read_4(SP804_TIMER2_CONTROL);
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reg &= ~(TIMER_CONTROL_EN);
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sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg);
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return (0);
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}
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static int
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sp804_timer_intr(void *arg)
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{
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struct sp804_timer_softc *sc = arg;
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static uint32_t prev = 0;
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uint32_t x = 0;
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x = sp804_timer_tc_read_4(SP804_TIMER1_VALUE);
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prev =x ;
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sp804_timer_tc_write_4(SP804_TIMER2_INTCLR, 1);
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if (sc->et_enabled) {
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if (sc->et.et_active) {
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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}
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}
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return (FILTER_HANDLED);
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}
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static int
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sp804_timer_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_is_compatible(dev, "arm,sp804")) {
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device_set_desc(dev, "SP804 System Timer");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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sp804_timer_attach(device_t dev)
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{
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struct sp804_timer_softc *sc = device_get_softc(dev);
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int rid = 0;
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int i;
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uint32_t id, reg;
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phandle_t node;
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pcell_t clock;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "could not allocate memory resource\n");
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return (ENXIO);
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}
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sc->bst = rman_get_bustag(sc->mem_res);
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sc->bsh = rman_get_bushandle(sc->mem_res);
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/* Request the IRQ resources */
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
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if (sc->irq_res == NULL) {
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device_printf(dev, "Error: could not allocate irq resources\n");
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return (ENXIO);
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}
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sc->sysclk_freq = DEFAULT_FREQUENCY;
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/* Get the base clock frequency */
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node = ofw_bus_get_node(dev);
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if ((OF_getprop(node, "clock-frequency", &clock, sizeof(clock))) > 0) {
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sc->sysclk_freq = fdt32_to_cpu(clock);
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}
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/* Setup and enable the timer */
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if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK,
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sp804_timer_intr, NULL, sc,
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&sc->intr_hl) != 0) {
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bus_release_resource(dev, SYS_RES_IRQ, rid,
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sc->irq_res);
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device_printf(dev, "Unable to setup the clock irq handler.\n");
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return (ENXIO);
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}
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sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, 0);
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sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, 0);
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/*
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* Timer 1, timecounter
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*/
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sc->tc.tc_frequency = sc->sysclk_freq;
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sc->tc.tc_name = "SP804 Time Counter";
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sc->tc.tc_get_timecount = sp804_timer_tc_get_timecount;
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sc->tc.tc_poll_pps = NULL;
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sc->tc.tc_counter_mask = ~0u;
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sc->tc.tc_quality = 1000;
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sc->tc.tc_priv = sc;
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sp804_timer_tc_write_4(SP804_TIMER1_VALUE, 0xffffffff);
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sp804_timer_tc_write_4(SP804_TIMER1_LOAD, 0xffffffff);
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reg = TIMER_CONTROL_PERIODIC | TIMER_CONTROL_32BIT;
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sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);
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reg |= TIMER_CONTROL_EN;
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sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg);
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tc_init(&sc->tc);
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/*
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* Timer 2, event timer
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*/
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sc->et_enabled = 0;
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sc->et.et_name = malloc(64, M_DEVBUF, M_NOWAIT | M_ZERO);
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sprintf(sc->et.et_name, "SP804 Event Timer %d",
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device_get_unit(dev));
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sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
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sc->et.et_quality = 1000;
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sc->et.et_frequency = sc->sysclk_freq / DEFAULT_DIVISOR;
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sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
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sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
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sc->et.et_start = sp804_timer_start;
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sc->et.et_stop = sp804_timer_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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id = 0;
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for (i = 3; i >= 0; i--) {
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id = (id << 8) |
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(sp804_timer_tc_read_4(SP804_PERIPH_ID0 + i*4) & 0xff);
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}
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device_printf(dev, "peripheral ID: %08x\n", id);
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id = 0;
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for (i = 3; i >= 0; i--) {
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id = (id << 8) |
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(sp804_timer_tc_read_4(SP804_PRIMECELL_ID0 + i*4) & 0xff);
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}
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device_printf(dev, "PrimeCell ID: %08x\n", id);
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sc->timer_initialized = 1;
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return (0);
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}
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static device_method_t sp804_timer_methods[] = {
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DEVMETHOD(device_probe, sp804_timer_probe),
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DEVMETHOD(device_attach, sp804_timer_attach),
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{ 0, 0 }
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};
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static driver_t sp804_timer_driver = {
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"timer",
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sp804_timer_methods,
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sizeof(struct sp804_timer_softc),
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};
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static devclass_t sp804_timer_devclass;
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DRIVER_MODULE(sp804_timer, simplebus, sp804_timer_driver, sp804_timer_devclass, 0, 0);
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void
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DELAY(int usec)
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{
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int32_t counts;
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uint32_t first, last;
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device_t timer_dev;
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struct sp804_timer_softc *sc;
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int timer_initialized = 0;
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timer_dev = devclass_get_device(sp804_timer_devclass, 0);
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if (timer_dev) {
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sc = device_get_softc(timer_dev);
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if (sc)
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timer_initialized = sc->timer_initialized;
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}
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if (!timer_initialized) {
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/*
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* Timer is not initialized yet
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*/
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for (; usec > 0; usec--)
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for (counts = 200; counts > 0; counts--)
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/* Prevent gcc from optimizing out the loop */
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cpufunc_nullop();
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return;
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}
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/* Get the number of times to count */
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counts = usec * ((sc->tc.tc_frequency / 1000000) + 1);
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first = sp804_timer_tc_get_timecount(&sc->tc);
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while (counts > 0) {
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last = sp804_timer_tc_get_timecount(&sc->tc);
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if (last == first)
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continue;
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if (last>first) {
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counts -= (int32_t)(last - first);
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} else {
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counts -= (int32_t)((0xFFFFFFFF - first) + last);
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}
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first = last;
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}
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}
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