Peter Grehan 112a8d7bdb Major overhaul of common trap code ... - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD		2004-02-04 13:10:25 +00:00
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aim	Major overhaul of common trap code	2004-02-04 13:10:25 +00:00
compile
conf	- Recruit some new ULE users by making it the default scheduler in GENERIC.	2004-01-24 21:38:52 +00:00
include	Move temporary register save area from exception-vector memory to	2004-02-04 12:56:15 +00:00
ofw	A syscons implementation using the 8-bit framebuffer set up by	2004-01-21 05:16:23 +00:00
powermac	- removed debug printf that was a false positive on non-OpenPIC systems	2004-02-04 04:53:09 +00:00
powerpc	Major overhaul of common trap code	2004-02-04 13:10:25 +00:00
psim	Catch up with ATA UMA changes	2004-01-15 23:52:32 +00:00