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8dee0fd04c
r235162: Initial LPC32x0 support. Includes DTS file for Embedded Artists EA3250 board. Peripherals currently supported: - Serial ports - Interrupt controller - Timers - Ethernet - USB host - Framebuffer (in conjunction with SSD1289 LCD controller) - RTC - SPI - GPIO Submitted by: Jakub Wojciech Klama <jceel@freebsd.org>
244 lines
5.5 KiB
C
244 lines
5.5 KiB
C
/*-
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* Copyright (c) 2010 Jakub Wojciech Klama <jceel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timetc.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/lpc/lpcreg.h>
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struct lpc_intc_softc {
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struct resource * li_res;
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bus_space_tag_t li_bst;
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bus_space_handle_t li_bsh;
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};
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static int lpc_intc_probe(device_t);
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static int lpc_intc_attach(device_t);
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static void lpc_intc_eoi(void *);
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static struct lpc_intc_softc *intc_softc = NULL;
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#define intc_read_4(reg) \
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bus_space_read_4(intc_softc->li_bst, intc_softc->li_bsh, reg)
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#define intc_write_4(reg, val) \
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bus_space_write_4(intc_softc->li_bst, intc_softc->li_bsh, reg, val)
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static int
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lpc_intc_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "lpc,pic"))
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return (ENXIO);
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device_set_desc(dev, "LPC32x0 Interrupt Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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lpc_intc_attach(device_t dev)
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{
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struct lpc_intc_softc *sc = device_get_softc(dev);
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int rid = 0;
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if (intc_softc)
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return (ENXIO);
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sc->li_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->li_res) {
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device_printf(dev, "could not alloc resources\n");
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return (ENXIO);
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}
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sc->li_bst = rman_get_bustag(sc->li_res);
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sc->li_bsh = rman_get_bushandle(sc->li_res);
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intc_softc = sc;
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arm_post_filter = lpc_intc_eoi;
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/* Clear interrupt status registers and disable all interrupts */
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intc_write_4(LPC_INTC_MIC_ER, 0);
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intc_write_4(LPC_INTC_SIC1_ER, 0);
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intc_write_4(LPC_INTC_SIC2_ER, 0);
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intc_write_4(LPC_INTC_MIC_RSR, ~0);
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intc_write_4(LPC_INTC_SIC1_RSR, ~0);
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intc_write_4(LPC_INTC_SIC2_RSR, ~0);
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return (0);
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}
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static device_method_t lpc_intc_methods[] = {
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DEVMETHOD(device_probe, lpc_intc_probe),
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DEVMETHOD(device_attach, lpc_intc_attach),
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{ 0, 0 }
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};
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static driver_t lpc_intc_driver = {
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"pic",
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lpc_intc_methods,
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sizeof(struct lpc_intc_softc),
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};
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static devclass_t lpc_intc_devclass;
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DRIVER_MODULE(pic, simplebus, lpc_intc_driver, lpc_intc_devclass, 0, 0);
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int
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arm_get_next_irq(int last)
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{
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uint32_t value;
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int i;
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/* IRQs 0-31 are mapped to LPC_INTC_MIC_SR */
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value = intc_read_4(LPC_INTC_MIC_SR);
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for (i = 0; i < 32; i++) {
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if (value & (1 << i))
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return (i);
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}
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/* IRQs 32-63 are mapped to LPC_INTC_SIC1_SR */
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value = intc_read_4(LPC_INTC_SIC1_SR);
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for (i = 0; i < 32; i++) {
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if (value & (1 << i))
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return (i + 32);
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}
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/* IRQs 64-95 are mapped to LPC_INTC_SIC2_SR */
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value = intc_read_4(LPC_INTC_SIC2_SR);
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for (i = 0; i < 32; i++) {
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if (value & (1 << i))
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return (i + 64);
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}
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return (-1);
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}
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void
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arm_mask_irq(uintptr_t nb)
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{
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int reg;
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uint32_t value;
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/* Make sure that interrupt isn't active already */
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lpc_intc_eoi((void *)nb);
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if (nb > 63) {
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nb -= 64;
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reg = LPC_INTC_SIC2_ER;
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} else if (nb > 31) {
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nb -= 32;
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reg = LPC_INTC_SIC1_ER;
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} else
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reg = LPC_INTC_MIC_ER;
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/* Clear bit in ER register */
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value = intc_read_4(reg);
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value &= ~(1 << nb);
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intc_write_4(reg, value);
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}
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void
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arm_unmask_irq(uintptr_t nb)
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{
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int reg;
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uint32_t value;
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if (nb > 63) {
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nb -= 64;
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reg = LPC_INTC_SIC2_ER;
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} else if (nb > 31) {
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nb -= 32;
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reg = LPC_INTC_SIC1_ER;
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} else
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reg = LPC_INTC_MIC_ER;
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/* Set bit in ER register */
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value = intc_read_4(reg);
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value |= (1 << nb);
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intc_write_4(reg, value);
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}
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static void
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lpc_intc_eoi(void *data)
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{
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int reg;
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int nb = (int)data;
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uint32_t value;
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if (nb > 63) {
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nb -= 64;
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reg = LPC_INTC_SIC2_RSR;
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} else if (nb > 31) {
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nb -= 32;
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reg = LPC_INTC_SIC1_RSR;
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} else
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reg = LPC_INTC_MIC_RSR;
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/* Set bit in RSR register */
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value = intc_read_4(reg);
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value |= (1 << nb);
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intc_write_4(reg, value);
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}
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struct fdt_fixup_entry fdt_fixup_table[] = {
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{ NULL, NULL }
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};
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static int
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fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
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int *pol)
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{
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if (!fdt_is_compatible(node, "lpc,pic"))
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return (ENXIO);
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*interrupt = fdt32_to_cpu(intr[0]);
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*trig = INTR_TRIGGER_CONFORM;
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*pol = INTR_POLARITY_CONFORM;
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return (0);
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}
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fdt_pic_decode_t fdt_pic_table[] = {
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&fdt_pic_decode_ic,
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NULL
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};
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