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fc28edf53e
Submitted by: Lee Cremeans <lee@st-lcremean.tidalwave.net>
1439 lines
35 KiB
C
1439 lines
35 KiB
C
/*
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* Copyright 1996 Massachusetts Institute of Technology
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*
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby
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* granted, provided that both the above copyright notice and this
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* permission notice appear in all copies, that both the above
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* copyright notice and this permission notice appear in all
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* supporting documentation, and that the name of M.I.T. not be used
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* in advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission. M.I.T. makes
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* no representations about the suitability of this software for any
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* purpose. It is provided "as is" without express or implied
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* warranty.
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*
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* THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
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* ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
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* SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: ide_pci.c,v 1.18 1998/12/14 05:49:04 dillon Exp $
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*/
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#include "pci.h"
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#if NPCI > 0
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#include "opt_wd.h"
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#include "wd.h"
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#if NWDC > 0
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/buf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <i386/isa/wdreg.h>
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#ifdef PC98
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#include <pc98/pc98/pc98.h>
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#else
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#include <i386/isa/isa.h>
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#endif
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#include <i386/isa/isa_device.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include <pci/ide_pcireg.h>
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#ifndef MIN
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#define MIN(a,b) (((a)<(b))?(a):(b))
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#endif
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#define PROMISE_ULTRA33 0x4d33105a
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struct ide_pci_cookie; /* structs vendor_fns, ide_pci_cookie are recursive */
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struct vendor_fns {
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int (*vendor_dmainit) /* initialize DMA controller and drive */
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(struct ide_pci_cookie *cookie,
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struct wdparams *wp,
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int (*wdcmd)(int, void *),
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void *);
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void (*vendor_status) /* prints off DMA timing info */
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(struct ide_pci_cookie *cookie);
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};
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/*
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* XXX the fact that this list keeps all kinds of info on PCI controllers
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* is pretty grotty-- much of this should be replaced by a proper integration
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* of PCI probes into the wd driver.
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* XXX if we're going to support native-PCI controllers, we also need to
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* keep the address of the IDE control block register, which is something wd.c
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* needs to know, which is why this info is in the wrong place.
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*/
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struct ide_pci_cookie {
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LIST_ENTRY(ide_pci_cookie) le;
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int iobase_wd;
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int ctlr; /* controller 0/1 on PCI IDE interface */
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int unit;
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int iobase_bm; /* SFF-8038 control registers */
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int altiobase_wd;
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pcici_t tag;
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pcidi_t type;
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struct ide_pci_prd *prd;
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struct vendor_fns vs;
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};
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struct ide_pci_softc {
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LIST_HEAD(, ide_pci_cookie) cookies;
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};
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static int
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generic_dmainit(struct ide_pci_cookie *cookie,
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struct wdparams *wp,
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int (*wdcmd)(int, void *),
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void *wdinfo);
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static void
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generic_status(struct ide_pci_cookie *cookie);
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static void
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via_571_status(struct ide_pci_cookie *cookie);
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static int
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via_571_dmainit(struct ide_pci_cookie *cookie,
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struct wdparams *wp,
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int (*wdcmd)(int, void *),
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void *wdinfo);
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static void
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intel_piix_dump_drive(char *ctlr,
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int sitre,
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int is_piix4,
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int word40,
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int word44,
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int word48,
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int word4a,
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int drive);
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static void
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intel_piix_status(struct ide_pci_cookie *cookie);
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static int
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intel_piix_dmainit(struct ide_pci_cookie *cookie,
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struct wdparams *wp,
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int (*wdcmd)(int, void *),
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void *wdinfo);
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static struct ide_pci_cookie *
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mkcookie(int iobase_wd,
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int ctlr,
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int unit,
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int iobase_bm,
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pcici_t tag,
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pcidi_t type,
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struct vendor_fns *vp,
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int altiobase_wd);
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static void ide_pci_attach(pcici_t tag, int unit);
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static void *ide_pci_candma(int, int);
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static int ide_pci_dmainit(void *,
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struct wdparams *,
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int (*)(int, void *),
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void *);
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static int ide_pci_dmaverify(void *, char *, u_long, int);
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static int ide_pci_dmasetup(void *, char *, u_long, int);
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static void ide_pci_dmastart(void *);
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static int ide_pci_dmadone(void *);
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static int ide_pci_status(void *);
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static int ide_pci_iobase(void *xcp);
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static int ide_pci_altiobase(void *xcp);
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static struct ide_pci_softc softc;
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static int ide_pci_softc_cookies_initted = 0;
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extern struct isa_driver wdcdriver;
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/*
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* PRD_ALLOC_SIZE should be something that will not be allocated across a 64k
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* boundary.
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* PRD_MAX_SEGS is defined to be the maximum number of segments required for
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* a transfer on an IDE drive, for an xfer that is linear in virtual memory.
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* PRD_BUF_SIZE is the size of the buffer needed for a PRD table.
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*/
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#define PRD_ALLOC_SIZE PAGE_SIZE
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#define PRD_MAX_SEGS ((256 * 512 / PAGE_SIZE) + 1)
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#define PRD_BUF_SIZE PRD_MAX_SEGS * 8
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static void *prdbuf = 0;
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static void *prdbuf_next = 0;
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/*
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* Hardware specific IDE controller code. All vendor-specific code
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* for handling IDE timing and other chipset peculiarities should be
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* encapsulated here.
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*/
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/* helper funcs */
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/*
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* nnn_mode() return the highest valid mode, or -1 if the mode class is
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* not supported
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*/
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static __inline int
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pio_mode(struct wdparams *wp)
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{
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if ((wp->wdp_atavalid & 2) == 2) {
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if ((wp->wdp_eidepiomodes & 2) == 2) return 4;
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if ((wp->wdp_eidepiomodes & 1) == 1) return 3;
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}
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return -1;
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}
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#if 0
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static __inline int
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dma_mode(struct wdparams *wp)
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{
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/* XXX not quite sure how to verify validity on this field */
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}
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#endif
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static __inline int
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mwdma_mode(struct wdparams *wp)
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{
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/*
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* XXX technically, using wdp_atavalid to test for validity of
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* this field is not quite correct
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*/
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if ((wp->wdp_atavalid & 2) == 2) {
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if ((wp->wdp_dmamword & 4) == 4) return 2;
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if ((wp->wdp_dmamword & 2) == 2) return 1;
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if ((wp->wdp_dmamword & 1) == 1) return 0;
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}
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return -1;
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}
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static __inline int
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udma_mode(struct wdparams *wp)
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{
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if ((wp->wdp_atavalid & 4) == 4) {
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if ((wp->wdp_udmamode & 4) == 4) return 2;
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if ((wp->wdp_udmamode & 2) == 2) return 1;
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if ((wp->wdp_udmamode & 1) == 1) return 0;
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}
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return -1;
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}
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/* Generic busmastering PCI-IDE */
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static int
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generic_dmainit(struct ide_pci_cookie *cookie,
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struct wdparams *wp,
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int(*wdcmd)(int, void *),
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void *wdinfo)
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{
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/*
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* punt on the whole timing issue by looking for either a
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* drive programmed for both PIO4 and mDMA2 (which use similar
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* timing) or a drive in an UltraDMA mode (hopefully all
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* controllers have separate timing for UDMA). one hopes that if
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* the drive's DMA mode has been configured by the BIOS, the
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* controller's has also.
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*
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* XXX there are examples where this approach is now known to be
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* broken, at least on systems based on Intel chipsets.
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*/
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if ((pio_mode(wp) >= 4 && mwdma_mode(wp) >= 2) ||
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(udma_mode(wp) >= 2)) {
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printf("ide_pci: generic_dmainit %04x:%d: warning, IDE controller timing not set\n",
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cookie->iobase_wd,
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cookie->unit);
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return 1;
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}
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#ifdef IDE_PCI_DEBUG
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printf("pio_mode: %d, mwdma_mode(wp): %d, udma_mode(wp): %d\n",
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pio_mode(wp), mwdma_mode(wp), udma_mode(wp));
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#endif
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return 0;
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}
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static void
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generic_status(struct ide_pci_cookie *cookie)
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{
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printf("generic_status: no PCI IDE timing info available\n");
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}
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static struct vendor_fns vs_generic =
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{
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generic_dmainit,
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generic_status
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};
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/* VIA Technologies "82C571" PCI-IDE controller core */
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static void
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via_571_status(struct ide_pci_cookie *cookie)
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{
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int iobase_wd;
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int ctlr, unit;
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int iobase_bm;
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pcici_t tag;
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pcidi_t type;
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u_long word40[5];
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int i, unitno;
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iobase_wd = cookie->iobase_wd;
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unit = cookie->unit;
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ctlr = cookie->ctlr;
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iobase_bm = cookie->iobase_bm;
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tag = cookie->tag;
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type = cookie->type;
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unitno = ctlr * 2 + unit;
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for (i=0; i<5; i++) {
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word40[i] = pci_conf_read(tag, i * 4 + 0x40);
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}
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if (ctlr == 0)
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printf("via_571_status: Primary IDE prefetch/postwrite %s/%s\n",
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word40[0] & 0x8000 ? "enabled" : "disabled",
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word40[0] & 0x4000 ? "enabled" : "disabled");
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else
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printf("via_571_status: Secondary IDE prefetch/postwrite %s/%s\n",
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word40[0] & 0x2000 ? "enabled" : "disabled",
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word40[0] & 0x1000 ? "enabled" : "disabled");
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printf("via_571_status: busmaster status read retry %s\n",
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(word40[1] & 0x08) ? "enabled" : "disabled");
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printf("via_571_status: %s drive %d data setup=%d active=%d recovery=%d\n",
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unitno < 2 ? "primary" : "secondary",
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unitno & 1,
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((u_int)(word40[3] >> ((3 - unitno) * 2)) & 3) + 1,
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((u_int)(word40[2] >> (((3 - unitno) * 8) + 4)) & 0x0f) + 1,
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((u_int)(word40[2] >> ((3 - unitno) * 8)) & 0x0f) + 1);
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if (ctlr == 0)
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printf("via_571_status: primary ctrl active=%d recovery=%d\n",
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((u_int)(word40[3] >> 28) & 0x0f) + 1,
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((u_int)(word40[2] >> 24) & 0x0f) + 1);
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else
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printf("via_571_status: secondary ctrl active=%d recovery=%d\n",
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((u_int)(word40[3] >> 20) & 0x0f) + 1,
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((u_int)(word40[2] >> 16) & 0x0f) + 1);
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/* UltraDMA dump */
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{
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int foo;
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foo = word40[4] >> ((3 - unitno) * 8);
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printf("via_571_status: %s drive %d udma method=%d enable=%d PIOmode=%d cycle=%d\n",
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i < 2 ? "primary" : "secondary",
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i & 1,
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(foo >> 7) & 1,
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(foo >> 6) & 1,
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(foo >> 5) & 1,
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(foo & 3) + 2);
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}
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}
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/*
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* XXX timing values set here are only good for 30/33MHz buses; should deal
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* with slower ones too (BTW: you overclock-- you lose)
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*/
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static int
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via_571_dmainit(struct ide_pci_cookie *cookie,
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struct wdparams *wp,
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int(*wdcmd)(int, void *),
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void *wdinfo)
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{
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int r;
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u_long pci_revision;
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int unitno;
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pci_revision = pci_conf_read(cookie->tag, PCI_CLASS_REG) &
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PCI_REVISION_MASK;
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unitno = cookie->ctlr * 2 + cookie->unit;
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/* If it's a UDMA drive on a '590, set it up */
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/*
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* XXX the revision number we check for is of dubious validity.
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* it's extracted from the AMD 645 datasheet.
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*/
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if (pci_revision >= 1 && udma_mode(wp) >= 2) {
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unsigned int word50, mask, new;
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word50 = pci_conf_read(cookie->tag, 0x50);
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/* UDMA enable by SET FEATURES, DMA cycles, cycle time 2T */
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mask = 0xe3000000 >> (unitno * 8);
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new = 0x80000000 >> (unitno * 8);
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word50 &= ~mask;
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word50 |= new;
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pci_conf_write(cookie->tag, 0x50, word50);
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/*
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* With the '590, drive configuration should come *after* the
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* controller configuration, to make sure the controller sees
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* the SET FEATURES command and does the right thing.
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*/
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/* Set UDMA mode 2 on drive */
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if (bootverbose)
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printf("intel_piix_dmainit: setting ultra DMA mode 2\n");
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r = wdcmd(WDDMA_UDMA2, wdinfo);
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if (!r) {
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printf("intel_piix_dmainit: setting DMA mode failed\n");
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return 0;
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}
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if (bootverbose)
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via_571_status(cookie);
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return 1;
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}
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/* otherwise, try and program it for MW DMA mode 2 */
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else if (mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4) {
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u_long workword;
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/* Set multiword DMA mode 2 on drive */
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if (bootverbose)
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printf("intel_piix_dmainit: setting multiword DMA mode 2\n");
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r = wdcmd(WDDMA_MDMA2, wdinfo);
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if (!r) {
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printf("intel_piix_dmainit: setting DMA mode failed\n");
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return 0;
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}
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/* Configure the controller appropriately for MWDMA mode 2 */
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workword = pci_conf_read(cookie->tag, 0x40);
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/*
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* enable prefetch/postwrite-- XXX may cause problems
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* with CD-ROMs?
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*/
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workword &= ~(3 << (cookie->ctlr * 2 + 12));
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workword |= 3 << (cookie->ctlr * 2 + 12);
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/* FIFO configurations-- equal split, threshold 1/2 */
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workword &= 0x90ffffff;
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workword |= 0x2a000000;
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pci_conf_write(cookie->tag, 0x40, workword);
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workword = pci_conf_read(cookie->tag, 0x44);
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/* enable status read retry */
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workword |= 8;
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/* enable FIFO flush on interrupt and end of sector */
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workword &= 0xff0cffff;
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workword |= 0x00f00000;
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pci_conf_write(cookie->tag, 0x44, workword);
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workword = pci_conf_read(cookie->tag, 0x48);
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/* set Mode2 timing */
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workword &= ~(0xff000000 >> (unitno * 8));
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workword |= 0x31000000 >> (unitno * 8);
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pci_conf_write(cookie->tag, 0x48, workword);
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/* set sector size */
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pci_conf_write(cookie->tag, cookie->ctlr ? 0x68 : 0x60, 0x200);
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if (bootverbose)
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via_571_status(cookie);
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return 1;
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}
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return 0;
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}
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|
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static struct vendor_fns vs_via_571 =
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{
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via_571_dmainit,
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via_571_status
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};
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|
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static void
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promise_status(struct ide_pci_cookie *cookie)
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{
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pcici_t tag;
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int i;
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u_int32_t port0_command, port0_altstatus;
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u_int32_t port1_command, port1_altstatus;
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u_int32_t dma_block;
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|
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u_int32_t lat_and_interrupt;
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u_int32_t drivetiming;
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int pa, pb, mb, mc;
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tag = cookie->tag;
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port0_command = pci_conf_read(tag, 0x10);
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port0_altstatus = pci_conf_read(tag, 0x14);
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port1_command = pci_conf_read(tag, 0x18);
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port1_altstatus = pci_conf_read(tag, 0x1c);
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dma_block = pci_conf_read(tag, 0x20);
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lat_and_interrupt = pci_conf_read(tag, 0x3c);
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|
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printf("promise_status: port0: 0x%lx, port0_alt: 0x%lx, port1: 0x%lx, port1_alt: 0x%lx\n",
|
|
(u_long)port0_command, (u_long)port0_altstatus, (u_long)port1_command,
|
|
(u_long)port1_altstatus);
|
|
printf(
|
|
"promise_status: dma control blk address: 0x%lx, int: %d, irq: %d\n",
|
|
(u_long)dma_block, (u_int)(lat_and_interrupt >> 8) & 0xff,
|
|
(u_int)lat_and_interrupt & 0xff);
|
|
|
|
for(i=0;i<4;i+=2) {
|
|
drivetiming = pci_conf_read(tag, 0x60 + i * 4);
|
|
printf("drivebits%d-%d: %b\n", i, i+1, drivetiming,
|
|
"\020\05Prefetch\06Iordy\07Errdy\010Sync\025DmaW\026DmaR");
|
|
pa = drivetiming & 0xf;
|
|
pb = (drivetiming >> 8) & 0x1f;
|
|
mb = (drivetiming >> 13) & 0x7;
|
|
mc = (drivetiming >> 16) & 0xf;
|
|
printf("drivetiming%d: pa: 0x%x, pb: 0x%x, mb: 0x%x, mc: 0x%x\n",
|
|
i, pa, pb, mb, mc);
|
|
|
|
drivetiming = pci_conf_read(tag, 0x60 + (i + 1) * 4);
|
|
pa = drivetiming & 0xf;
|
|
pb = (drivetiming >> 8) & 0x1f;
|
|
mb = (drivetiming >> 13) & 0x7;
|
|
mc = (drivetiming >> 16) & 0xf;
|
|
printf("drivetiming%d: pa: 0x%x, pb: 0x%x, mb: 0x%x, mc: 0x%x\n",
|
|
i + 1, pa, pb, mb, mc);
|
|
}
|
|
}
|
|
|
|
static struct vendor_fns vs_promise =
|
|
{
|
|
generic_dmainit,
|
|
promise_status
|
|
};
|
|
|
|
/* Intel PIIX, PIIX3, and PIIX4 IDE controller subfunctions */
|
|
static void
|
|
intel_piix_dump_drive(char *ctlr,
|
|
int sitre,
|
|
int is_piix4,
|
|
int word40,
|
|
int word44,
|
|
int word48,
|
|
int word4a,
|
|
int drive)
|
|
{
|
|
char *ms;
|
|
|
|
if (!sitre)
|
|
ms = "master/slave";
|
|
else if (drive == 0)
|
|
ms = "master";
|
|
else
|
|
ms = "slave";
|
|
|
|
printf("intel_piix_status: %s %s sample = %d, %s recovery = %d\n",
|
|
ctlr,
|
|
ms,
|
|
5 - ((sitre && drive) ?
|
|
((word44 >> 2) & 3) :
|
|
((word40 >> 12) & 3)),
|
|
ms,
|
|
4 - ((sitre && drive) ?
|
|
((word44 >> 0) & 3) :
|
|
((word40 >> 8) & 3)));
|
|
|
|
word40 >>= (drive * 4);
|
|
printf("intel_piix_status: %s %s fastDMAonly %s, pre/post %s,\n\
|
|
intel_piix_status: IORDY sampling %s,\n\
|
|
intel_piix_status: fast PIO %s%s\n",
|
|
ctlr,
|
|
(drive == 0) ? "master" : "slave",
|
|
(word40 & 8) ? "enabled" : "disabled",
|
|
(word40 & 4) ? "enabled" : "disabled",
|
|
(word40 & 2) ? "enabled" : "disabled",
|
|
(word40 & 1) ? "enabled" : "disabled",
|
|
((word40 & 9) == 9) ? " (overridden by fastDMAonly)" : "" );
|
|
|
|
if (is_piix4)
|
|
printf("intel_piix_status: UltraDMA %s, CT/RP = %d/%d\n",
|
|
word48 ? "enabled": "disabled",
|
|
4 - (word4a & 3),
|
|
6 - (word4a & 3));
|
|
}
|
|
|
|
static void
|
|
intel_piix_status(struct ide_pci_cookie *cookie)
|
|
{
|
|
int iobase_wd;
|
|
int unit;
|
|
int iobase_bm;
|
|
pcici_t tag;
|
|
pcidi_t type;
|
|
int ctlr;
|
|
u_long word40, word44, word48;
|
|
int sitre, is_piix4;
|
|
|
|
iobase_wd = cookie->iobase_wd;
|
|
unit = cookie->unit;
|
|
iobase_bm = cookie->iobase_bm;
|
|
tag = cookie->tag;
|
|
type = cookie->type;
|
|
ctlr = cookie->ctlr;
|
|
|
|
word40 = pci_conf_read(tag, 0x40);
|
|
word44 = pci_conf_read(tag, 0x44);
|
|
word48 = pci_conf_read(tag, 0x48);
|
|
|
|
/*
|
|
* XXX will not be right for the *next* generation of upward-compatible
|
|
* intel IDE controllers...
|
|
*/
|
|
is_piix4 = pci_conf_read(tag, PCI_CLASS_REG) == 0x71118086;
|
|
|
|
sitre = word40 & 0x4000;
|
|
|
|
switch (ctlr * 2 + unit) {
|
|
case 0:
|
|
intel_piix_dump_drive("primary",
|
|
sitre,
|
|
is_piix4,
|
|
word40 & 0xffff,
|
|
word44 & 0x0f,
|
|
word48,
|
|
word48 >> 16,
|
|
0);
|
|
break;
|
|
case 1:
|
|
intel_piix_dump_drive("primary",
|
|
sitre,
|
|
is_piix4,
|
|
word40 & 0xffff,
|
|
word44 & 0x0f,
|
|
word48 >> 1,
|
|
word48 >> 20,
|
|
1);
|
|
break;
|
|
case 2:
|
|
intel_piix_dump_drive("secondary",
|
|
sitre,
|
|
is_piix4,
|
|
(word40 >> 16) & 0xffff,
|
|
(word44 >> 4) & 0x0f,
|
|
word48 >> 2,
|
|
word48 >> 24,
|
|
0);
|
|
break;
|
|
case 3:
|
|
intel_piix_dump_drive("secondary",
|
|
sitre,
|
|
is_piix4,
|
|
(word40 >> 16) & 0xffff,
|
|
(word44 >> 4) & 0x0f,
|
|
word48 >> 3,
|
|
word48 >> 28,
|
|
1);
|
|
break;
|
|
default:
|
|
printf("intel_piix_status: bad drive or controller number\n");
|
|
}
|
|
}
|
|
|
|
/*
|
|
* XXX timing values set hereare only good for 30/33MHz buses; should deal
|
|
* with slower ones too (BTW: you overclock-- you lose)
|
|
*/
|
|
|
|
static int
|
|
intel_piix_dmainit(struct ide_pci_cookie *cookie,
|
|
struct wdparams *wp,
|
|
int(*wdcmd)(int, void *),
|
|
void *wdinfo)
|
|
{
|
|
int r;
|
|
|
|
/* If it's a UDMA drive and a PIIX4, set it up */
|
|
if (cookie->type == 0x71118086 && udma_mode(wp) >= 2) {
|
|
/* Set UDMA mode 2 on controller */
|
|
int unitno, mask, new;
|
|
|
|
if (bootverbose)
|
|
printf("intel_piix_dmainit: setting ultra DMA mode 2\n");
|
|
|
|
r = wdcmd(WDDMA_UDMA2, wdinfo);
|
|
|
|
if (!r) {
|
|
printf("intel_piix_dmainit: setting DMA mode failed\n");
|
|
return 0;
|
|
}
|
|
|
|
unitno = cookie->ctlr * 2 + cookie->unit;
|
|
|
|
mask = (1 << unitno) + (3 << (16 + unitno * 4));
|
|
new = (1 << unitno) + (2 << (16 + unitno * 4));
|
|
|
|
pci_conf_write(cookie->tag, 0x48,
|
|
(pci_conf_read(cookie->tag, 0x48) & ~mask) | new);
|
|
|
|
if (bootverbose)
|
|
intel_piix_status(cookie);
|
|
return 1;
|
|
}
|
|
/*
|
|
* if it's an 82371FB, which can't do independent programming of
|
|
* drive timing, we punt; we're not going to fuss with trying to
|
|
* coordinate timing modes between drives. if this is you, get a
|
|
* new motherboard. or contribute patches :)
|
|
*
|
|
* we do now at least see if the modes set are OK to use. this should
|
|
* satisfy the majority of people, with mwdma mode2 drives.
|
|
*/
|
|
else if (cookie->type == 0x12308086)
|
|
{
|
|
u_long word40;
|
|
|
|
/* can drive do PIO 4 and MW DMA 2? */
|
|
if (!(mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4))
|
|
return 0;
|
|
|
|
word40 = pci_conf_read(cookie->tag, 0x40);
|
|
word40 >>= cookie->ctlr * 16;
|
|
|
|
/* Check for timing config usable for DMA on controller */
|
|
if (!((word40 & 0x3300) == 0x2300 &&
|
|
((word40 >> (cookie->unit * 4)) & 1) == 1))
|
|
return 0;
|
|
|
|
/* Set multiword DMA mode 2 on drive */
|
|
if (bootverbose)
|
|
printf("intel_piix_dmainit: setting multiword DMA mode 2\n");
|
|
r = wdcmd(WDDMA_MDMA2, wdinfo);
|
|
if (!r) {
|
|
printf("intel_piix_dmainit: setting DMA mode failed\n");
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
/* otherwise, treat it as a PIIX3 and program it for MW DMA mode 2 */
|
|
else if (mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4) {
|
|
u_long mask40, mask44, new40, new44;
|
|
|
|
/*
|
|
* If SITRE is not set, set it and copy the
|
|
* appropriate bits into the secondary registers. Do
|
|
* both controllers at once.
|
|
*/
|
|
if (((pci_conf_read(cookie->tag, 0x40) >> (16 * cookie->ctlr))
|
|
& 0x4000) == 0) {
|
|
unsigned int word40, word44;
|
|
|
|
word40 = pci_conf_read(cookie->tag, 0x40);
|
|
|
|
/* copy bits to secondary register */
|
|
word44 = pci_conf_read(cookie->tag, 0x44);
|
|
/*
|
|
* I've got a Biostar motherboard with Award
|
|
* BIOS that sets SITRE and secondary timing
|
|
* on one controller but not the other.
|
|
* Bizarre.
|
|
*/
|
|
if ((word40 & 0x4000) == 0) {
|
|
word44 &= ~0xf;
|
|
word44 |= ((word40 & 0x3000) >> 10) |
|
|
((word40 & 0x0300) >> 8);
|
|
}
|
|
if ((word40 & 0x40000000) == 0) {
|
|
word44 &= ~0xf0;
|
|
word44 |= ((word40 & 0x30000000) >> 22) |
|
|
((word40 & 0x03000000) >> 20);
|
|
}
|
|
/* set SITRE */
|
|
word40 |= 0x40004000;
|
|
|
|
pci_conf_write(cookie->tag, 0x40, word40);
|
|
pci_conf_write(cookie->tag, 0x44, word44);
|
|
}
|
|
|
|
/* Set multiword DMA mode 2 on drive */
|
|
if (bootverbose)
|
|
printf("intel_piix_dmainit: setting multiword DMA mode 2\n");
|
|
|
|
r = wdcmd(WDDMA_MDMA2, wdinfo);
|
|
|
|
if (!r) {
|
|
printf("intel_piix_dmainit: setting DMA mode failed\n");
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* backward compatible hardware leaves us with such
|
|
* twisted masses of software (aka twiddle the
|
|
* extremely weird register layout on a PIIX3, setting
|
|
* PIO mode 4 and MWDMA mode 2)
|
|
*/
|
|
if (cookie->unit == 0) {
|
|
mask40 = 0x330f;
|
|
new40 = 0x2307;
|
|
mask44 = 0;
|
|
new44 = 0;
|
|
} else {
|
|
mask40 = 0x00f0;
|
|
new40 = 0x0070;
|
|
mask44 = 0x000f;
|
|
new44 = 0x000b;
|
|
}
|
|
|
|
if (cookie->ctlr) {
|
|
mask40 <<= 16;
|
|
new40 <<= 16;
|
|
mask44 <<= 4;
|
|
new44 <<= 4;
|
|
}
|
|
|
|
pci_conf_write(cookie->tag, 0x40,
|
|
(pci_conf_read(cookie->tag, 0x40) & ~mask40) | new40);
|
|
pci_conf_write(cookie->tag, 0x44,
|
|
(pci_conf_read(cookie->tag, 0x44) & ~mask44) | new44);
|
|
|
|
if (bootverbose)
|
|
intel_piix_status(cookie);
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static struct vendor_fns vs_intel_piix =
|
|
{
|
|
intel_piix_dmainit,
|
|
intel_piix_status
|
|
};
|
|
|
|
/* Generic SFF-8038i code-- all code below here, except for PCI probes,
|
|
* more or less conforms to the SFF-8038i spec as extended for PCI.
|
|
* There should be no code that goes beyond that feature set below.
|
|
*/
|
|
|
|
/* XXX mkcookie is overloaded with too many parameters */
|
|
|
|
static struct ide_pci_cookie *
|
|
mkcookie(int iobase_wd,
|
|
int ctlr,
|
|
int unit,
|
|
int iobase_bm,
|
|
pcici_t tag,
|
|
pcidi_t type,
|
|
struct vendor_fns *vp,
|
|
int altiobase_wd)
|
|
{
|
|
struct ide_pci_cookie *cp;
|
|
|
|
cp = malloc(sizeof *cp, M_DEVBUF, M_NOWAIT);
|
|
if (!cp) return 0;
|
|
|
|
cp->iobase_wd = iobase_wd;
|
|
cp->ctlr = ctlr;
|
|
cp->unit = unit;
|
|
cp->tag = tag;
|
|
cp->type = type;
|
|
cp->iobase_bm = iobase_bm;
|
|
cp->altiobase_wd = altiobase_wd;
|
|
bcopy(vp, &cp->vs, sizeof(struct vendor_fns));
|
|
|
|
if (!prdbuf) {
|
|
prdbuf = malloc(PRD_ALLOC_SIZE, M_DEVBUF, M_NOWAIT);
|
|
if (!prdbuf) {
|
|
FREE(cp, M_DEVBUF);
|
|
return 0;
|
|
}
|
|
if (((int)prdbuf >> PAGE_SHIFT) ^
|
|
(((int)prdbuf + PRD_ALLOC_SIZE - 1) >> PAGE_SHIFT)) {
|
|
printf("ide_pci: prdbuf straddles page boundary, no DMA\n");
|
|
FREE(cp, M_DEVBUF);
|
|
FREE(prdbuf, M_DEVBUF);
|
|
return 0;
|
|
}
|
|
|
|
prdbuf_next = prdbuf;
|
|
}
|
|
if (((char *)prdbuf_next + PRD_BUF_SIZE) >
|
|
((char *)prdbuf + PRD_ALLOC_SIZE)) {
|
|
printf("ide_pci: mkcookie %04x:%d: no more space for PRDs, no DMA\n",
|
|
iobase_wd, unit);
|
|
FREE(cp, M_DEVBUF);
|
|
return 0;
|
|
}
|
|
|
|
cp->prd = prdbuf_next;
|
|
(char *)prdbuf_next += PRD_BUF_SIZE;
|
|
|
|
LIST_INSERT_HEAD(&softc.cookies, cp, le);
|
|
return cp;
|
|
}
|
|
|
|
static const char *
|
|
ide_pci_probe(pcici_t tag, pcidi_t type)
|
|
{
|
|
u_long data;
|
|
|
|
data = pci_conf_read(tag, PCI_CLASS_REG);
|
|
|
|
if ((data & PCI_CLASS_MASK) == PCI_CLASS_MASS_STORAGE &&
|
|
((data & PCI_SUBCLASS_MASK) == 0x00010000 ||
|
|
((data & PCI_SUBCLASS_MASK) == 0x00040000))) {
|
|
if (type == 0x71118086)
|
|
return ("Intel PIIX4 Bus-master IDE controller");
|
|
if (type == 0x70108086)
|
|
return ("Intel PIIX3 Bus-master IDE controller");
|
|
if (type == 0x12308086)
|
|
return ("Intel PIIX Bus-master IDE controller");
|
|
if (type == PROMISE_ULTRA33)
|
|
return ("Promise Ultra/33 IDE controller");
|
|
if (type == 0x05711106)
|
|
return ("VIA 82C586x (Apollo) Bus-master IDE controller");
|
|
if (data & 0x8000)
|
|
return ("PCI IDE controller (busmaster capable)");
|
|
#ifndef CMD640
|
|
/*
|
|
* XXX the CMD640B hack should be better integrated, or
|
|
* something.
|
|
*/
|
|
else
|
|
return ("PCI IDE controller (not busmaster capable)");
|
|
#endif
|
|
};
|
|
return ((char*)0);
|
|
}
|
|
|
|
static void
|
|
ide_pci_attach(pcici_t tag, int unit)
|
|
{
|
|
u_long class = 0, cmd;
|
|
int bmista_1, bmista_2;
|
|
int iobase_wd_1, iobase_wd_2, iobase_bm_1, iobase_bm_2;
|
|
int altiobase_wd_1, altiobase_wd_2;
|
|
struct vendor_fns *vp;
|
|
pcidi_t type;
|
|
struct ide_pci_cookie *cookie;
|
|
int ctlridx;
|
|
|
|
ctlridx = unit * 2;
|
|
|
|
/* set up vendor-specific stuff */
|
|
type = pci_conf_read(tag, PCI_ID_REG);
|
|
|
|
if (type != PROMISE_ULTRA33) {
|
|
/* is it busmaster capable? bail if not */
|
|
class = pci_conf_read(tag, PCI_CLASS_REG);
|
|
if (!(class & 0x8000)) {
|
|
return;
|
|
}
|
|
|
|
/* is it enabled and is busmastering turned on? */
|
|
cmd = pci_conf_read(tag, PCI_COMMAND_STATUS_REG);
|
|
if ((cmd & 5) != 5) {
|
|
return;
|
|
}
|
|
}
|
|
|
|
switch (type) {
|
|
case 0x71118086:
|
|
case 0x70108086:
|
|
case 0x12308086:
|
|
/* Intel PIIX, PIIX3, PIIX4 */
|
|
vp = &vs_intel_piix;
|
|
break;
|
|
|
|
case 0x5711106:
|
|
/* VIA Apollo chipset family */
|
|
vp = &vs_via_571;
|
|
break;
|
|
|
|
case PROMISE_ULTRA33:
|
|
/* Promise controllers */
|
|
vp = &vs_promise;
|
|
break;
|
|
|
|
default:
|
|
/* everybody else */
|
|
vp = &vs_generic;
|
|
break;
|
|
}
|
|
|
|
if (type != PROMISE_ULTRA33) {
|
|
if ((class & 0x100) == 0) {
|
|
iobase_wd_1 = IO_WD1;
|
|
altiobase_wd_1 = iobase_wd_1 + wd_altsts;
|
|
} else {
|
|
iobase_wd_1 = pci_conf_read(tag, 0x10) & 0xfffc;
|
|
altiobase_wd_1 = pci_conf_read(tag, 0x14) & 0xfffc;
|
|
}
|
|
|
|
if ((class & 0x400) == 0) {
|
|
iobase_wd_2 = IO_WD2;
|
|
altiobase_wd_2 = iobase_wd_2 + wd_altsts;
|
|
} else {
|
|
iobase_wd_2 = pci_conf_read(tag, 0x18) & 0xfffc;
|
|
altiobase_wd_2 = pci_conf_read(tag, 0x1c) & 0xfffc;
|
|
}
|
|
} else {
|
|
iobase_wd_1 = pci_conf_read(tag, 0x10) & 0xfffc;
|
|
altiobase_wd_1 = pci_conf_read(tag, 0x14) & 0xfffc;
|
|
iobase_wd_2 = pci_conf_read(tag, 0x18) & 0xfffc;
|
|
altiobase_wd_2 = pci_conf_read(tag, 0x1c) & 0xfffc;
|
|
}
|
|
|
|
iobase_bm_1 = pci_conf_read(tag, 0x20) & 0xfffc;
|
|
iobase_bm_2 = iobase_bm_1 + SFF8038_CTLR_1;
|
|
if (iobase_bm_1 == 0) {
|
|
printf("ide_pci: BIOS has not configured busmaster I/O address,\n\
|
|
ide_pci: giving up\n");
|
|
return;
|
|
}
|
|
|
|
wddma[unit].wdd_candma = ide_pci_candma;
|
|
wddma[unit].wdd_dmainit = ide_pci_dmainit;
|
|
wddma[unit].wdd_dmaverify = ide_pci_dmaverify;
|
|
wddma[unit].wdd_dmaprep = ide_pci_dmasetup;
|
|
wddma[unit].wdd_dmastart = ide_pci_dmastart;
|
|
wddma[unit].wdd_dmadone = ide_pci_dmadone;
|
|
wddma[unit].wdd_dmastatus = ide_pci_status;
|
|
wddma[unit].wdd_iobase = ide_pci_iobase;
|
|
wddma[unit].wdd_altiobase = ide_pci_altiobase;
|
|
|
|
/*
|
|
* This code below is mighty bogus. The config entries for the
|
|
* isa_devtab_bio are plugged in before the standard ISA bios scan.
|
|
* This is our "hack" way to simulate a dynamic assignment of I/O
|
|
* addresses, from a PCI device to an ISA probe. Sorry :-).
|
|
*/
|
|
if (iobase_wd_1 != IO_WD1) {
|
|
struct isa_device *dvp, *dvp1, *dvup;
|
|
for( dvp = isa_devtab_bio;
|
|
dvp->id_id != 0;
|
|
dvp++) {
|
|
if ((dvp->id_driver == &wdcdriver) && (dvp->id_iobase == 0)) {
|
|
int biotabunit;
|
|
biotabunit = dvp->id_unit * 2;
|
|
dvp->id_iobase = iobase_wd_1;
|
|
dvp1 = dvp + 1;
|
|
dvp1->id_iobase = iobase_wd_2;
|
|
printf("ide_pci%d: adding drives to controller %d:",
|
|
unit, biotabunit);
|
|
for(dvup = isa_biotab_wdc;
|
|
dvup->id_id != 0;
|
|
dvup++) {
|
|
if (dvup->id_driver != &wdcdriver)
|
|
continue;
|
|
if (dvup->id_unit != biotabunit)
|
|
continue;
|
|
|
|
dvup->id_iobase = dvp->id_iobase;
|
|
printf(" %d", dvup->id_unit);
|
|
dvup++;
|
|
|
|
pci_map_int(tag, wdintr, (void *) dvp->id_unit, &bio_imask);
|
|
if (dvup->id_id == 0)
|
|
break;
|
|
|
|
if (dvup->id_unit == biotabunit + 1) {
|
|
dvup->id_iobase = dvp->id_iobase;
|
|
printf(" %d", dvup->id_unit);
|
|
dvup++;
|
|
if (dvup->id_id == 0) {
|
|
iobase_wd_2 = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (dvup->id_unit == biotabunit + 2) {
|
|
pci_map_int(tag, wdintr, (void *) ((int) dvp->id_unit + 1), &bio_imask);
|
|
dvup->id_iobase = dvp1->id_iobase;
|
|
printf(" %d", dvup->id_unit);
|
|
dvup++;
|
|
if (dvup->id_id == 0) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (dvup->id_unit == biotabunit + 3) {
|
|
pci_map_int(tag, wdintr, (void *) ((int) dvp->id_unit + 1), &bio_imask);
|
|
dvup->id_iobase = dvp1->id_iobase;
|
|
printf(" %d", dvup->id_unit);
|
|
}
|
|
|
|
break;
|
|
}
|
|
printf("\n");
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
bmista_1 = inb(iobase_bm_1 + BMISTA_PORT);
|
|
bmista_2 = inb(iobase_bm_2 + BMISTA_PORT);
|
|
|
|
if (!ide_pci_softc_cookies_initted) {
|
|
LIST_INIT(&softc.cookies);
|
|
ide_pci_softc_cookies_initted = 1;
|
|
}
|
|
|
|
if (iobase_wd_1 != 0) {
|
|
cookie = mkcookie(iobase_wd_1,
|
|
ctlridx,
|
|
0,
|
|
iobase_bm_1,
|
|
tag,
|
|
type,
|
|
vp,
|
|
altiobase_wd_1);
|
|
if (bootverbose)
|
|
vp->vendor_status(cookie);
|
|
cookie = mkcookie(iobase_wd_1,
|
|
ctlridx,
|
|
1,
|
|
iobase_bm_1,
|
|
tag,
|
|
type,
|
|
vp,
|
|
altiobase_wd_1);
|
|
if (bootverbose) {
|
|
vp->vendor_status(cookie);
|
|
|
|
printf("ide_pci: busmaster 0 status: %02x from port: %08x\n",
|
|
bmista_1, iobase_bm_1+BMISTA_PORT);
|
|
|
|
if (bmista_1 & BMISTA_DMA0CAP)
|
|
printf("ide_pci: ide0:0 has been configured for DMA by BIOS\n");
|
|
if (bmista_1 & BMISTA_DMA1CAP)
|
|
printf("ide_pci: ide0:1 has been configured for DMA by BIOS\n");
|
|
}
|
|
}
|
|
|
|
if (bmista_1 & BMISTA_SIMPLEX || bmista_2 & BMISTA_SIMPLEX) {
|
|
printf("ide_pci: controller is simplex, no DMA on secondary channel\n");
|
|
} else if (iobase_wd_2 != 0) {
|
|
cookie = mkcookie(iobase_wd_2,
|
|
ctlridx + 1,
|
|
0,
|
|
iobase_bm_2,
|
|
tag,
|
|
type,
|
|
vp,
|
|
altiobase_wd_2);
|
|
if (bootverbose)
|
|
vp->vendor_status(cookie);
|
|
cookie = mkcookie(iobase_wd_2,
|
|
ctlridx + 1,
|
|
1,
|
|
iobase_bm_2,
|
|
tag,
|
|
type,
|
|
vp,
|
|
altiobase_wd_2);
|
|
if (bootverbose) {
|
|
vp->vendor_status(cookie);
|
|
|
|
printf("ide_pci: busmaster 1 status: %02x from port: %08x\n",
|
|
bmista_2, iobase_bm_2+BMISTA_PORT);
|
|
|
|
if (bmista_2 & BMISTA_DMA0CAP)
|
|
printf("ide_pci: ide1:0 has been configured for DMA by BIOS\n");
|
|
if (bmista_2 & BMISTA_DMA1CAP)
|
|
printf("ide_pci: ide1:1 has been configured for DMA by BIOS\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
static u_long ide_pci_count;
|
|
|
|
static struct pci_device ide_pci_device = {
|
|
"ide_pci",
|
|
ide_pci_probe,
|
|
ide_pci_attach,
|
|
&ide_pci_count,
|
|
0
|
|
};
|
|
|
|
DATA_SET(pcidevice_set, ide_pci_device);
|
|
|
|
/*
|
|
* Return a cookie if we can do DMA on the specified (iobase_wd, unit).
|
|
*/
|
|
static void *
|
|
ide_pci_candma(int iobase_wd, int unit)
|
|
{
|
|
struct ide_pci_cookie *cp;
|
|
|
|
cp = softc.cookies.lh_first;
|
|
while(cp) {
|
|
if (cp->unit == unit &&
|
|
((iobase_wd == 0) || (cp->iobase_wd == iobase_wd)))
|
|
break;
|
|
cp = cp->le.le_next;
|
|
}
|
|
|
|
return cp;
|
|
}
|
|
|
|
/*
|
|
* Initialize controller and drive for DMA operation, including timing modes.
|
|
* Uses data passed from the wd driver and a callback function to initialize
|
|
* timing modes on the drive.
|
|
*/
|
|
static int
|
|
ide_pci_dmainit(void *cookie,
|
|
struct wdparams *wp,
|
|
int(*wdcmd)(int, void *),
|
|
void *wdinfo)
|
|
{
|
|
struct ide_pci_cookie *cp = cookie;
|
|
/*
|
|
* If the controller status indicates that DMA is configured already,
|
|
* we flounce happily away
|
|
*/
|
|
if (inb(cp->iobase_bm + BMISTA_PORT) &
|
|
((cp->unit == 0) ? BMISTA_DMA0CAP : BMISTA_DMA1CAP))
|
|
return 1;
|
|
|
|
/* We take a stab at it with device-dependent code */
|
|
return(cp->vs.vendor_dmainit(cp, wp, wdcmd, wdinfo));
|
|
}
|
|
|
|
/*
|
|
* Verify that controller can handle a dma request for cp. Should
|
|
* not affect any hardware or driver state.
|
|
*/
|
|
static int
|
|
ide_pci_dmaverify(void *xcp, char *vaddr, u_long count, int dir)
|
|
{
|
|
int badfu;
|
|
|
|
/*
|
|
* check for nonaligned or odd-length Stuff
|
|
*/
|
|
badfu = ((unsigned int)vaddr & 1) || (count & 1);
|
|
#ifdef DIAGNOSTIC
|
|
if (badfu) {
|
|
printf("ide_pci: dmaverify odd vaddr or length, ");
|
|
printf("vaddr = %p length = %08lx\n", (void *)vaddr, count);
|
|
}
|
|
#endif
|
|
return (!badfu);
|
|
}
|
|
|
|
/*
|
|
* Set up DMA for cp. It is the responsibility of the caller
|
|
* to ensure that the controller is idle before this routine
|
|
* is called.
|
|
*/
|
|
static int
|
|
ide_pci_dmasetup(void *xcp, char *vaddr, u_long vcount, int dir)
|
|
{
|
|
struct ide_pci_cookie *cp = xcp;
|
|
struct ide_pci_prd *prd;
|
|
int i;
|
|
u_long firstpage;
|
|
u_long prd_base, prd_count;
|
|
u_long nbase, ncount, nend;
|
|
int iobase_bm;
|
|
u_long count;
|
|
#ifdef DIAGNOSTIC
|
|
u_long checkcount;
|
|
#endif
|
|
|
|
prd = cp->prd;
|
|
|
|
count = vcount;
|
|
|
|
i = 0;
|
|
|
|
iobase_bm = cp->iobase_bm;
|
|
|
|
if (count == 0) {
|
|
printf("ide_pci: dmasetup 0-length transfer, ");
|
|
printf("vaddr = %p length = %08lx\n", (void *)vaddr, count);
|
|
return 1;
|
|
}
|
|
|
|
/* Generate first PRD entry, which may be non-aligned. */
|
|
|
|
firstpage = PAGE_SIZE - ((uintptr_t)vaddr & PAGE_MASK);
|
|
|
|
prd_base = vtophys(vaddr);
|
|
prd_count = MIN(count, firstpage);
|
|
|
|
vaddr += prd_count;
|
|
count -= prd_count;
|
|
|
|
/* Step through virtual pages, coalescing as needed. */
|
|
while (count) {
|
|
nbase = vtophys(vaddr);
|
|
ncount = MIN(count, PAGE_SIZE);
|
|
nend = nbase + ncount;
|
|
|
|
/*
|
|
* Coalesce if physically contiguous and not crossing
|
|
* 64k boundary.
|
|
*/
|
|
if ((prd_base + prd_count == nbase) &&
|
|
((((nend - 1) ^ prd_base) & ~0xffff) == 0)) {
|
|
prd_count += ncount;
|
|
} else {
|
|
prd[i].prd_base = prd_base;
|
|
prd[i].prd_count = (prd_count & 0xffff);
|
|
i++;
|
|
if (i >= PRD_MAX_SEGS) {
|
|
printf("wd82371: too many segments in PRD table\n");
|
|
return 1;
|
|
}
|
|
prd_base = nbase;
|
|
prd_count = ncount;
|
|
}
|
|
vaddr += ncount;
|
|
count -= ncount;
|
|
}
|
|
|
|
/* Write last PRD entry. */
|
|
prd[i].prd_base = prd_base;
|
|
prd[i].prd_count = (prd_count & 0xffff) | PRD_EOT_BIT;
|
|
|
|
#ifdef DIAGNOSTIC
|
|
/* sanity check the transfer for length and page-alignment, at least */
|
|
checkcount = 0;
|
|
for (i = 0;; i++) {
|
|
unsigned int modcount;
|
|
|
|
modcount = prd[i].prd_count & 0xffffe;
|
|
if (modcount == 0) modcount = 0x10000;
|
|
checkcount += modcount;
|
|
if (i != 0 && ((prd[i].prd_base & PAGE_MASK) != 0)) {
|
|
printf("ide_pci: dmasetup() diagnostic fails-- unaligned page\n");
|
|
return 1;
|
|
}
|
|
if (prd[i].prd_count & PRD_EOT_BIT)
|
|
break;
|
|
}
|
|
|
|
if (checkcount != vcount) {
|
|
printf("ide_pci: dmasetup() diagnostic fails-- bad length\n");
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
/* Set up PRD base register */
|
|
outl(iobase_bm + BMIDTP_PORT, vtophys(prd));
|
|
|
|
/* Set direction of transfer */
|
|
outb(iobase_bm + BMICOM_PORT, (dir == B_READ) ? BMICOM_READ_WRITE : 0);
|
|
|
|
/* Clear interrupt and error bits */
|
|
outb(iobase_bm + BMISTA_PORT,
|
|
(inb(iobase_bm + BMISTA_PORT)
|
|
| (BMISTA_INTERRUPT | BMISTA_DMA_ERROR)));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
ide_pci_dmastart(void *xcp)
|
|
{
|
|
struct ide_pci_cookie *cp = xcp;
|
|
int iobase_bm;
|
|
|
|
iobase_bm = cp->iobase_bm;
|
|
|
|
outb(iobase_bm + BMICOM_PORT,
|
|
inb(iobase_bm + BMICOM_PORT) | BMICOM_STOP_START);
|
|
|
|
}
|
|
|
|
static int
|
|
ide_pci_dmadone(void *xcp)
|
|
{
|
|
struct ide_pci_cookie *cp = xcp;
|
|
int iobase_bm, status;
|
|
|
|
status = ide_pci_status(xcp);
|
|
iobase_bm = cp->iobase_bm;
|
|
|
|
outb(iobase_bm + BMICOM_PORT,
|
|
inb(iobase_bm + BMICOM_PORT) & ~BMICOM_STOP_START);
|
|
|
|
return status;
|
|
}
|
|
|
|
static int
|
|
ide_pci_status(void *xcp)
|
|
{
|
|
struct ide_pci_cookie *cp = xcp;
|
|
int iobase_bm, status, bmista;
|
|
|
|
status = 0;
|
|
iobase_bm = cp->iobase_bm;
|
|
|
|
bmista = inb(iobase_bm + BMISTA_PORT);
|
|
|
|
if (bmista & BMISTA_INTERRUPT)
|
|
status |= WDDS_INTERRUPT;
|
|
if (bmista & BMISTA_DMA_ERROR)
|
|
status |= WDDS_ERROR;
|
|
if (bmista & BMISTA_DMA_ACTIVE)
|
|
status |= WDDS_ACTIVE;
|
|
|
|
return status;
|
|
}
|
|
|
|
static int
|
|
ide_pci_altiobase(void *xcp)
|
|
{
|
|
struct ide_pci_cookie *cp = xcp;
|
|
if (cp == 0) {
|
|
return 0;
|
|
} else {
|
|
return cp->altiobase_wd;
|
|
}
|
|
}
|
|
|
|
static int
|
|
ide_pci_iobase(void *xcp)
|
|
{
|
|
struct ide_pci_cookie *cp = xcp;
|
|
if (cp == 0) {
|
|
return 0;
|
|
} else {
|
|
return cp->iobase_wd;
|
|
}
|
|
}
|
|
|
|
#endif
|
|
#endif /* NPCI > 0 */
|