Pyun YongHyeon 1bf71544de Add minimal dealy while ste(4) is waiting for the end of active DMA ... cycle.		2009-12-22 19:00:18 +00:00
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if_ste.c	Add minimal dealy while ste(4) is waiting for the end of active DMA	2009-12-22 19:00:18 +00:00
if_stereg.h	Add bus_dma(9) and endianness support to ste(4).	2009-12-22 18:57:07 +00:00