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Memory Interface (CFI). The flash memory can be read and written to through /dev/cfi# and an ioctl() exists so processes can read the query information. The driver supports the AMD and Intel command set, though only the AMD command has been tested. Obtained from: Juniper Networks, Inc.
420 lines
9.7 KiB
C
420 lines
9.7 KiB
C
/*-
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* Copyright (c) 2007, Juniper Networks, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <dev/cfi/cfi_reg.h>
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#include <dev/cfi/cfi_var.h>
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extern struct cdevsw cfi_cdevsw;
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char cfi_driver_name[] = "cfi";
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devclass_t cfi_devclass;
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uint32_t
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cfi_read(struct cfi_softc *sc, u_int ofs)
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{
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uint32_t val;
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ofs &= ~(sc->sc_width - 1);
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switch (sc->sc_width) {
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case 1:
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val = bus_space_read_1(sc->sc_tag, sc->sc_handle, ofs);
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break;
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case 2:
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val = bus_space_read_2(sc->sc_tag, sc->sc_handle, ofs);
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break;
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case 4:
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val = bus_space_read_4(sc->sc_tag, sc->sc_handle, ofs);
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break;
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default:
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val = ~0;
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break;
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}
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return (val);
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}
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static void
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cfi_write(struct cfi_softc *sc, u_int ofs, u_int val)
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{
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ofs &= ~(sc->sc_width - 1);
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switch (sc->sc_width) {
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case 1:
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bus_space_write_1(sc->sc_tag, sc->sc_handle, ofs, val);
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break;
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case 2:
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bus_space_write_2(sc->sc_tag, sc->sc_handle, ofs, val);
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break;
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case 4:
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bus_space_write_4(sc->sc_tag, sc->sc_handle, ofs, val);
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break;
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}
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}
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uint8_t
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cfi_read_qry(struct cfi_softc *sc, u_int ofs)
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{
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uint8_t val;
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cfi_write(sc, CFI_QRY_CMD_ADDR * sc->sc_width, CFI_QRY_CMD_DATA);
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val = cfi_read(sc, ofs * sc->sc_width);
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cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
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return (val);
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}
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static void
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cfi_amd_write(struct cfi_softc *sc, u_int ofs, u_int addr, u_int data)
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{
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cfi_write(sc, ofs + AMD_ADDR_START, CFI_AMD_UNLOCK);
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cfi_write(sc, ofs + AMD_ADDR_ACK, CFI_AMD_UNLOCK_ACK);
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cfi_write(sc, ofs + addr, data);
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}
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static char *
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cfi_fmtsize(uint32_t sz)
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{
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static char buf[8];
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static const char *sfx[] = { "", "K", "M", "G" };
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int sfxidx;
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sfxidx = 0;
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while (sfxidx < 3 && sz > 1023) {
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sz /= 1024;
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sfxidx++;
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}
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sprintf(buf, "%u%sB", sz, sfx[sfxidx]);
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return (buf);
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}
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int
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cfi_probe(device_t dev)
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{
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char desc[80];
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struct cfi_softc *sc;
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char *vend_str;
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int error;
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uint16_t iface, vend;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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sc->sc_rid = 0;
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sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
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RF_ACTIVE);
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if (sc->sc_res == NULL)
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return (ENXIO);
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sc->sc_tag = rman_get_bustag(sc->sc_res);
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sc->sc_handle = rman_get_bushandle(sc->sc_res);
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sc->sc_width = 1;
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while (sc->sc_width <= 4) {
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if (cfi_read_qry(sc, CFI_QRY_IDENT) == 'Q')
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break;
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sc->sc_width <<= 1;
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}
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if (sc->sc_width > 4) {
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error = ENXIO;
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goto out;
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}
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/* We got a Q. Check if we also have the R and the Y. */
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if (cfi_read_qry(sc, CFI_QRY_IDENT + 1) != 'R' ||
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cfi_read_qry(sc, CFI_QRY_IDENT + 2) != 'Y') {
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error = ENXIO;
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goto out;
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}
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/* Get the vendor and command set. */
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vend = cfi_read_qry(sc, CFI_QRY_VEND) |
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(cfi_read_qry(sc, CFI_QRY_VEND + 1) << 8);
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sc->sc_cmdset = vend;
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switch (vend) {
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case CFI_VEND_AMD_ECS:
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case CFI_VEND_AMD_SCS:
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vend_str = "AMD/Fujitsu";
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break;
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case CFI_VEND_INTEL_ECS:
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vend_str = "Intel/Sharp";
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break;
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case CFI_VEND_INTEL_SCS:
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vend_str = "Intel";
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break;
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case CFI_VEND_MITSUBISHI_ECS:
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case CFI_VEND_MITSUBISHI_SCS:
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vend_str = "Mitsubishi";
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break;
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default:
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vend_str = "Unknown vendor";
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break;
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}
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/* Get the device size. */
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sc->sc_size = 1U << cfi_read_qry(sc, CFI_QRY_SIZE);
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/* Sanity-check the I/F */
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iface = cfi_read_qry(sc, CFI_QRY_IFACE) |
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(cfi_read_qry(sc, CFI_QRY_IFACE + 1) << 8);
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/*
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* Adding 1 to iface will give us a bit-wise "switch"
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* that allows us to test for the interface width by
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* testing a single bit.
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*/
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iface++;
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error = (iface & sc->sc_width) ? 0 : EINVAL;
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if (error)
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goto out;
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snprintf(desc, sizeof(desc), "%s - %s", vend_str,
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cfi_fmtsize(sc->sc_size));
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device_set_desc_copy(dev, desc);
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out:
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bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
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return (error);
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}
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int
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cfi_attach(device_t dev)
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{
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struct cfi_softc *sc;
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u_int blksz, blocks;
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u_int r, u;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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sc->sc_rid = 0;
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sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
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RF_ACTIVE);
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if (sc->sc_res == NULL)
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return (ENXIO);
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sc->sc_tag = rman_get_bustag(sc->sc_res);
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sc->sc_handle = rman_get_bushandle(sc->sc_res);
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/* Get time-out values for erase and write. */
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sc->sc_write_timeout = 1 << cfi_read_qry(sc, CFI_QRY_TTO_WRITE);
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sc->sc_erase_timeout = 1 << cfi_read_qry(sc, CFI_QRY_TTO_ERASE);
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sc->sc_write_timeout *= 1 << cfi_read_qry(sc, CFI_QRY_MTO_WRITE);
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sc->sc_erase_timeout *= 1 << cfi_read_qry(sc, CFI_QRY_MTO_ERASE);
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/* Get erase regions. */
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sc->sc_regions = cfi_read_qry(sc, CFI_QRY_NREGIONS);
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sc->sc_region = malloc(sc->sc_regions * sizeof(struct cfi_region),
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M_TEMP, M_WAITOK | M_ZERO);
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for (r = 0; r < sc->sc_regions; r++) {
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blocks = cfi_read_qry(sc, CFI_QRY_REGION(r)) |
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(cfi_read_qry(sc, CFI_QRY_REGION(r) + 1) << 8);
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sc->sc_region[r].r_blocks = blocks + 1;
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blksz = cfi_read_qry(sc, CFI_QRY_REGION(r) + 2) |
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(cfi_read_qry(sc, CFI_QRY_REGION(r) + 3) << 8);
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sc->sc_region[r].r_blksz = (blksz == 0) ? 128 :
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blksz * 256;
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}
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/* Reset the device to a default state. */
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cfi_write(sc, 0, CFI_BCS_CLEAR_STATUS);
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if (bootverbose) {
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device_printf(dev, "[");
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for (r = 0; r < sc->sc_regions; r++) {
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printf("%ux%s%s", sc->sc_region[r].r_blocks,
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cfi_fmtsize(sc->sc_region[r].r_blksz),
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(r == sc->sc_regions - 1) ? "]\n" : ",");
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}
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}
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u = device_get_unit(dev);
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sc->sc_nod = make_dev(&cfi_cdevsw, u, UID_ROOT, GID_WHEEL, 0600,
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"%s%u", cfi_driver_name, u);
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sc->sc_nod->si_drv1 = sc;
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return (0);
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}
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int
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cfi_detach(device_t dev)
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{
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struct cfi_softc *sc;
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sc = device_get_softc(dev);
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destroy_dev(sc->sc_nod);
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free(sc->sc_region, M_TEMP);
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bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
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return (0);
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}
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static int
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cfi_wait_ready(struct cfi_softc *sc, u_int timeout)
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{
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int done, error;
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uint32_t st0, st;
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done = 0;
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error = 0;
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timeout *= 10;
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while (!done && !error && timeout) {
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DELAY(100);
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timeout--;
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switch (sc->sc_cmdset) {
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case CFI_VEND_INTEL_ECS:
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case CFI_VEND_INTEL_SCS:
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st = cfi_read(sc, sc->sc_wrofs);
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done = (st & 0x80);
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if (done) {
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if (st & 0x02)
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error = EPERM;
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else if (st & 0x10)
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error = EIO;
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else if (st & 0x20)
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error = ENXIO;
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}
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break;
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case CFI_VEND_AMD_SCS:
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case CFI_VEND_AMD_ECS:
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st0 = cfi_read(sc, sc->sc_wrofs);
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st = cfi_read(sc, sc->sc_wrofs);
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done = ((st & 0x40) == (st0 & 0x40)) ? 1 : 0;
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break;
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}
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}
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if (!done && !error)
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error = ETIMEDOUT;
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if (error)
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printf("\nerror=%d\n", error);
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return (error);
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}
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int
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cfi_write_block(struct cfi_softc *sc)
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{
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union {
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uint8_t *x8;
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uint16_t *x16;
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uint32_t *x32;
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} ptr;
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register_t intr;
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int error, i;
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/* Erase the block. */
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switch (sc->sc_cmdset) {
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case CFI_VEND_INTEL_ECS:
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case CFI_VEND_INTEL_SCS:
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cfi_write(sc, sc->sc_wrofs, CFI_BCS_BLOCK_ERASE);
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cfi_write(sc, sc->sc_wrofs, CFI_BCS_CONFIRM);
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break;
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case CFI_VEND_AMD_SCS:
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case CFI_VEND_AMD_ECS:
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cfi_amd_write(sc, sc->sc_wrofs, AMD_ADDR_START,
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CFI_AMD_ERASE_SECTOR);
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cfi_amd_write(sc, sc->sc_wrofs, 0, CFI_AMD_BLOCK_ERASE);
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break;
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default:
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/* Better safe than sorry... */
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return (ENODEV);
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}
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error = cfi_wait_ready(sc, sc->sc_erase_timeout);
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if (error)
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goto out;
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/* Write the block. */
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ptr.x8 = sc->sc_wrbuf;
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for (i = 0; i < sc->sc_wrbufsz; i += sc->sc_width) {
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/*
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* Make sure the command to start a write and the
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* actual write happens back-to-back without any
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* excessive delays.
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*/
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intr = intr_disable();
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switch (sc->sc_cmdset) {
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case CFI_VEND_INTEL_ECS:
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case CFI_VEND_INTEL_SCS:
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cfi_write(sc, sc->sc_wrofs + i, CFI_BCS_PROGRAM);
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break;
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case CFI_VEND_AMD_SCS:
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case CFI_VEND_AMD_ECS:
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cfi_amd_write(sc, 0, AMD_ADDR_START, CFI_AMD_PROGRAM);
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break;
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}
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switch (sc->sc_width) {
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case 1:
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bus_space_write_1(sc->sc_tag, sc->sc_handle,
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sc->sc_wrofs + i, *(ptr.x8)++);
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break;
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case 2:
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bus_space_write_2(sc->sc_tag, sc->sc_handle,
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sc->sc_wrofs + i, *(ptr.x16)++);
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break;
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case 4:
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bus_space_write_4(sc->sc_tag, sc->sc_handle,
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sc->sc_wrofs + i, *(ptr.x32)++);
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break;
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}
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intr_restore(intr);
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error = cfi_wait_ready(sc, sc->sc_write_timeout);
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if (error)
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goto out;
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}
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/* error is 0. */
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out:
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cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
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return (error);
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}
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