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mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
147 lines
4.5 KiB
C
147 lines
4.5 KiB
C
/*-
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* Copyright (c) 1987, 1991 Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)endian.h 7.8 (Berkeley) 4/3/91
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ENDIAN_H_
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#define _MACHINE_ENDIAN_H_
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#include <sys/cdefs.h>
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#ifndef __ASSEMBLER__
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#include <sys/_types.h>
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Definitions for byte order, according to byte significance from low
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* address to high.
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*/
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#define _LITTLE_ENDIAN 1234 /* LSB first: i386, vax */
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#define _BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */
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#define _PDP_ENDIAN 3412 /* LSB first in word, MSW first in long */
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#ifdef __MIPSEB__
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#define _BYTE_ORDER _BIG_ENDIAN
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#else
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#define _BYTE_ORDER _LITTLE_ENDIAN
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#endif /* __MIBSEB__ */
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/*
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* Deprecated variants that don't have enough underscores to be useful in more
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* strict namespaces.
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*/
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#if __BSD_VISIBLE
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#define LITTLE_ENDIAN _LITTLE_ENDIAN
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#define BIG_ENDIAN _BIG_ENDIAN
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#define PDP_ENDIAN _PDP_ENDIAN
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#define BYTE_ORDER _BYTE_ORDER
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#endif
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#ifndef __ASSEMBLER__
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#if defined(__GNUCLIKE_BUILTIN_CONSTANT_P) && defined(__OPTIMIZE__)
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#define __is_constant(x) __builtin_constant_p(x)
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#else
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#define __is_constant(x) 0
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#endif
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#define __bswap16_const(x) (((x) >> 8) | (((x) << 8) & 0xff00))
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#define __bswap32_const(x) (((x) >> 24) | (((x) >> 8) & 0xff00) | \
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(((x) << 8) & 0xff0000) | (((x) << 24) & 0xff000000))
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#define __bswap64_const(x) (((x) >> 56) | (((x) >> 40) & 0xff00) | \
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(((x) >> 24) & 0xff0000) | (((x) >> 8) & 0xff000000) | \
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(((x) << 8) & ((__uint64_t)0xff << 32)) | \
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(((x) << 24) & ((__uint64_t)0xff << 40)) | \
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(((x) << 40) & ((__uint64_t)0xff << 48)) | (((x) << 56)))
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static __inline __uint16_t
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__bswap16_var(__uint16_t _x)
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{
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return ((_x >> 8) | ((_x << 8) & 0xff00));
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}
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static __inline __uint32_t
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__bswap32_var(__uint32_t _x)
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{
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return ((_x >> 24) | ((_x >> 8) & 0xff00) | ((_x << 8) & 0xff0000) |
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((_x << 24) & 0xff000000));
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}
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static __inline __uint64_t
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__bswap64_var(__uint64_t _x)
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{
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return ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) |
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((_x >> 8) & 0xff000000) | ((_x << 8) & ((__uint64_t)0xff << 32)) |
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((_x << 24) & ((__uint64_t)0xff << 40)) |
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((_x << 40) & ((__uint64_t)0xff << 48)) | ((_x << 56)));
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}
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#define __bswap16(x) (__uint16_t)(__is_constant(x) ? __bswap16_const(x) : \
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__bswap16_var(x))
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#define __bswap32(x) (__uint32_t)(__is_constant(x) ? __bswap32_const(x) : \
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__bswap32_var(x))
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#define __bswap64(x) (__uint64_t)(__is_constant(x) ? __bswap64_const(x) : \
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__bswap64_var(x))
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#ifdef __MIPSEB__
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#define __htonl(x) ((__uint32_t)(x))
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#define __htons(x) ((__uint16_t)(x))
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#define __ntohl(x) ((__uint32_t)(x))
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#define __ntohs(x) ((__uint16_t)(x))
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/*
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* Define the order of 32-bit words in 64-bit words.
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*/
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/*
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* XXXMIPS: Additional parentheses to make gcc more happy.
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*/
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#define _QUAD_HIGHWORD 0
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#define _QUAD_LOWWORD 1
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#else
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#define _QUAD_HIGHWORD 1
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#define _QUAD_LOWWORD 0
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#define __ntohl(x) (__bswap32((x)))
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#define __ntohs(x) (__bswap16((x)))
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#define __htonl(x) (__bswap32((x)))
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#define __htons(x) (__bswap16((x)))
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#endif /* _MIPSEB */
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#endif /* _ASSEMBLER_ */
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#ifdef __cplusplus
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}
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#endif
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#endif /* !_MACHINE_ENDIAN_H_ */
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