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33cfde03bc
following changes have been done: - stylify. The original code was too hard to read. - get rid of a number of compilation options (Adaptec-only, Eni-only, no-DMA). - more debugging features. - locking. This is not correct yet in the absence of interface layer locking, but is correct enough to not to cause lock order reversals. - remove RAW mode. There are no users of this in the tree and I doubt that there are any. - remove NetBSD compatibility code. There was no way to keep NetBSD non-busdma and FreeBSD busdma code together. - if_en now buildable as a module. This has been actively tested on sparc64 and i386 with ENI server and client cards and an Adaptec card (thanks to kjc). Reviewed by: mdodd, arr
283 lines
10 KiB
C
283 lines
10 KiB
C
/* $NetBSD: midwayreg.h,v 1.6 1997/03/20 21:34:47 chuck Exp $ */
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/*
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* m i d w a y r e g . h
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*
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* this file contains the description of the ENI ATM midway chip
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* data structures. see midway.c for more details.
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*
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* $FreeBSD$
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*/
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#define MID_SZTOB(X) ((X) * 256 * 4) /* size to bytes */
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#define MID_BTOSZ(X) ((X) / 256 / 4) /* bytes to "size" */
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#define MID_N_VC 1024 /* # of VCs we can use */
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#define MID_VCI_BITS 10 /* number of bits */
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#define MID_NTX_CH 8 /* 8 transmit channels (shared) */
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#define MID_ATMDATASZ 48 /* need data in 48 byte blocks */
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/*
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* card data structures, top down
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*
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* in order to have a portable driver, the netbsd guys will not let us
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* use structs. we have a bus_space_handle_t which is the en_base address.
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* everything else is an offset from that base. all card data must be
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* accessed with bus_space_read_4()/bus_space_write_4():
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*
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* rv = bus_space_read_4(sc->en_memt, sc->en_base, BYTE_OFFSET);
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* bus_space_write_4(sc->en_memt, sc->en_base, BYTE_OFFSET, VALUE);
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*
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* en_card: the whole card (prom + phy + midway + obmem)
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* obmem contains: vci tab + dma queues (rx & tx) + service list + bufs
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*/
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/* byte offsets from en_base of various items */
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#define MID_SUNIOFF 0x020000 /* SUNI offset */
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#define MID_PHYOFF 0x030000 /* PHY offset */
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#define MID_MIDOFF 0x040000 /* midway regs offset */
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#define MID_RAMOFF 0x200000 /* RAM offset */
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#define MID_DRQOFF 0x204000 /* DRQ offset */
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#define MID_DRQEND MID_DTQOFF /* DRQ end */
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#define MID_DTQOFF 0x205000 /* DTQ offset */
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#define MID_DTQEND MID_SLOFF /* DTQ end */
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#define MID_SLOFF 0x206000 /* service list */
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#define MID_SLEND MID_BUFOFF /* service list end */
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#define MID_BUFOFF 0x207000 /* buffer area */
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#define MID_PROBEOFF 0x21fffc /* start probe here */
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#define MID_PROBSIZE 0x020000 /* 128 KB */
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#define MID_MAXOFF 0x3ffffc /* max offset */
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/*
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* prom & phy: not defined here
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*/
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#define MID_ADPMACOFF 0xffc0 /* mac address offset (adaptec only) */
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#define MID_NSUNI 256 /* suni registers */
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/*
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* midway regs (byte offsets from en_base)
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*/
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#define MID_RESID 0x40000 /* write=reset reg, read=ID reg */
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#define MID_VER(X) (((X) & 0xf0000000) >> 28) /* midway version # */
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#define MID_MID(X) (((X) & 0x700) >> 8) /* motherboard ID */
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#define MID_IS_SABRE(X) ((X) & 0x80) /* sabre controller? */
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#define MID_IS_SUNI(X) ((X) & 0x40) /* SUNI? vs utopia */
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#define MID_IS_UPIPE(X) ((X) & 0x20) /* utopia pipeline? */
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#define MID_DID(X) ((X) & 0x1f) /* daughterboard ID */
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#define MID_INTACK 0x40004 /* interrupt ACK */
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#define MID_INTSTAT 0x40008 /* interrupt status */
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#define MID_INTENA 0x4000c /* interrupt enable */
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#define MID_TXCHAN(N) (1 << ((N) + 9)) /* ack/status/enable xmit channel bit*/
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#define MID_INT_TX 0x1fe00 /* mask for any xmit interrupt */
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#define MID_INT_DMA_OVR 0x00100 /* DMA overflow interrupt */
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#define MID_INT_IDENT 0x00080 /* ident match error interrupt */
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#define MID_INT_LERR 0x00040 /* LERR interrupt (sbus?) */
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#define MID_INT_DMA_ERR 0x00020 /* DMA error interrupt */
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#define MID_INT_DMA_RX 0x00010 /* DMA recv interrupt */
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#define MID_INT_DMA_TX 0x00008 /* DMA xmit interrupt */
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#define MID_INT_SERVICE 0x00004 /* service list interrupt */
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#define MID_INT_SUNI 0x00002 /* SUNI interrupt */
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#define MID_INT_STATS 0x00001 /* stats overflow interrupt */
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#define MID_INT_ANY 0x1ffff /* any interrupt? */
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#define MID_INTBITS "\20\21T7\20T6\17T5\16T4\15T3\14T2\13T1\12T0\11DMAOVR\10ID\7LERR\6DMAERR\5RXDMA\4TXDMA\3SERV\2SUNI\1STAT"
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#define MID_MAST_CSR 0x40010 /* master CSR */
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#define MID_IPL(X) (((X) & 0x1c0) >> 6) /* IPL */
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#define MID_SETIPL(I) ((I) << 6)
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#define MID_MCSR_TXLOCK 0x20 /* lock on xmit overflow mode */
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/* NOTE: next 5 bits: write 1 means enable, write 0 means no change */
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#define MID_MCSR_ENDMA 0x10 /* DMA enable */
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#define MID_MCSR_ENTX 0x08 /* TX enable */
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#define MID_MCSR_ENRX 0x04 /* RX enable */
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#define MID_MCSR_W1MS 0x02 /* wait 1 msec */
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#define MID_MCSR_W500US 0x01 /* wait 500 usec */
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#define MID_MCSRBITS "\20\6LCK\5DMAON\4TXON\3RXON\2W1MS\1W500US"
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#define MID_STAT 0x40014 /* stat register, clear on read */
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#define MID_VTRASH(X) (((X) >> 16) & 0xffff)
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/* # cells trashed due to VCI's mode */
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#define MID_OTRASH(X) ((X) & 0xffff) /* # cells trashed due to overflow */
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#define MID_SERV_WRITE 0x40018 /* 10 bit service write pointer (r/o) */
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#define MID_DMA_ADDR 0x4001c /* VA of DMA (r/o) */
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/* DMA queue pointers (bits 0 to 8) */
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#define MID_DMA_WRRX 0x40020 /* write ptr. for DMA recv queue */
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/* (for adaptor -> host xfers) */
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#define MID_DMA_RDRX 0x40024 /* read ptr for DMA recv queue (r/o) */
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/* (i.e. current adaptor->host xfer) */
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#define MID_DMA_WRTX 0x40028 /* write ptr for DMA xmit queue */
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/* (for host -> adaptor xfers) */
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#define MID_DMA_RDTX 0x4002c /* read ptr for DMA xmit queue (r/o) */
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/* (i.e. current host->adaptor xfer) */
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/* xmit channel regs (1 per channel, MID_NTX_CH max channels) */
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#define MIDX_PLACE(N) (0x40040+((N)*0x10)) /* xmit place */
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#define MIDX_MKPLACE(SZ,LOC) ( ((SZ) << 11) | (LOC) )
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#define MIDX_LOC(X) ((X) & 0x7ff) /* location in obmem */
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#define MIDX_SZ(X) ((X) >> 11) /* (size of block / 256) in int32_t's*/
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#define MIDX_BASE(X) \
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(((MIDX_LOC(X) << MIDV_LOCTOPSHFT) * sizeof(uint32_t)) + MID_RAMOFF)
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/* the following two regs are word offsets in the block */
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/* xmit read pointer (r/o) */
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#define MIDX_READPTR(N) (0x40044 + ((N) * 0x10))
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/* seg currently in DMA (r/o) */
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#define MIDX_DESCSTART(N) (0x40048 + ((N) * 0x10))
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/*
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* obmem items
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*/
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/*
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* vci table in obmem (offset from MID_VCTOFF)
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*/
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#define MID_VC(N) (MID_RAMOFF + ((N) * 0x10))
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#define MIDV_TRASH 0x00000000 /* ignore VC */
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#define MIDV_AAL5 0x80000000 /* do AAL5 on it */
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#define MIDV_NOAAL 0x40000000 /* do per-cell stuff on it */
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#define MIDV_MASK 0xc0000000 /* mode mask */
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#define MIDV_SETMODE(VC,M) (((VC) & ~(MIDV_MASK)) | (M)) /* new mode */
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#define MIDV_PTI 0x20000000 /* save PTI cells? */
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#define MIDV_LOCTOPSHFT 8 /* shift to get top 11 bits of 19 */
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#define MIDV_LOCSHIFT 18
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#define MIDV_LOCMASK 0x7ff
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#define MIDV_LOC(X) (((X) >> MIDV_LOCSHIFT) & MIDV_LOCMASK)
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/* 11 most sig bits of addr */
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#define MIDV_SZSHIFT 15
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#define MIDV_SZ(X) (((X) >> MIDV_SZSHIFT) & 7)
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/* size encoded the usual way */
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#define MIDV_INSERVICE 0x1 /* in service list */
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#define MID_DST_RP(N) (MID_VC(N)|0x4)
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#define MIDV_DSTART_SHIFT 16 /* shift */
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#define MIDV_DSTART(X) (((X) >> MIDV_DSTART_SHIFT) & 0x7fff)
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#define MIDV_READP_MASK 0x7fff /* valid bits, (shift = 0) */
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#define MID_WP_ST_CNT(N) (MID_VC(N)|0x8) /* write pointer/state/count */
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#define MIDV_WRITEP_MASK 0x7fff0000 /* mask for write ptr. */
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#define MIDV_WRITEP_SHIFT 16
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#define MIDV_ST_IDLE 0x0000
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#define MIDV_ST_TRASH 0xc000
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#define MIDV_ST_REASS 0x4000
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#define MIDV_CCOUNT 0x7ff /* cell count */
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#define MID_CRC(N) (MID_VC(N)|0xc) /* CRC */
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/*
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* dma recv q.
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*/
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#define MID_DMA_END (1 << 5) /* for both tx and rx */
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#define MID_DMA_CNT(X) (((X) >> 16) & 0xffff)
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#define MID_DMA_TXCHAN(X) (((X) >> 6) & 0x7)
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#define MID_DMA_RXVCI(X) (((X) >> 6) & 0x3ff)
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#define MID_DMA_TYPE(X) ((X) & 0xf)
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#define MID_DRQ_N 512 /* # of descriptors */
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/* convert byte offset to reg value */
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#define MID_DRQ_A2REG(N) (((N) - MID_DRQOFF) >> 3)
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/* and back */
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#define MID_DRQ_REG2A(N) (((N) << 3) + MID_DRQOFF)
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/* note: format of word 1 of RXQ is different beween ENI and ADP cards */
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#define MID_MK_RXQ_ENI(CNT, VC, END, TYPE) \
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(((CNT) << 16) | ((VC) << 6) | (END) | (TYPE))
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#define MID_MK_RXQ_ADP(CNT, VC, END, JK) \
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(((CNT) << 12) | ((VC) << 2) | ((END) >> 4) | (((JK) != 0) ? 1 : 0))
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/*
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* dma xmit q.
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*/
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#define MID_DTQ_N 512 /* # of descriptors */
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/* convert byte offset to reg value */
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#define MID_DTQ_A2REG(N) (((N) - MID_DTQOFF) >> 3)
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/* and back */
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#define MID_DTQ_REG2A(N) (((N) << 3) + MID_DTQOFF)
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/* note: format of word 1 of TXQ is different beween ENI and ADP cards */
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#define MID_MK_TXQ_ENI(CNT, CHN, END, TYPE) \
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(((CNT) << 16) | ((CHN) << 6) | (END) | (TYPE))
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#define MID_MK_TXQ_ADP(CNT, CHN, END, JK) \
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(((CNT) << 12) | ((CHN) << 2) | ((END) >> 4) | (((JK) != 0) ? 1 : 0))
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/*
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* dma types
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*/
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#define MIDDMA_JK 0x3 /* just kidding */
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#define MIDDMA_BYTE 0x1 /* byte */
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#define MIDDMA_2BYTE 0x2 /* 2 bytes */
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#define MIDDMA_WORD 0x0 /* word */
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#define MIDDMA_2WORD 0x7 /* 2 words */
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#define MIDDMA_4WORD 0x4 /* 4 words */
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#define MIDDMA_8WORD 0x5 /* 8 words */
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#define MIDDMA_16WORD 0x6 /* 16 words!!! */
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#define MIDDMA_2WMAYBE 0xf /* 2 words, maybe */
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#define MIDDMA_4WMAYBE 0xc /* 4 words, maybe */
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#define MIDDMA_8WMAYBE 0xd /* 8 words, maybe */
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#define MIDDMA_16WMAYBE 0xe /* 16 words, maybe */
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#define MIDDMA_MAYBE 0xc /* mask to detect WMAYBE dma code */
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#define MIDDMA_MAXBURST (16 * sizeof(uint32_t)) /* largest burst */
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/*
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* service list
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*/
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#define MID_SL_N 1024 /* max # entries on slist */
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/* convert byte offset to reg value */
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#define MID_SL_A2REG(N) (((N) - MID_SLOFF) >> 2)
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/* and back */
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#define MID_SL_REG2A(N) (((N) << 2) + MID_SLOFF)
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/*
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* data in the buffer area of obmem
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*/
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/*
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* recv buffer desc. (1 uint32_t at start of buffer)
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*/
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#define MID_RBD_SIZE 4 /* RBD size */
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#define MID_CHDR_SIZE 4 /* on aal0, cell header size */
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#define MID_RBD_ID(X) ((X) & 0xfe000000) /* get ID */
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#define MID_RBD_STDID 0x36000000 /* standard ID */
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#define MID_RBD_CLP 0x01000000 /* CLP: cell loss priority */
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#define MID_RBD_CE 0x00010000 /* CE: congestion experienced */
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#define MID_RBD_T 0x00001000 /* T: trashed due to overflow */
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#define MID_RBD_CRCERR 0x00000800 /* CRC error */
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#define MID_RBD_CNT(X) ((X) & 0x7ff) /* cell count */
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/*
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* xmit buffer desc. (2 uint32_t's at start of buffer)
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* (note we treat the PR & RATE as a single uint8_t)
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*/
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#define MID_TBD_SIZE 8
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#define MID_TBD_MK1(AAL,PR_RATE,CNT) \
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(MID_TBD_STDID | (AAL) | ((PR_RATE) << 19) | (CNT))
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#define MID_TBD_STDID 0xb0000000 /* standard ID */
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#define MID_TBD_AAL5 0x08000000 /* AAL 5 */
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#define MID_TBD_NOAAL5 0x00000000 /* not AAL 5 */
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#define MID_TBD_MK2(VCI,PTI,CLP) \
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(((VCI) << 4) | ((PTI) << 1) | (CLP))
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/*
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* aal5 pdu tail, last 2 words of last cell of AAL5 frame
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* (word 2 is CRC .. handled by hw)
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*/
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#define MID_PDU_SIZE 8
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#define MID_PDU_MK1(UU, CPI, LEN) \
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(((UU) << 24) | ((CPI) << 16) | (LEN))
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#define MID_PDU_LEN(X) ((X) & 0xffff)
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