Marius Strobl 2611aba180 USIII and beyond CPUs have stricter requirements when it comes ... to synchronization needed after stores to internal ASIs in order to make side-effects visible. This mainly requires the MEMBAR #Sync after such stores to be replaced with a FLUSH. We use KERNBASE as the address to FLUSH as it is guaranteed to not trap. Actually, the USII synchronization rules also already require a FLUSH in pretty much all of the cases changed. We're also hitting an additional USIII synchronization rule which requires stores to AA_IMMU_SFSR to be immediately followed by a DONE, FLUSH or RETRY. Doing so triggers a RED state exception though so leave the MEMBAR #Sync. Linux apparently also has gotten away with doing the same for quite some time now, apart from the fact that it's not clear to me why we need to clear the valid bit from the SFSR in the first place. Reviewed by: nwhitehorn		2008-09-08 20:38:48 +00:00
..
boot1	Start each of the license/copyright comments with /*-	2005-01-05 22:16:58 +00:00
loader	USIII and beyond CPUs have stricter requirements when it comes	2008-09-08 20:38:48 +00:00
Makefile
Makefile.inc	Enable GCC stack protection (aka Propolice) for userland:	2008-06-25 21:33:28 +00:00