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af6646cdc5
but others say it's working. (DTR etc) Closes PR#884 Submitted-by: John Hay <jhay@mikom.csir.co.za>
1442 lines
33 KiB
C
1442 lines
33 KiB
C
/*
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* Copyright (c) 1995 John Hay. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by John Hay.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_ar.c,v 1.5 1996/02/06 18:50:32 wollman Exp $
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*/
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/*
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* Programming assumptions and other issues.
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*
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* The descriptors of a DMA channel will fit in a 16K memory window.
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*
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* The buffers of a transmit DMA channel will fit in a 16K memory window.
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*
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* Only the ISA bus and V.35 is tested.
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*
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* When interface is going up, handshaking is set and it is only cleared
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* when the interface is down'ed.
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*
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* There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
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* internal/external clock, etc.....
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*
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*/
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#include "ar.h"
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#include "bpfilter.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/mbuf.h>
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#include <sys/ioctl.h>
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#include <sys/socket.h>
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#include <sys/conf.h>
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#include <sys/errno.h>
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#include <sys/malloc.h>
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#include <sys/syslog.h>
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#include <net/if.h>
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#include <net/if_types.h>
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#include <net/if_sppp.h>
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#include <net/bpfdesc.h>
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#endif
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#include <sys/devconf.h>
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#include <machine/clock.h>
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#include <i386/isa/if_arregs.h>
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#include <i386/isa/ic/hd64570.h>
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#ifdef TRACE
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#define TRC(x) x
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#else
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#define TRC(x)
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#endif
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#define TRCL(x) x
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#define PPP_HEADER_LEN 4
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#define ARC_GET_WIN(addr) ((addr >> ARC_WIN_SHFT) & AR_WIN_MSK)
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#define ARC_SET_MEM(iobase,win) outb(iobase+AR_MSCA_EN, AR_ENA_MEM | \
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ARC_GET_WIN(win))
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#define ARC_SET_SCA(iobase,ch) outb(iobase+AR_MSCA_EN, AR_ENA_MEM | \
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AR_ENA_SCA | (ch ? AR_SEL_SCA_1:AR_SEL_SCA_0))
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#define ARC_SET_OFF(iobase) outb(iobase+AR_MSCA_EN, 0)
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static struct ar_hardc {
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int cunit;
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struct ar_softc *sc;
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u_short iobase;
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int startunit;
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int numports;
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caddr_t mem_start;
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caddr_t mem_end;
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u_int memsize; /* in bytes */
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u_char bustype; /* ISA, MCA, PCI.... */
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u_char interface; /* X21, V.35, EIA-530.... */
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u_char revision;
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u_char handshake; /* handshake lines supported by card. */
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u_char txc_dtr[NPORT/NCHAN]; /* the register is write only */
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u_int txc_dtr_off[NPORT/NCHAN];
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sca_regs *sca;
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struct kern_devconf kdc;
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}ar_hardc[NAR];
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struct ar_softc {
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struct sppp ifsppp;
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int unit; /* With regards to all ar devices */
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int subunit; /* With regards to this card */
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struct ar_hardc *hc;
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u_int txdesc; /* On card address */
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u_int txstart; /* On card address */
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u_int txend; /* On card address */
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u_int txtail; /* Index of first unused buffer */
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u_int txmax; /* number of usable buffers/descriptors */
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u_int rxdesc; /* On card address */
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u_int rxstart; /* On card address */
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u_int rxend; /* On card address */
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u_int rxhind; /* Index to the head of the rx buffers. */
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u_int rxmax; /* number of usable buffers/descriptors */
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int scano;
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int scachan;
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struct kern_devconf kdc;
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};
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static int arprobe(struct isa_device *id);
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static int arattach(struct isa_device *id);
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/*
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* This translate from irq numbers to
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* the value that the arnet card needs
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* in the lower part of the AR_INT_SEL
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* register.
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*/
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static int irqtable[16] = {
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0, /* 0 */
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0, /* 1 */
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0, /* 2 */
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1, /* 3 */
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0, /* 4 */
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2, /* 5 */
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0, /* 6 */
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3, /* 7 */
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0, /* 8 */
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0, /* 9 */
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4, /* 10 */
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5, /* 11 */
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6, /* 12 */
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0, /* 13 */
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0, /* 14 */
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7 /* 15 */
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};
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struct isa_driver ardriver = {arprobe, arattach, "arc"};
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static struct kern_devconf kdc_ar_template = {
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0, 0, 0,
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"ar", 0, { MDDT_ISA, 0, "net" },
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isa_generic_externalize, 0, 0, ISA_EXTERNALLEN,
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&kdc_isa0,
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0,
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DC_UNCONFIGURED,
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"Arnet SYNC/570i Port",
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DC_CLS_NETIF
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};
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static struct kern_devconf kdc_arc_template = {
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0, 0, 0,
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"arc", 0, { MDDT_ISA, 0, "net" },
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isa_generic_externalize, 0, 0, ISA_EXTERNALLEN,
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&kdc_isa0,
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0,
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DC_UNCONFIGURED,
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"Arnet SYNC/570i Adapter",
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DC_CLS_NETIF
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};
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static void arstart(struct ifnet *ifp);
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static int arioctl(struct ifnet *ifp, int cmd, caddr_t data);
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static void arwatchdog(struct ifnet *ifp);
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static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat);
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static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len);
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static void ar_eat_packet(struct ar_softc *sc);
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static void ar_get_packets(struct ar_softc *sc);
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static void ar_up(struct ar_softc *sc);
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static void ar_down(struct ar_softc *sc);
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static void arc_init(struct isa_device *id);
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static void ar_init_sca(struct ar_hardc *hc, int scano);
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static void ar_init_msci(struct ar_softc *sc);
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static void ar_init_rx_dmac(struct ar_softc *sc);
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static void ar_init_tx_dmac(struct ar_softc *sc);
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static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr);
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static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr);
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static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr);
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static inline void ar_registerdev(int ctlr, int unit)
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{
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struct ar_softc *sc;
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sc = &ar_hardc[ctlr].sc[unit];
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sc->kdc = kdc_ar_template;
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sc->kdc.kdc_unit = ar_hardc[ctlr].startunit + unit;
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sc->kdc.kdc_parentdata = &ar_hardc[ctlr].kdc;
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dev_attach(&sc->kdc);
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}
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static inline void arc_registerdev(struct isa_device *dvp)
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{
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int unit = dvp->id_unit;
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struct ar_hardc *hc = &ar_hardc[dvp->id_unit];
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hc->kdc = kdc_arc_template;
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hc->kdc.kdc_unit = unit;
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hc->kdc.kdc_parentdata = dvp;
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dev_attach(&hc->kdc);
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}
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/*
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* Register the Adapter.
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* Probe to see if it is there.
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* Get its information and fill it in.
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*/
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static int
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arprobe(struct isa_device *id)
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{
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struct ar_hardc *hc = &ar_hardc[id->id_unit];
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u_int tmp;
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u_short port;
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/*
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* Register the card.
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*/
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arc_registerdev(id);
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/*
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* Now see if the card is realy there.
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*
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* XXX For now I just check the undocumented ports
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* for "570". We will probably have to do more checking.
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*/
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port = id->id_iobase;
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if((inb(port+AR_ID_5) != '5') || (inb(port+AR_ID_7) != '7') ||
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(inb(port+AR_ID_0) != '0'))
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return 0;
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/*
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* We have a card here, fill in what we can.
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*/
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tmp = inb(port + AR_BMI);
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hc->bustype = tmp & AR_BUS_MSK;
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hc->memsize = (tmp & AR_MEM_MSK) >> AR_MEM_SHFT;
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hc->memsize = 1 << hc->memsize;
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hc->memsize <<= 16;
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hc->interface = (tmp & AR_IFACE_MSK);
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hc->revision = inb(port + AR_REV);
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hc->numports = inb(port + AR_PNUM);
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hc->handshake = inb(port + AR_HNDSH);
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id->id_msize = ARC_WIN_SIZ;
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hc->iobase = id->id_iobase;
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hc->mem_start = id->id_maddr;
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hc->mem_end = id->id_maddr + id->id_msize;
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hc->cunit = id->id_unit;
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switch(hc->interface) {
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case AR_IFACE_EIA_232:
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printf("ar%d: The EIA 232 interface is not supported.\n",
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id->id_unit);
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return 0;
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case AR_IFACE_V_35:
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break;
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case AR_IFACE_EIA_530:
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printf("ar%d: WARNING: The EIA 530 interface is untested.\n",
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id->id_unit);
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break;
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case AR_IFACE_X_21:
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break;
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case AR_IFACE_COMBO:
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printf("ar%d: WARNING: The COMBO interface is untested.\n",
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id->id_unit);
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break;
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}
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switch(hc->numports) {
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case 2:
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hc->kdc.kdc_description = "Arnet SYNC/570i 2 Port Adapter";
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break;
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case 4:
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hc->kdc.kdc_description = "Arnet SYNC/570i 4 Port Adapter";
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break;
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}
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if(id->id_unit == 0)
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hc->startunit = 0;
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else
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hc->startunit = ar_hardc[id->id_unit - 1].startunit +
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ar_hardc[id->id_unit - 1].numports;
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/*
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* Do a little sanity check.
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*/
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if((hc->numports > NPORT) || (hc->memsize > (512*1024)))
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return 0;
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return ARC_IO_SIZ; /* return the amount of IO addresses used. */
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}
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/*
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* Malloc memory for the softc structures.
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* Reset the card to put it in a known state.
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* Register the ports on the adapter.
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* Fill in the info for each port.
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* Attach each port to sppp and bpf.
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*/
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static int
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arattach(struct isa_device *id)
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{
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struct ar_hardc *hc = &ar_hardc[id->id_unit];
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struct ar_softc *sc;
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struct ifnet *ifp;
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int unit;
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char *iface;
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switch(hc->interface) {
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default: iface = "UNKNOWN"; break;
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case AR_IFACE_EIA_232: iface = "EIA-232"; break;
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case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break;
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case AR_IFACE_EIA_530: iface = "EIA-530"; break;
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case AR_IFACE_X_21: iface = "X.21"; break;
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case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break;
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}
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printf("arc%d: %uK RAM, %u ports, rev %u, "
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"%s interface.\n",
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id->id_unit,
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hc->memsize/1024,
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hc->numports,
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hc->revision,
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iface);
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hc->kdc.kdc_state = DC_BUSY;
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arc_init(id);
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sc = hc->sc;
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for(unit=0;unit<hc->numports;unit+=NCHAN)
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ar_init_sca(hc, unit / NCHAN);
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/*
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* Now configure each port on the card.
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*/
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for(unit=0;unit<hc->numports;sc++,unit++) {
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sc->hc = hc;
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sc->subunit = unit;
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sc->unit = hc->startunit + unit;
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sc->scano = unit / NCHAN;
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sc->scachan = unit%NCHAN;
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ar_registerdev(id->id_unit, unit);
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ar_init_rx_dmac(sc);
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ar_init_tx_dmac(sc);
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ar_init_msci(sc);
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ifp = &sc->ifsppp.pp_if;
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ifp->if_softc = sc;
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ifp->if_unit = hc->startunit + unit;
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ifp->if_name = "ar";
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ifp->if_mtu = PP_MTU;
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ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
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ifp->if_ioctl = arioctl;
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ifp->if_start = arstart;
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ifp->if_watchdog = arwatchdog;
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sc->ifsppp.pp_flags = PP_KEEPALIVE;
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sc->kdc.kdc_state = DC_IDLE;
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printf("ar%d: Adapter %d, port %d.\n",
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sc->unit,
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hc->cunit,
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sc->subunit);
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sppp_attach((struct ifnet *)&sc->ifsppp);
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if_attach(ifp);
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#if NBPFILTER > 0
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bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
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#endif
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}
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ARC_SET_OFF(hc->iobase);
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return 1;
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}
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/*
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* First figure out which SCA gave the interrupt.
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* Process it.
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* See if there is other interrupts pending.
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* Repeat until there is no more interrupts.
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*/
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void arintr(int unit)
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{
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struct ar_hardc *hc = &ar_hardc[unit];
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sca_regs *sca = hc->sca;
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u_char isr0, isr1, isr2, arisr;
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int scano;
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arisr = inb(hc->iobase + AR_ISTAT);
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while(arisr & AR_BD_INT) {
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if(arisr & AR_INT_0)
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scano = 0;
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else if(arisr & AR_INT_1)
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scano = 1;
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else {
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/* XXX Oops this shouldn't happen. */
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printf("arc%d: Interrupted with no interrupt.\n", unit);
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return;
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}
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ARC_SET_SCA(hc->iobase, scano);
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isr0 = sca->isr0;
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isr1 = sca->isr1;
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isr2 = sca->isr2;
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/*
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* Acknoledge all the interrupts pending.
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*/
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sca->isr0 = isr0;
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sca->isr1 = isr1;
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sca->isr2 = isr2;
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TRC(printf("ARINTR %d, isr0 %x, isr1 %x, isr2 %x\n", intno++,
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isr0,
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isr1,
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isr2));
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if(isr0)
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ar_msci_intr(hc, scano, isr0);
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if(isr1)
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ar_dmac_intr(hc, scano, isr1);
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if(isr2)
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ar_timer_intr(hc, scano, isr2);
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/*
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* Proccess the second sca's interrupt if available.
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* Else see if there are any new interrupts.
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*/
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if((arisr & AR_INT_0) && (arisr & AR_INT_1))
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arisr &= ~AR_INT_0;
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else
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arisr = inb(hc->iobase + AR_ISTAT);
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}
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ARC_SET_OFF(hc->iobase);
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}
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|
|
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/*
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|
* This function will be called from the upper level when a user add a
|
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* packet to be send, and from the interrupt handler after a finished
|
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* transmit.
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*
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* NOTE: it should run at spl_imp().
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|
*
|
|
* Transmitter idle state is indicated by the IFF_OACTIVE flag. The function
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|
* that clears that should ensure that the transmitter and it's DMA is
|
|
* in a "good" idle state.
|
|
*/
|
|
static void
|
|
arstart(struct ifnet *ifp)
|
|
{
|
|
struct ar_softc *sc = ifp->if_softc;
|
|
int i, len, tlen;
|
|
struct mbuf *mtx;
|
|
u_char *txdata;
|
|
sca_descriptor *txdesc;
|
|
static int intno = 0;
|
|
|
|
if(!(ifp->if_flags & IFF_RUNNING))
|
|
return;
|
|
|
|
mtx = sppp_dequeue(ifp);
|
|
if(!mtx)
|
|
return;
|
|
|
|
intno++;
|
|
|
|
/*
|
|
* It is OK to set the memory window outside the loop because
|
|
* all tx buffers and descriptors are assumed to be in the same
|
|
* 16K window.
|
|
*/
|
|
ARC_SET_MEM(sc->hc->iobase, sc->txdesc);
|
|
|
|
/*
|
|
* We stay in this loop until there is nothing in the
|
|
* TX queue left or the tx buffer is full.
|
|
*/
|
|
i = 0;
|
|
txdesc = (sca_descriptor *)
|
|
(sc->hc->mem_start + (sc->txdesc & ARC_WIN_MSK));
|
|
txdata = (u_char *)(sc->hc->mem_start + (sc->txstart & ARC_WIN_MSK));
|
|
for(;;) {
|
|
len = mtx->m_pkthdr.len;
|
|
|
|
TRC(printf("ar%d: ARstart %d, len %u\n", sc->unit, intno, len));
|
|
|
|
/*
|
|
* We can do this because the tx buffers don't wrap.
|
|
*/
|
|
m_copydata(mtx, 0, len, txdata);
|
|
tlen = len;
|
|
while(tlen > AR_BUF_SIZ) {
|
|
txdesc->stat = 0;
|
|
txdesc->len = AR_BUF_SIZ;
|
|
tlen -= AR_BUF_SIZ;
|
|
txdesc++;
|
|
txdata += AR_BUF_SIZ;
|
|
i++;
|
|
}
|
|
/* XXX Move into the loop? */
|
|
txdesc->stat = SCA_DESC_EOM;
|
|
txdesc->len = tlen;
|
|
txdesc++;
|
|
txdata += AR_BUF_SIZ;
|
|
i++;
|
|
|
|
#if NBPFILTER > 0
|
|
if(ifp->if_bpf)
|
|
bpf_mtap(ifp, mtx);
|
|
#endif
|
|
m_freem(mtx);
|
|
++sc->ifsppp.pp_if.if_opackets;
|
|
|
|
/*
|
|
* Check if we have space for another mbuf.
|
|
* XXX This is hardcoded. A packet won't be larger
|
|
* than 3 buffers (3 x 512).
|
|
*/
|
|
if((i + 3) >= sc->txmax)
|
|
break;
|
|
|
|
mtx = sppp_dequeue(ifp);
|
|
if(!mtx)
|
|
break;
|
|
}
|
|
|
|
sc->txtail = i;
|
|
|
|
/*
|
|
* Mark the last descriptor, so that the SCA know where
|
|
* to stop.
|
|
*/
|
|
txdesc--;
|
|
txdesc->stat |= SCA_DESC_EOT;
|
|
|
|
#if 0
|
|
printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp);
|
|
printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp);
|
|
printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb);
|
|
printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len);
|
|
printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat);
|
|
#endif
|
|
|
|
/*
|
|
* Start DMA.
|
|
* XXX For now we always start from the start.
|
|
*/
|
|
{
|
|
dmac_channel *dmac = &sc->hc->sca->dmac[DMAC_TXCH(sc->scachan)];
|
|
|
|
ARC_SET_SCA(sc->hc->iobase, sc->scano);
|
|
dmac->cda = (u_short)(sc->txdesc & 0xffff);
|
|
|
|
txdesc = (sca_descriptor *)sc->txdesc;
|
|
dmac->eda = (u_short)((u_int)&txdesc[i]);
|
|
dmac->dsr = SCA_DSR_DE;
|
|
}
|
|
|
|
ifp->if_flags |= IFF_OACTIVE;
|
|
ifp->if_timer = 2; /* Value in seconds. */
|
|
ARC_SET_OFF(sc->hc->iobase);
|
|
}
|
|
|
|
static int
|
|
arioctl(struct ifnet *ifp, int cmd, caddr_t data)
|
|
{
|
|
int s, error;
|
|
int was_up, should_be_up;
|
|
struct sppp *sp = (struct sppp *)ifp;
|
|
struct ar_softc *sc = ifp->if_softc;
|
|
|
|
TRC(printf("ar%d: arioctl.\n", ifp->if_unit);)
|
|
|
|
if(cmd == SIOCSIFFLAGS) {
|
|
if(ifp->if_flags & IFF_LINK2)
|
|
sp->pp_flags |= PP_CISCO;
|
|
else
|
|
sp->pp_flags &= ~PP_CISCO;
|
|
}
|
|
|
|
was_up = ifp->if_flags & IFF_RUNNING;
|
|
|
|
error = sppp_ioctl(ifp, cmd, data);
|
|
TRC(printf("ar%d: ioctl: ifsppp.pp_flags = %x, if_flags %x.\n",
|
|
ifp->if_unit, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);)
|
|
if(error)
|
|
return error;
|
|
|
|
if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR))
|
|
return 0;
|
|
|
|
TRC(printf("ar%d: arioctl %s.\n", ifp->if_unit,
|
|
(cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");)
|
|
|
|
s = splimp();
|
|
should_be_up = ifp->if_flags & IFF_RUNNING;
|
|
|
|
if(!was_up && should_be_up) {
|
|
/* Interface should be up -- start it. */
|
|
ar_up(sc);
|
|
arstart(ifp);
|
|
/* XXX Maybe clear the IFF_UP flag so that the link
|
|
* will only go up after sppp lcp and ipcp negotiation.
|
|
*/
|
|
} else if(was_up && !should_be_up) {
|
|
/* Interface should be down -- stop it. */
|
|
ar_down(sc);
|
|
sppp_flush(ifp);
|
|
}
|
|
splx(s);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* This is to catch lost tx interrupts.
|
|
*/
|
|
static void
|
|
arwatchdog(struct ifnet *ifp)
|
|
{
|
|
struct ar_softc *sc = ifp->if_softc;
|
|
|
|
if(!(ifp->if_flags & IFF_RUNNING))
|
|
return;
|
|
|
|
/* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */
|
|
printf("ar%d: transmit failed.\n", ifp->if_unit);
|
|
|
|
ARC_SET_SCA(sc->hc->iobase, sc->scano);
|
|
sc->hc->sca->msci[sc->scachan].cmd = SCA_CMD_TXABORT;
|
|
|
|
ar_down(sc);
|
|
ar_up(sc);
|
|
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
|
|
arstart(ifp);
|
|
}
|
|
|
|
static void ar_up(struct ar_softc *sc)
|
|
{
|
|
sca_regs *sca = sc->hc->sca;
|
|
msci_channel *msci = &sca->msci[sc->scachan];
|
|
|
|
TRC(printf("ar%d: sca %p, msci %p, ch %d\n",
|
|
sc->unit, sca, msci, sc->scachan));
|
|
sc->kdc.kdc_state = DC_BUSY;
|
|
|
|
/*
|
|
* Enable transmitter and receiver.
|
|
* Raise DTR and RTS.
|
|
* Enable interrupts.
|
|
*/
|
|
ARC_SET_SCA(sc->hc->iobase, sc->scano);
|
|
|
|
/* XXX
|
|
* What about using AUTO mode in msci->md0 ???
|
|
* And what about CTS/DCD etc... ?
|
|
*/
|
|
if(sc->hc->handshake & AR_SHSK_RTS)
|
|
msci->ctl &= ~SCA_CTL_RTS;
|
|
if(sc->hc->handshake & AR_SHSK_DTR) {
|
|
sc->hc->txc_dtr[sc->scano] &= sc->scachan ?
|
|
~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0;
|
|
outb(sc->hc->iobase + sc->hc->txc_dtr_off[sc->scano],
|
|
sc->hc->txc_dtr[sc->scano]);
|
|
}
|
|
|
|
if(sc->scachan == 0) {
|
|
sca->ier0 |= 0x0F;
|
|
sca->ier1 |= 0x0F;
|
|
} else {
|
|
sca->ier0 |= 0xF0;
|
|
sca->ier1 |= 0xF0;
|
|
}
|
|
|
|
msci->cmd = SCA_CMD_RXENABLE;
|
|
inb(sc->hc->iobase + AR_ID_5); /* XXX slow it down a bit. */
|
|
msci->cmd = SCA_CMD_TXENABLE;
|
|
|
|
ARC_SET_OFF(sc->hc->iobase);
|
|
}
|
|
|
|
static void ar_down(struct ar_softc *sc)
|
|
{
|
|
sca_regs *sca = sc->hc->sca;
|
|
msci_channel *msci = &sca->msci[sc->scachan];
|
|
|
|
sc->kdc.kdc_state = DC_IDLE;
|
|
|
|
/*
|
|
* Disable transmitter and receiver.
|
|
* Lower DTR and RTS.
|
|
* Disable interrupts.
|
|
*/
|
|
ARC_SET_SCA(sc->hc->iobase, sc->scano);
|
|
msci->cmd = SCA_CMD_RXDISABLE;
|
|
inb(sc->hc->iobase + AR_ID_5); /* XXX slow it down a bit. */
|
|
msci->cmd = SCA_CMD_TXDISABLE;
|
|
|
|
if(sc->hc->handshake & AR_SHSK_RTS)
|
|
msci->ctl |= SCA_CTL_RTS;
|
|
if(sc->hc->handshake & AR_SHSK_DTR) {
|
|
sc->hc->txc_dtr[sc->scano] |= sc->scachan ?
|
|
AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0;
|
|
outb(sc->hc->iobase + sc->hc->txc_dtr_off[sc->scano],
|
|
sc->hc->txc_dtr[sc->scano]);
|
|
}
|
|
|
|
if(sc->scachan == 0) {
|
|
sca->ier0 &= ~0x0F;
|
|
sca->ier1 &= ~0x0F;
|
|
} else {
|
|
sca->ier0 &= ~0xF0;
|
|
sca->ier1 &= ~0xF0;
|
|
}
|
|
|
|
ARC_SET_OFF(sc->hc->iobase);
|
|
}
|
|
|
|
/*
|
|
* Initialize the card, allocate memory for the ar_softc structures
|
|
* and fill in the pointers.
|
|
*/
|
|
void arc_init(struct isa_device *id)
|
|
{
|
|
struct ar_hardc *hc = &ar_hardc[id->id_unit];
|
|
struct ar_softc *sc;
|
|
int x;
|
|
u_int chanmem;
|
|
u_int bufmem;
|
|
u_int next;
|
|
u_int descneeded;
|
|
u_char isr, mar;
|
|
|
|
sc = hc->sc = malloc(hc->numports * sizeof(struct ar_softc),
|
|
M_DEVBUF, M_WAITOK);
|
|
bzero(sc, hc->numports * sizeof(struct ar_softc));
|
|
|
|
hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET |
|
|
AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
|
|
hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
|
|
hc->txc_dtr_off[0] = AR_TXC_DTR0;
|
|
hc->txc_dtr_off[1] = AR_TXC_DTR2;
|
|
|
|
/*
|
|
* reset the card and wait at least 1uS.
|
|
*/
|
|
outb(hc->iobase + AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET & hc->txc_dtr[0]);
|
|
DELAY(2);
|
|
outb(hc->iobase + AR_TXC_DTR0, hc->txc_dtr[0]);
|
|
|
|
/*
|
|
* Configure the card.
|
|
* Mem address, irq,
|
|
*/
|
|
mar = kvtop(id->id_maddr) >> 16;
|
|
isr = irqtable[ffs(id->id_irq) - 1] << 1;
|
|
if(isr == 0)
|
|
printf("ar%d: Warning illegal interrupt %d\n",
|
|
id->id_unit, ffs(id->id_irq) - 1);
|
|
isr = isr | ((kvtop(id->id_maddr) & 0xc000) >> 10);
|
|
|
|
hc->sca = (sca_regs *)hc->mem_start;
|
|
|
|
outb(hc->iobase + AR_MEM_SEL, mar);
|
|
outb(hc->iobase + AR_INT_SEL, isr | AR_INTS_CEN);
|
|
|
|
/*
|
|
* Make TX clock output and enable TX.
|
|
*/
|
|
hc->txc_dtr[0] |= AR_TXC_DTR_TX0 | AR_TXC_DTR_TX1 |
|
|
AR_TXC_DTR_TXCS0 | AR_TXC_DTR_TXCS1;
|
|
outb(hc->iobase + AR_TXC_DTR0, hc->txc_dtr[0]);
|
|
if(hc->numports > NCHAN) {
|
|
hc->txc_dtr[1] |= AR_TXC_DTR_TX0 | AR_TXC_DTR_TX1 |
|
|
AR_TXC_DTR_TXCS0 | AR_TXC_DTR_TXCS1;
|
|
outb(hc->iobase + AR_TXC_DTR2, hc->txc_dtr[1]);
|
|
}
|
|
|
|
chanmem = hc->memsize / hc->numports;
|
|
next = 0;
|
|
|
|
for(x=0;x<hc->numports;x++, sc++) {
|
|
sc->txdesc = next;
|
|
bufmem = 16 * 1024;
|
|
descneeded = bufmem / AR_BUF_SIZ;
|
|
sc->txstart = sc->txdesc +
|
|
((((descneeded * sizeof(sca_descriptor)) /
|
|
AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
|
|
sc->txend = next + bufmem;
|
|
sc->txmax = (sc->txend - sc->txstart) / AR_BUF_SIZ;
|
|
next += bufmem;
|
|
|
|
TRC(printf("ar%d: txdesc %x, txstart %x, txend %x, txmax %d\n",
|
|
x,
|
|
sc->txdesc, sc->txstart, sc->txend, sc->txmax));
|
|
|
|
sc->rxdesc = next;
|
|
bufmem = chanmem - bufmem;
|
|
descneeded = bufmem / AR_BUF_SIZ;
|
|
sc->rxstart = sc->rxdesc +
|
|
((((descneeded * sizeof(sca_descriptor)) /
|
|
AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
|
|
sc->rxend = next + bufmem;
|
|
sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ;
|
|
next += bufmem;
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* The things done here are channel independent.
|
|
*
|
|
* Configure the sca waitstates.
|
|
* Configure the global interrupt registers.
|
|
* Enable master dma enable.
|
|
*/
|
|
static void ar_init_sca(struct ar_hardc *hc, int scano)
|
|
{
|
|
sca_regs *sca = hc->sca;
|
|
|
|
ARC_SET_SCA(hc->iobase, scano);
|
|
|
|
/*
|
|
* Do the wait registers.
|
|
* Set everything to 0 wait states.
|
|
*/
|
|
sca->pabr0 = 0;
|
|
sca->pabr1 = 0;
|
|
sca->wcrl = 0;
|
|
sca->wcrm = 0;
|
|
sca->wcrh = 0;
|
|
|
|
/*
|
|
* Configure the interrupt registers.
|
|
* Most are cleared until the interface is configured.
|
|
*/
|
|
sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */
|
|
sca->ier1 = 0x00; /* DMAC interrupts */
|
|
sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */
|
|
sca->itcr = 0x00; /* Use ivr and no intr ack */
|
|
sca->ivr = 0x40; /* Fill in the interrupt vector. */
|
|
sca->imvr = 0x40;
|
|
|
|
/*
|
|
* Configure the timers.
|
|
* XXX Later
|
|
*/
|
|
|
|
|
|
sca->dmer = SCA_DMER_EN; /* Enable all dma channels. */
|
|
}
|
|
|
|
|
|
/*
|
|
* Configure the msci
|
|
*
|
|
* NOTE: The serial port configuration is hardcoded at the moment.
|
|
*/
|
|
void ar_init_msci(struct ar_softc *sc)
|
|
{
|
|
msci_channel *msci = &sc->hc->sca->msci[sc->scachan];
|
|
|
|
ARC_SET_SCA(sc->hc->iobase, sc->scano);
|
|
|
|
msci->cmd = SCA_CMD_RESET;
|
|
|
|
msci->md0 = SCA_MD0_CRC_1 |
|
|
SCA_MD0_CRC_CCITT |
|
|
SCA_MD0_CRC_ENABLE |
|
|
SCA_MD0_MODE_HDLC;
|
|
msci->md1 = SCA_MD1_NOADDRCHK;
|
|
msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ;
|
|
|
|
/*
|
|
* Acording to the manual I should give a reset after changing the
|
|
* mode registers.
|
|
*/
|
|
msci->cmd = SCA_CMD_RXRESET;
|
|
msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS;
|
|
|
|
/*
|
|
* For now all interfaces are programmed to use the RX clock for
|
|
* the TX clock.
|
|
*/
|
|
switch(sc->hc->interface) {
|
|
case AR_IFACE_V_35:
|
|
case AR_IFACE_X_21:
|
|
case AR_IFACE_EIA_530:
|
|
case AR_IFACE_COMBO:
|
|
msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
|
|
msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1;
|
|
}
|
|
|
|
msci->tmc = 153; /* This give 64k for loopback */
|
|
|
|
/* XXX
|
|
* Disable all interrupts for now. I think if you are using
|
|
* the dmac you don't use these interrupts.
|
|
*/
|
|
msci->ie0 = 0;
|
|
msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */
|
|
msci->ie2 = 0;
|
|
msci->fie = 0;
|
|
|
|
msci->sa0 = 0;
|
|
msci->sa1 = 0;
|
|
|
|
msci->idl = 0x7E; /* XXX This is what cisco does. */
|
|
|
|
/*
|
|
* This is what the ARNET diags use.
|
|
*/
|
|
msci->rrc = 0x0E;
|
|
msci->trc0 = 0x12;
|
|
msci->trc1 = 0x1F;
|
|
}
|
|
|
|
/*
|
|
* Configure the rx dma controller.
|
|
*/
|
|
void ar_init_rx_dmac(struct ar_softc *sc)
|
|
{
|
|
dmac_channel *dmac = &sc->hc->sca->dmac[DMAC_RXCH(sc->scachan)];
|
|
sca_descriptor *rxd;
|
|
u_int rxbuf;
|
|
u_int rxda;
|
|
u_int rxda_d;
|
|
|
|
ARC_SET_MEM(sc->hc->iobase, sc->rxdesc);
|
|
|
|
rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&ARC_WIN_MSK));
|
|
rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~ARC_WIN_MSK);
|
|
|
|
for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) {
|
|
rxda = (u_int)&rxd[1] - rxda_d;
|
|
rxd->cp = (u_short)(rxda & 0xfffful);
|
|
|
|
TRC(printf("Descrp %p, data pt %p, data long %lx, ",
|
|
&sc->rxdesc[x], rxinuse->buf, rxbuf));
|
|
|
|
rxd->bp = (u_short)(rxbuf & 0xfffful);
|
|
rxd->bpb = (u_char)((rxbuf >> 16) & 0xff);
|
|
rxd->len = 0;
|
|
rxd->stat = 0xff; /* The sca write here when it is finished. */
|
|
|
|
TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp));
|
|
}
|
|
rxd--;
|
|
rxd->cp = (u_short)(sc->rxdesc & 0xfffful);
|
|
|
|
sc->rxhind = 0;
|
|
|
|
ARC_SET_SCA(sc->hc->iobase, sc->scano);
|
|
|
|
dmac->dsr = 0; /* Disable DMA transfer */
|
|
dmac->dcr = SCA_DCR_ABRT;
|
|
|
|
/* XXX maybe also SCA_DMR_CNTE */
|
|
dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
|
|
dmac->bfl = AR_BUF_SIZ;
|
|
|
|
dmac->cda = (u_short)(sc->rxdesc & 0xffff);
|
|
dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff);
|
|
|
|
rxd = (sca_descriptor *)sc->rxstart;
|
|
dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff);
|
|
|
|
dmac->dir = 0xF0;
|
|
|
|
dmac->dsr = SCA_DSR_DE;
|
|
}
|
|
|
|
/*
|
|
* Configure the TX DMA descriptors.
|
|
* Initialize the needed values and chain the descriptors.
|
|
*/
|
|
void ar_init_tx_dmac(struct ar_softc *sc)
|
|
{
|
|
dmac_channel *dmac = &sc->hc->sca->dmac[DMAC_TXCH(sc->scachan)];
|
|
sca_descriptor *txd;
|
|
u_int txbuf;
|
|
u_int txda;
|
|
u_int txda_d;
|
|
|
|
ARC_SET_MEM(sc->hc->iobase, sc->txdesc);
|
|
|
|
txd = (sca_descriptor *)(sc->hc->mem_start + (sc->txdesc&ARC_WIN_MSK));
|
|
txda_d = (u_int)sc->hc->mem_start - (sc->txdesc & ~ARC_WIN_MSK);
|
|
|
|
for(txbuf=sc->txstart;txbuf<sc->txend;txbuf += AR_BUF_SIZ, txd++) {
|
|
txda = (u_int)&txd[1] - txda_d;
|
|
txd->cp = (u_short)(txda & 0xfffful);
|
|
|
|
txd->bp = (u_short)(txbuf & 0xfffful);
|
|
txd->bpb = (u_char)((txbuf >> 16) & 0xff);
|
|
TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n",
|
|
sc->unit, txbuf, txd->bpb, txd->bp));
|
|
txd->len = 0;
|
|
txd->stat = 0;
|
|
}
|
|
txd--;
|
|
txd->cp = (u_short)(sc->txdesc & 0xfffful);
|
|
|
|
sc->txtail = (u_int)txd - (u_int)sc->hc->mem_start;
|
|
TRC(printf("TX Descriptors start %x, end %x.\n",
|
|
sc->txhead,
|
|
sc->txtail));
|
|
|
|
ARC_SET_SCA(sc->hc->iobase, sc->scano);
|
|
|
|
dmac->dsr = 0; /* Disable DMA */
|
|
dmac->dcr = SCA_DCR_ABRT;
|
|
dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
|
|
dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF;
|
|
|
|
dmac->sarb = (u_char)((sc->txdesc >> 16) & 0xff);
|
|
}
|
|
|
|
|
|
/*
|
|
* Look through the descriptors to see if there is a complete packet
|
|
* available. Stop if we get to where the sca is busy.
|
|
*
|
|
* Return the length and status of the packet.
|
|
* Return nonzero if there is a packet available.
|
|
*/
|
|
static int
|
|
ar_packet_avail(struct ar_softc *sc,
|
|
int *len,
|
|
u_char *rxstat)
|
|
{
|
|
sca_descriptor *rxdesc;
|
|
sca_descriptor *endp;
|
|
|
|
ARC_SET_MEM(sc->hc->iobase, sc->rxdesc);
|
|
rxdesc = (sca_descriptor *)
|
|
(sc->hc->mem_start + (sc->rxdesc & ARC_WIN_MSK));
|
|
endp = rxdesc;
|
|
rxdesc = &rxdesc[sc->rxhind];
|
|
endp = &endp[sc->rxmax];
|
|
|
|
*len = 0;
|
|
|
|
while(rxdesc->stat != 0xff) {
|
|
*len += rxdesc->len;
|
|
|
|
if(rxdesc->stat & SCA_DESC_EOM) {
|
|
*rxstat = rxdesc->stat;
|
|
TRC(printf("ar%d: PKT AVAIL len %d, %x, bufs %u.\n",
|
|
sc->unit, *len, *rxstat, x));
|
|
return 1;
|
|
}
|
|
rxdesc++;
|
|
if(rxdesc == endp)
|
|
rxdesc = (sca_descriptor *)
|
|
(sc->hc->mem_start + (sc->rxdesc & ARC_WIN_MSK));
|
|
}
|
|
|
|
*len = 0;
|
|
*rxstat = 0;
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Copy a packet from the on card memory into a provided mbuf.
|
|
* Take into account that buffers wrap and that a packet may
|
|
* be larger than a buffer.
|
|
*/
|
|
static void
|
|
ar_copy_rxbuf(struct mbuf *m,
|
|
struct ar_softc *sc,
|
|
int len)
|
|
{
|
|
sca_descriptor *rxdesc;
|
|
u_int rxdata;
|
|
u_int rxmax;
|
|
u_int off = 0;
|
|
u_int tlen;
|
|
|
|
rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ);
|
|
rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ);
|
|
|
|
rxdesc = (sca_descriptor *)
|
|
(sc->hc->mem_start + (sc->rxdesc & ARC_WIN_MSK));
|
|
rxdesc = &rxdesc[sc->rxhind];
|
|
|
|
while(len) {
|
|
tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ;
|
|
ARC_SET_MEM(sc->hc->iobase, rxdata);
|
|
bcopy(sc->hc->mem_start + (rxdata & ARC_WIN_MSK),
|
|
mtod(m, caddr_t) + off,
|
|
tlen);
|
|
|
|
off += tlen;
|
|
len -= tlen;
|
|
|
|
ARC_SET_MEM(sc->hc->iobase, sc->rxdesc);
|
|
rxdesc->len = 0;
|
|
rxdesc->stat = 0xff;
|
|
|
|
rxdata += AR_BUF_SIZ;
|
|
rxdesc++;
|
|
if(rxdata == rxmax) {
|
|
rxdata = sc->rxstart;
|
|
rxdesc = (sca_descriptor *)
|
|
(sc->hc->mem_start + (sc->rxdesc & ARC_WIN_MSK));
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Just eat a packet. Update pointers to point to the next packet.
|
|
*/
|
|
static void
|
|
ar_eat_packet(struct ar_softc *sc)
|
|
{
|
|
sca_descriptor *rxdesc;
|
|
sca_descriptor *endp;
|
|
|
|
/*
|
|
* Loop until desc->stat == (0xff || EOM)
|
|
* Clear the status and length in the descriptor.
|
|
* Increment the descriptor.
|
|
*/
|
|
ARC_SET_MEM(sc->hc->iobase, sc->rxdesc);
|
|
rxdesc = (sca_descriptor *)
|
|
(sc->hc->mem_start + (sc->rxdesc & ARC_WIN_MSK));
|
|
endp = rxdesc;
|
|
rxdesc = &rxdesc[sc->rxhind];
|
|
endp = &endp[sc->rxmax];
|
|
|
|
while(rxdesc->stat != 0xff) {
|
|
if((rxdesc->stat & ~SCA_DESC_EOM) == 0)
|
|
break;
|
|
|
|
rxdesc->len = 0;
|
|
rxdesc->stat = 0xff;
|
|
|
|
rxdesc++;
|
|
sc->rxhind++;
|
|
if(rxdesc == endp) {
|
|
rxdesc = (sca_descriptor *)
|
|
(sc->hc->mem_start + (sc->rxdesc & ARC_WIN_MSK));
|
|
sc->rxhind = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* While there is packets available in the rx buffer, read them out
|
|
* into mbufs and ship them off.
|
|
*/
|
|
static void
|
|
ar_get_packets(struct ar_softc *sc)
|
|
{
|
|
sca_descriptor *rxdesc;
|
|
struct mbuf *m = NULL;
|
|
int i;
|
|
int len;
|
|
u_char rxstat;
|
|
|
|
while(ar_packet_avail(sc, &len, &rxstat)) {
|
|
if((rxstat & SCA_DESC_ERRORS) == 0) {
|
|
MGETHDR(m, M_DONTWAIT, MT_DATA);
|
|
if(m != NULL) {
|
|
MCLGET(m, M_DONTWAIT);
|
|
if((m->m_flags & M_EXT) != 0) {
|
|
m->m_pkthdr.rcvif = &sc->ifsppp.pp_if;
|
|
m->m_pkthdr.len = m->m_len = len;
|
|
ar_copy_rxbuf(m, sc, len);
|
|
#if NBPFILTER > 0
|
|
if(sc->ifsppp.pp_if.if_bpf)
|
|
bpf_mtap(&sc->ifsppp.pp_if, m);
|
|
#endif
|
|
sppp_input(&sc->ifsppp.pp_if, m);
|
|
sc->ifsppp.pp_if.if_ipackets++;
|
|
} else {
|
|
m_freem(m);
|
|
/* eat packet if get mbuf fail!! */
|
|
ar_eat_packet(sc);
|
|
}
|
|
} else {
|
|
/* eat packet if get mbuf fail!! */
|
|
ar_eat_packet(sc);
|
|
}
|
|
} else {
|
|
msci_channel *msci = &sc->hc->sca->msci[sc->scachan];
|
|
|
|
ar_eat_packet(sc);
|
|
|
|
sc->ifsppp.pp_if.if_ierrors++;
|
|
|
|
ARC_SET_SCA(sc->hc->iobase, sc->scano);
|
|
|
|
TRCL(printf("RX%d So this does happen :), stat %x, "
|
|
"ST2 %x, cda %x.\n",
|
|
sc->scachan,
|
|
rxstat,
|
|
msci->st2,
|
|
sc->hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda));
|
|
|
|
/*
|
|
* Reset the rx unit.
|
|
*
|
|
* XXX Maybe it should only be done when certain
|
|
* errors occured. ie not for CRC errors?
|
|
*/
|
|
msci->cmd = SCA_CMD_RXRESET;
|
|
msci->cmd = SCA_CMD_RXENABLE;
|
|
|
|
TRCL(printf("RX%d After reset: ST2 %x.\n",
|
|
sc->scachan, msci->st2));
|
|
} /* else */
|
|
|
|
i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ;
|
|
sc->rxhind = (sc->rxhind + i) % sc->rxmax;
|
|
|
|
/*
|
|
* Update the eda to the previous descriptor.
|
|
*/
|
|
ARC_SET_SCA(sc->hc->iobase, sc->scano);
|
|
|
|
rxdesc = (sca_descriptor *)sc->rxdesc;
|
|
rxdesc = &rxdesc[(sc->rxhind + sc->rxmax -1 ) % sc->rxmax];
|
|
|
|
sc->hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
|
|
(u_short)((u_int)&rxdesc & 0xffff);
|
|
|
|
} /* while */
|
|
}
|
|
|
|
|
|
/*
|
|
* All DMA interrupts come here.
|
|
*
|
|
* Each channel has two interrupts.
|
|
* Interrupt A for errors and Interrupt B for normal stuff like end
|
|
* of transmit or receive dmas.
|
|
*/
|
|
static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1)
|
|
{
|
|
u_char dsr;
|
|
int mch;
|
|
struct ar_softc *sc;
|
|
sca_regs *sca = hc->sca;
|
|
dmac_channel *dmac;
|
|
|
|
mch = 0;
|
|
/*
|
|
* Shortcut if there is no interrupts for dma channel 0 or 1
|
|
*/
|
|
if((isr1 & 0x0F) == 0) {
|
|
mch = 1;
|
|
isr1 >>= 4;
|
|
}
|
|
|
|
do {
|
|
sc = &hc->sc[mch + (NCHAN * scano)];
|
|
dmac = &sca->dmac[DMAC_RXCH(mch)];
|
|
|
|
/*
|
|
* Receive channel
|
|
*/
|
|
if(isr1 & 0x03) {
|
|
ARC_SET_SCA(hc->iobase, scano);
|
|
|
|
dsr = dmac->dsr;
|
|
dmac->dsr = dsr;
|
|
|
|
TRC(printf("AR: RX DSR %x\n", dsr));
|
|
|
|
/* End of frame */
|
|
if(dsr & SCA_DSR_EOM) {
|
|
ar_get_packets(sc);
|
|
}
|
|
|
|
/* Counter overflow */
|
|
if(dsr & SCA_DSR_COF) {
|
|
printf("ar%d: RX DMA Counter overflow, "
|
|
"rxpkts %lu.\n",
|
|
sc->unit,
|
|
sc->ifsppp.pp_if.if_ipackets);
|
|
sc->ifsppp.pp_if.if_ierrors++;
|
|
}
|
|
|
|
/* Buffer overflow */
|
|
if(dsr & SCA_DSR_BOF) {
|
|
printf("ar%d: RX DMA Buffer overflow, "
|
|
"rxpkts %lu.\n",
|
|
sc->unit,
|
|
sc->ifsppp.pp_if.if_ipackets);
|
|
sc->ifsppp.pp_if.if_ierrors++;
|
|
dmac->dsr = SCA_DSR_DE;
|
|
}
|
|
|
|
/* End of Transfer */
|
|
if(dsr & SCA_DSR_EOT) {
|
|
/*
|
|
* If this happen, it means that we are
|
|
* receiving faster than what the processor
|
|
* can handle.
|
|
*
|
|
* XXX We should enable the dma again.
|
|
*/
|
|
printf("ar%d: RX End of transfer, rxpkts %lu.\n",
|
|
sc->unit,
|
|
sc->ifsppp.pp_if.if_ipackets);
|
|
sc->ifsppp.pp_if.if_ierrors++;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* We are finished with the 2 DMA status bits for RX now do TX.
|
|
*/
|
|
isr1 >>= 2;
|
|
|
|
/*
|
|
* Transmit channel
|
|
*/
|
|
if(isr1 & 0x03) {
|
|
dmac = &sca->dmac[DMAC_TXCH(mch)];
|
|
|
|
ARC_SET_SCA(hc->iobase, scano);
|
|
|
|
dsr = dmac->dsr;
|
|
dmac->dsr = dsr;
|
|
|
|
/* Counter overflow */
|
|
if(dsr & SCA_DSR_COF) {
|
|
printf("ar%d: TX DMA Counter overflow, "
|
|
"txpacket no %lu.\n",
|
|
sc->unit,
|
|
sc->ifsppp.pp_if.if_opackets);
|
|
sc->ifsppp.pp_if.if_oerrors++;
|
|
}
|
|
|
|
/* Buffer overflow */
|
|
if(dsr & SCA_DSR_BOF) {
|
|
printf("ar%d: TX DMA Buffer overflow, "
|
|
"txpacket no %lu, dsr %02x, "
|
|
"cda %04x, eda %04x.\n",
|
|
sc->unit,
|
|
sc->ifsppp.pp_if.if_opackets,
|
|
dsr,
|
|
dmac->cda,
|
|
dmac->eda);
|
|
sc->ifsppp.pp_if.if_oerrors++;
|
|
}
|
|
|
|
/* End of Transfer */
|
|
if(dsr & SCA_DSR_EOT) {
|
|
/*
|
|
* This should be the most common case.
|
|
*
|
|
* Clear the IFF_OACTIVE flag.
|
|
*
|
|
* Call arstart to start a new transmit if
|
|
* there is data to transmit.
|
|
*/
|
|
sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
|
|
sc->ifsppp.pp_if.if_timer = 0;
|
|
|
|
arstart(&sc->ifsppp.pp_if);
|
|
}
|
|
}
|
|
isr1 >>= 2;
|
|
|
|
mch++;
|
|
}while((mch<NCHAN) && isr1);
|
|
}
|
|
|
|
static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0)
|
|
{
|
|
printf("arc%d: ARINTR: MSCI\n", hc->cunit);
|
|
}
|
|
|
|
static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2)
|
|
{
|
|
printf("arc%d: ARINTR: TIMER\n", hc->cunit);
|
|
}
|
|
|
|
/*
|
|
********************************* END ************************************
|
|
*/
|
|
|