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382 lines
8.3 KiB
C
382 lines
8.3 KiB
C
/*-
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* Copyright (c) 2009 Yohanes Nugroho <yohanes@gmail.com>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include "econa_reg.h"
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#include "econa_var.h"
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#define INITIAL_TIMECOUNTER (0xffffffff)
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static int timers_initialized = 0;
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#define HZ 100
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extern unsigned int CPU_clock;
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extern unsigned int AHB_clock;
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extern unsigned int APB_clock;
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static unsigned long timer_counter = 0;
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struct ec_timer_softc {
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struct resource * timer_res[3];
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bus_space_tag_t timer_bst;
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bus_space_handle_t timer_bsh;
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struct mtx timer_mtx;
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};
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static struct resource_spec ec_timer_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ -1, 0 }
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};
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static unsigned ec_timer_get_timecount(struct timecounter *);
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static struct timecounter ec_timecounter = {
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.tc_get_timecount = ec_timer_get_timecount,
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.tc_name = "CPU Timer",
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/* This is assigned on the fly in the init sequence */
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.tc_frequency = 0,
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.tc_counter_mask = ~0u,
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.tc_quality = 1000,
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};
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static struct ec_timer_softc *timer_softc = NULL;
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static inline
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void write_4(unsigned int val, unsigned int addr)
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{
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bus_space_write_4(timer_softc->timer_bst,
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timer_softc->timer_bsh, addr, val);
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}
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static inline
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unsigned int read_4(unsigned int addr)
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{
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return bus_space_read_4(timer_softc->timer_bst,
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timer_softc->timer_bsh, addr);
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}
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#define uSECS_PER_TICK (1000000 / APB_clock)
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#define TICKS2USECS(x) ((x) * uSECS_PER_TICK)
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static unsigned
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read_timer_counter_noint(void)
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{
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arm_mask_irq(0);
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unsigned int v = read_4(TIMER_TM1_COUNTER_REG);
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arm_unmask_irq(0);
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return v;
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}
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void
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DELAY(int usec)
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{
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uint32_t val, val_temp;
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int nticks;
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if (!timers_initialized) {
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for (; usec > 0; usec--)
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for (val = 100; val > 0; val--)
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;
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return;
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}
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val = read_timer_counter_noint();
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nticks = (((APB_clock / 1000) * usec) / 1000) + 100;
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while (nticks > 0) {
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val_temp = read_timer_counter_noint();
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if (val > val_temp)
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nticks -= (val - val_temp);
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else
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nticks -= (val + (timer_counter - val_temp));
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val = val_temp;
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}
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}
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/*
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* Setup timer
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*/
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static inline void
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setup_timer(unsigned int counter_value)
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{
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unsigned int control_value;
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unsigned int mask_value;
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control_value = read_4(TIMER_TM_CR_REG);
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mask_value = read_4(TIMER_TM_INTR_MASK_REG);
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write_4(counter_value, TIMER_TM1_COUNTER_REG);
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write_4(counter_value, TIMER_TM1_LOAD_REG);
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write_4(0, TIMER_TM1_MATCH1_REG);
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write_4(0,TIMER_TM1_MATCH2_REG);
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control_value &= ~(TIMER1_CLOCK_SOURCE);
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control_value |= TIMER1_UP_DOWN_COUNT;
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write_4(0, TIMER_TM2_COUNTER_REG);
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write_4(0, TIMER_TM2_LOAD_REG);
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write_4(~0u, TIMER_TM2_MATCH1_REG);
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write_4(~0u,TIMER_TM2_MATCH2_REG);
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control_value &= ~(TIMER2_CLOCK_SOURCE);
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control_value &= ~(TIMER2_UP_DOWN_COUNT);
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mask_value &= ~(63);
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write_4(control_value, TIMER_TM_CR_REG);
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write_4(mask_value, TIMER_TM_INTR_MASK_REG);
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}
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/*
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* Enable timer
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*/
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static inline void
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timer_enable(void)
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{
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unsigned int control_value;
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control_value = read_4(TIMER_TM_CR_REG);
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control_value |= TIMER1_OVERFLOW_ENABLE;
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control_value |= TIMER1_ENABLE;
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control_value |= TIMER2_OVERFLOW_ENABLE;
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control_value |= TIMER2_ENABLE;
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write_4(control_value, TIMER_TM_CR_REG);
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}
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static inline unsigned int
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read_second_timer_counter(void)
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{
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return read_4(TIMER_TM2_COUNTER_REG);
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}
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/*
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* Get timer interrupt status
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*/
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static inline unsigned int
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read_timer_interrupt_status(void)
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{
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return read_4(TIMER_TM_INTR_STATUS_REG);
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}
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/*
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* Clear timer interrupt status
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*/
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static inline void
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clear_timer_interrupt_status(unsigned int irq)
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{
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unsigned int interrupt_status;
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interrupt_status = read_4(TIMER_TM_INTR_STATUS_REG);
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if (irq == 0) {
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if (interrupt_status & (TIMER1_MATCH1_INTR))
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interrupt_status &= ~(TIMER1_MATCH1_INTR);
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if (interrupt_status & (TIMER1_MATCH2_INTR))
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interrupt_status &= ~(TIMER1_MATCH2_INTR);
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if (interrupt_status & (TIMER1_OVERFLOW_INTR))
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interrupt_status &= ~(TIMER1_OVERFLOW_INTR);
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}
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if (irq == 1) {
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if (interrupt_status & (TIMER2_MATCH1_INTR))
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interrupt_status &= ~(TIMER2_MATCH1_INTR);
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if (interrupt_status & (TIMER2_MATCH2_INTR))
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interrupt_status &= ~(TIMER2_MATCH2_INTR);
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if (interrupt_status & (TIMER2_OVERFLOW_INTR))
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interrupt_status &= ~(TIMER2_OVERFLOW_INTR);
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}
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write_4(interrupt_status, TIMER_TM_INTR_STATUS_REG);
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}
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static unsigned
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ec_timer_get_timecount(struct timecounter *a)
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{
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unsigned int ticks1;
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arm_mask_irq(1);
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ticks1 = read_second_timer_counter();
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arm_unmask_irq(1);
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return ticks1;
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}
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/*
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* Setup timer
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*/
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static inline void
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do_setup_timer(void)
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{
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timer_counter = APB_clock/HZ;
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/*
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* setup timer-related values
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*/
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setup_timer(timer_counter);
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}
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void
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cpu_initclocks(void)
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{
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ec_timecounter.tc_frequency = APB_clock;
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tc_init(&ec_timecounter);
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timer_enable();
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timers_initialized = 1;
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}
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void
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cpu_startprofclock(void)
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{
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}
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void
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cpu_stopprofclock(void)
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{
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}
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static int
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ec_timer_probe(device_t dev)
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{
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device_set_desc(dev, "Econa CPU Timer");
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return (0);
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}
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static int
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ec_reset(void *arg)
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{
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arm_mask_irq(1);
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clear_timer_interrupt_status(1);
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arm_unmask_irq(1);
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return (FILTER_HANDLED);
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}
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static int
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ec_hardclock(void *arg)
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{
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struct trapframe *frame;
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unsigned int val;
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/*clear timer interrupt status*/
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arm_mask_irq(0);
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val = read_4(TIMER_INTERRUPT_STATUS_REG);
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val &= ~(TIMER1_OVERFLOW_INTERRUPT);
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write_4(val, TIMER_INTERRUPT_STATUS_REG);
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frame = (struct trapframe *)arg;
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hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
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arm_unmask_irq(0);
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return (FILTER_HANDLED);
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}
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static int
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ec_timer_attach(device_t dev)
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{
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struct ec_timer_softc *sc;
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int error;
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void *ihl;
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if (timer_softc != NULL)
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return (ENXIO);
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sc = (struct ec_timer_softc *)device_get_softc(dev);
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timer_softc = sc;
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error = bus_alloc_resources(dev, ec_timer_spec, sc->timer_res);
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if (error) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
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sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
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do_setup_timer();
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if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
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ec_hardclock, NULL, NULL, &ihl) != 0) {
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bus_release_resources(dev, ec_timer_spec, sc->timer_res);
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device_printf(dev, "could not setup hardclock interrupt\n");
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return (ENXIO);
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}
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if (bus_setup_intr(dev, sc->timer_res[2], INTR_TYPE_CLK,
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ec_reset, NULL, NULL, &ihl) != 0) {
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bus_release_resources(dev, ec_timer_spec, sc->timer_res);
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device_printf(dev, "could not setup timer interrupt\n");
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return (ENXIO);
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}
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return (0);
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}
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static device_method_t ec_timer_methods[] = {
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DEVMETHOD(device_probe, ec_timer_probe),
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DEVMETHOD(device_attach, ec_timer_attach),
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{ 0, 0 }
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};
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static driver_t ec_timer_driver = {
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"timer",
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ec_timer_methods,
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sizeof(struct ec_timer_softc),
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};
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static devclass_t ec_timer_devclass;
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DRIVER_MODULE(timer, econaarm, ec_timer_driver, ec_timer_devclass, 0, 0);
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