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cd036e891a
If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days
206 lines
6.6 KiB
C
206 lines
6.6 KiB
C
/*
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* Interface for the 93C66/56/46/26/06 serial eeprom parts.
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*
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* Copyright (c) 1995, 1996 Daniel M. Eischen
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU Public License ("GPL").
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: //depot/src/aic7xxx/aic7xxx_93cx6.c#8 $
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*
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* $FreeBSD$
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*/
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/*
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* The instruction set of the 93C66/56/46/26/06 chips are as follows:
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*
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* Start OP *
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* Function Bit Code Address** Data Description
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* -------------------------------------------------------------------
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* READ 1 10 A5 - A0 Reads data stored in memory,
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* starting at specified address
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* EWEN 1 00 11XXXX Write enable must precede
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* all programming modes
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* ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0
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* WRITE 1 01 A5 - A0 D15 - D0 Writes register
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* ERAL 1 00 10XXXX Erase all registers
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* WRAL 1 00 01XXXX D15 - D0 Writes to all registers
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* EWDS 1 00 00XXXX Disables all programming
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* instructions
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* *Note: A value of X for address is a don't care condition.
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* **Note: There are 8 address bits for the 93C56/66 chips unlike
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* the 93C46/26/06 chips which have 6 address bits.
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*
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* The 93C46 has a four wire interface: clock, chip select, data in, and
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* data out. In order to perform one of the above functions, you need
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* to enable the chip select for a clock period (typically a minimum of
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* 1 usec, with the clock high and low a minimum of 750 and 250 nsec
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* respectively). While the chip select remains high, you can clock in
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* the instructions (above) starting with the start bit, followed by the
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* OP code, Address, and Data (if needed). For the READ instruction, the
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* requested 16-bit register contents is read from the data out line but
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* is preceded by an initial zero (leading 0, followed by 16-bits, MSB
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* first). The clock cycling from low to high initiates the next data
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* bit to be sent from the chip.
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*
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*/
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#include <dev/aic7xxx/aic7xxx_freebsd.h>
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#include <dev/aic7xxx/aic7xxx_inline.h>
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#include <dev/aic7xxx/aic7xxx_93cx6.h>
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/*
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* Right now, we only have to read the SEEPROM. But we make it easier to
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* add other 93Cx6 functions.
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*/
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static struct seeprom_cmd {
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uint8_t len;
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uint8_t bits[3];
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} seeprom_read = {3, {1, 1, 0}};
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/*
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* Wait for the SEERDY to go high; about 800 ns.
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*/
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#define CLOCK_PULSE(sd, rdy) \
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while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) { \
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; /* Do nothing */ \
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} \
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(void)SEEPROM_INB(sd); /* Clear clock */
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/*
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* Read the serial EEPROM and returns 1 if successful and 0 if
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* not successful.
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*/
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int
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read_seeprom(sd, buf, start_addr, count)
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struct seeprom_descriptor *sd;
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uint16_t *buf;
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u_int start_addr;
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u_int count;
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{
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int i = 0;
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u_int k = 0;
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uint16_t v;
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uint8_t temp;
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/*
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* Read the requested registers of the seeprom. The loop
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* will range from 0 to count-1.
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*/
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for (k = start_addr; k < count + start_addr; k++) {
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/* Send chip select for one clock cycle. */
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temp = sd->sd_MS ^ sd->sd_CS;
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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/*
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* Now we're ready to send the read command followed by the
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* address of the 16-bit register we want to read.
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*/
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for (i = 0; i < seeprom_read.len; i++) {
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if (seeprom_read.bits[i] != 0)
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temp ^= sd->sd_DO;
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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if (seeprom_read.bits[i] != 0)
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temp ^= sd->sd_DO;
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}
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/* Send the 6 or 8 bit address (MSB first, LSB last). */
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for (i = (sd->sd_chip - 1); i >= 0; i--) {
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if ((k & (1 << i)) != 0)
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temp ^= sd->sd_DO;
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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if ((k & (1 << i)) != 0)
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temp ^= sd->sd_DO;
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}
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/*
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* Now read the 16 bit register. An initial 0 precedes the
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* register contents which begins with bit 15 (MSB) and ends
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* with bit 0 (LSB). The initial 0 will be shifted off the
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* top of our word as we let the loop run from 0 to 16.
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*/
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v = 0;
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for (i = 16; i >= 0; i--) {
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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v <<= 1;
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if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
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v |= 1;
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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}
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buf[k - start_addr] = v;
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/* Reset the chip select for the next command cycle. */
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temp = sd->sd_MS;
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
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CLOCK_PULSE(sd, sd->sd_RDY);
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SEEPROM_OUTB(sd, temp);
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CLOCK_PULSE(sd, sd->sd_RDY);
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}
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#ifdef AHC_DUMP_EEPROM
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printf("\nSerial EEPROM:\n\t");
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for (k = 0; k < count; k = k + 1) {
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if (((k % 8) == 0) && (k != 0)) {
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printf ("\n\t");
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}
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printf (" 0x%x", buf[k]);
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}
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printf ("\n");
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#endif
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return (1);
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}
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int
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verify_cksum(struct seeprom_config *sc)
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{
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int i;
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int maxaddr;
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uint32_t checksum;
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uint16_t *scarray;
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maxaddr = (sizeof(*sc)/2) - 1;
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checksum = 0;
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scarray = (uint16_t *)sc;
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for (i = 0; i < maxaddr; i++)
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checksum = checksum + scarray[i];
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if (checksum == 0
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|| (checksum & 0xFFFF) != sc->checksum) {
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return (0);
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} else {
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return(1);
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}
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}
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