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in cyopen() were done in a different order than in sioopen(), partly to (ab)use a side effect of comparam() and partly because I didn't understand what the reset was doing (it flushes the fifos). This turned out to be more than a cosmetic problem. Flushing the fifos quite late is good for discarding input that arrived while the line state was being initialized, and in the cy driver it also seems to reduce a problem with input that arrived long ago during the previous close (the UART loses sync too easily and for too long). |
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cy_isa.c | ||
cy_pci.c | ||
cy.c | ||
cyreg.h |