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2b71562fd8
mechanism defined for armv7 (and also present on some armv6 chips including the arm1176 used on rpi). The information is parsed into a global cpuinfo structure, which will be used by (upcoming) new cache and tlb maintenance code to handle cpu-specific variations of the maintence sequences. Submitted by: Svatopluk Kraus <onwahe@gmail.com>, Michal Meloun <meloun@miracle.cz |
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allwinner | ||
altera/socfpga | ||
arm | ||
at91 | ||
broadcom/bcm2835 | ||
cavium/cns11xx | ||
conf | ||
freescale | ||
include | ||
lpc | ||
mv | ||
rockchip | ||
samsung | ||
ti | ||
versatile | ||
xilinx | ||
xscale |