mirror of
https://git.FreeBSD.org/src.git
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56427 lines
1.5 MiB
56427 lines
1.5 MiB
/* This file is automatically generated --- changes will be lost */
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/* Generation Date : Tue Jan 28 03:02:08 IST 2020 */
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/* Directory name: t6_reg.txt, Changeset: 4272:a648ba4d5c0c */
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struct reg_info t6_sge_regs[] = {
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{ "SGE_PF_KDOORBELL", 0x1e000, 0 },
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{ "QID", 15, 17 },
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{ "Sync", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1e004, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1e008, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1e00c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1e400, 0 },
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{ "QID", 15, 17 },
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{ "Sync", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1e404, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1e408, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1e40c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1e800, 0 },
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{ "QID", 15, 17 },
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{ "Sync", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1e804, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1e808, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1e80c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1ec00, 0 },
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{ "QID", 15, 17 },
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{ "Sync", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1ec04, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1ec08, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1ec0c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1f000, 0 },
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{ "QID", 15, 17 },
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{ "Sync", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1f004, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1f008, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1f00c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1f400, 0 },
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{ "QID", 15, 17 },
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{ "Sync", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1f404, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1f408, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1f40c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1f800, 0 },
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{ "QID", 15, 17 },
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{ "Sync", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1f804, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1f808, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1f80c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1fc00, 0 },
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{ "QID", 15, 17 },
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{ "Sync", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1fc04, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1fc08, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1fc0c, 0 },
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{ "SGE_CONTROL", 0x1008, 0 },
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{ "IgrAllCPLtoFL", 31, 1 },
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{ "FLSplitMin", 22, 9 },
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{ "RxPktCPLMode", 18, 1 },
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{ "EgrStatusPageSize", 17, 1 },
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{ "IngHintEnable1", 15, 1 },
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{ "IngHintEnable0", 14, 1 },
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{ "IngIntCompareIDX", 13, 1 },
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{ "PktShift", 10, 3 },
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{ "IngPCIeBoundary", 7, 3 },
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{ "IngPadBoundary", 4, 3 },
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{ "GlobalEnable", 0, 1 },
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{ "SGE_HOST_PAGE_SIZE", 0x100c, 0 },
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{ "HostPageSizePF7", 28, 4 },
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{ "HostPageSizePF6", 24, 4 },
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{ "HostPageSizePF5", 20, 4 },
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{ "HostPageSizePF4", 16, 4 },
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{ "HostPageSizePF3", 12, 4 },
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{ "HostPageSizePF2", 8, 4 },
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{ "HostPageSizePF1", 4, 4 },
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{ "HostPageSizePF0", 0, 4 },
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{ "SGE_EGRESS_QUEUES_PER_PAGE_PF", 0x1010, 0 },
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{ "QueuesPerPagePF7", 28, 4 },
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{ "QueuesPerPagePF6", 24, 4 },
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{ "QueuesPerPagePF5", 20, 4 },
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{ "QueuesPerPagePF4", 16, 4 },
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{ "QueuesPerPagePF3", 12, 4 },
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{ "QueuesPerPagePF2", 8, 4 },
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{ "QueuesPerPagePF1", 4, 4 },
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{ "QueuesPerPagePF0", 0, 4 },
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{ "SGE_EGRESS_QUEUES_PER_PAGE_VF", 0x1014, 0 },
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{ "QueuesPerPageVFPF7", 28, 4 },
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{ "QueuesPerPageVFPF6", 24, 4 },
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{ "QueuesPerPageVFPF5", 20, 4 },
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{ "QueuesPerPageVFPF4", 16, 4 },
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{ "QueuesPerPageVFPF3", 12, 4 },
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{ "QueuesPerPageVFPF2", 8, 4 },
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{ "QueuesPerPageVFPF1", 4, 4 },
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{ "QueuesPerPageVFPF0", 0, 4 },
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{ "SGE_USER_MODE_LIMITS", 0x1018, 0 },
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{ "Opcode_Min", 24, 8 },
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{ "Opcode_Max", 16, 8 },
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{ "Length_Min", 8, 8 },
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{ "Length_Max", 0, 8 },
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{ "SGE_WR_ERROR", 0x101c, 0 },
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{ "SGE_INT_CAUSE1", 0x1024, 0 },
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{ "perr_flm_CreditFifo", 30, 1 },
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{ "perr_imsg_hint_fifo", 29, 1 },
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{ "perr_pc_rsp", 23, 1 },
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{ "perr_pc_req", 22, 1 },
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{ "perr_dbp_pc_rsp_fifo3", 21, 1 },
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{ "perr_dbp_pc_rsp_fifo2", 20, 1 },
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{ "perr_dbp_pc_rsp_fifo1", 19, 1 },
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{ "perr_dbp_pc_rsp_fifo0", 18, 1 },
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{ "perr_dmarbt", 17, 1 },
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{ "perr_flm_DbpFifo", 16, 1 },
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{ "perr_flm_MCReq_fifo", 15, 1 },
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{ "perr_flm_HintFifo", 14, 1 },
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{ "perr_align_ctl_fifo3", 13, 1 },
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{ "perr_align_ctl_fifo2", 12, 1 },
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{ "perr_align_ctl_fifo1", 11, 1 },
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{ "perr_align_ctl_fifo0", 10, 1 },
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{ "perr_edma_fifo3", 9, 1 },
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{ "perr_edma_fifo2", 8, 1 },
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{ "perr_edma_fifo1", 7, 1 },
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{ "perr_edma_fifo0", 6, 1 },
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{ "perr_pd_fifo3", 5, 1 },
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{ "perr_pd_fifo2", 4, 1 },
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{ "perr_pd_fifo1", 3, 1 },
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{ "perr_pd_fifo0", 2, 1 },
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{ "perr_ing_ctxt_mifrsp", 1, 1 },
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{ "perr_egr_ctxt_mifrsp", 0, 1 },
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{ "SGE_INT_ENABLE1", 0x1028, 0 },
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{ "perr_flm_CreditFifo", 30, 1 },
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{ "perr_imsg_hint_fifo", 29, 1 },
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{ "perr_pc_rsp", 23, 1 },
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{ "perr_pc_req", 22, 1 },
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{ "perr_dbp_pc_rsp_fifo3", 21, 1 },
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{ "perr_dbp_pc_rsp_fifo2", 20, 1 },
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{ "perr_dbp_pc_rsp_fifo1", 19, 1 },
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{ "perr_dbp_pc_rsp_fifo0", 18, 1 },
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{ "perr_dmarbt", 17, 1 },
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{ "perr_flm_DbpFifo", 16, 1 },
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{ "perr_flm_MCReq_fifo", 15, 1 },
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{ "perr_flm_HintFifo", 14, 1 },
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{ "perr_align_ctl_fifo3", 13, 1 },
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{ "perr_align_ctl_fifo2", 12, 1 },
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{ "perr_align_ctl_fifo1", 11, 1 },
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{ "perr_align_ctl_fifo0", 10, 1 },
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{ "perr_edma_fifo3", 9, 1 },
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{ "perr_edma_fifo2", 8, 1 },
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{ "perr_edma_fifo1", 7, 1 },
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{ "perr_edma_fifo0", 6, 1 },
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{ "perr_pd_fifo3", 5, 1 },
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{ "perr_pd_fifo2", 4, 1 },
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{ "perr_pd_fifo1", 3, 1 },
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{ "perr_pd_fifo0", 2, 1 },
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{ "perr_ing_ctxt_mifrsp", 1, 1 },
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{ "perr_egr_ctxt_mifrsp", 0, 1 },
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{ "SGE_PERR_ENABLE1", 0x102c, 0 },
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{ "perr_flm_CreditFifo", 30, 1 },
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{ "perr_imsg_hint_fifo", 29, 1 },
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{ "perr_pc_rsp", 23, 1 },
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{ "perr_pc_req", 22, 1 },
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{ "perr_dbp_pc_rsp_fifo3", 21, 1 },
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{ "perr_dbp_pc_rsp_fifo2", 20, 1 },
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{ "perr_dbp_pc_rsp_fifo1", 19, 1 },
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{ "perr_dbp_pc_rsp_fifo0", 18, 1 },
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{ "perr_dmarbt", 17, 1 },
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{ "perr_flm_DbpFifo", 16, 1 },
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{ "perr_flm_MCReq_fifo", 15, 1 },
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{ "perr_flm_HintFifo", 14, 1 },
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{ "perr_align_ctl_fifo3", 13, 1 },
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{ "perr_align_ctl_fifo2", 12, 1 },
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{ "perr_align_ctl_fifo1", 11, 1 },
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{ "perr_align_ctl_fifo0", 10, 1 },
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{ "perr_edma_fifo3", 9, 1 },
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{ "perr_edma_fifo2", 8, 1 },
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{ "perr_edma_fifo1", 7, 1 },
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{ "perr_edma_fifo0", 6, 1 },
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{ "perr_pd_fifo3", 5, 1 },
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{ "perr_pd_fifo2", 4, 1 },
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{ "perr_pd_fifo1", 3, 1 },
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{ "perr_pd_fifo0", 2, 1 },
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{ "perr_ing_ctxt_mifrsp", 1, 1 },
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{ "perr_egr_ctxt_mifrsp", 0, 1 },
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{ "SGE_INT_CAUSE2", 0x1030, 0 },
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{ "perr_dbp_hint_fl_fifo", 24, 1 },
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{ "perr_egr_dbp_tx_coal", 23, 1 },
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{ "perr_dbp_fl_fifo", 22, 1 },
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{ "deq_ll_perr", 21, 1 },
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{ "enq_perr", 20, 1 },
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{ "deq_out_perr", 19, 1 },
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{ "buf_perr", 18, 1 },
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{ "perr_conm_sram", 14, 1 },
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{ "perr_isw_idma0_fifo", 12, 1 },
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{ "perr_isw_idma1_fifo", 11, 1 },
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{ "perr_isw_dbp_fifo", 10, 1 },
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{ "perr_isw_gts_fifo", 9, 1 },
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{ "perr_itp_evr", 8, 1 },
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{ "perr_flm_cntxmem", 7, 1 },
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{ "perr_flm_l1Cache", 6, 1 },
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{ "perr_dbp_hint_fifo", 5, 1 },
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{ "perr_dbp_hp_fifo", 4, 1 },
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{ "perr_db_fifo", 3, 1 },
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{ "perr_ing_ctxt_cache", 2, 1 },
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{ "perr_egr_ctxt_cache", 1, 1 },
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{ "perr_base_size", 0, 1 },
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{ "SGE_INT_ENABLE2", 0x1034, 0 },
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{ "perr_dbp_hint_fl_fifo", 24, 1 },
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{ "perr_egr_dbp_tx_coal", 23, 1 },
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{ "perr_dbp_fl_fifo", 22, 1 },
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{ "deq_ll_perr", 21, 1 },
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{ "enq_perr", 20, 1 },
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{ "deq_out_perr", 19, 1 },
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{ "buf_perr", 18, 1 },
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{ "perr_conm_sram", 14, 1 },
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{ "perr_isw_idma0_fifo", 12, 1 },
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{ "perr_isw_idma1_fifo", 11, 1 },
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{ "perr_isw_dbp_fifo", 10, 1 },
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{ "perr_isw_gts_fifo", 9, 1 },
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{ "perr_itp_evr", 8, 1 },
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{ "perr_flm_cntxmem", 7, 1 },
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{ "perr_flm_l1Cache", 6, 1 },
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{ "perr_dbp_hint_fifo", 5, 1 },
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{ "perr_dbp_hp_fifo", 4, 1 },
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{ "perr_db_fifo", 3, 1 },
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{ "perr_ing_ctxt_cache", 2, 1 },
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{ "perr_egr_ctxt_cache", 1, 1 },
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{ "perr_base_size", 0, 1 },
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{ "SGE_PERR_ENABLE2", 0x1038, 0 },
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{ "perr_dbp_hint_fl_fifo", 24, 1 },
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{ "perr_egr_dbp_tx_coal", 23, 1 },
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{ "perr_dbp_fl_fifo", 22, 1 },
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{ "deq_ll_perr", 21, 1 },
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{ "enq_perr", 20, 1 },
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{ "deq_out_perr", 19, 1 },
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{ "buf_perr", 18, 1 },
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{ "perr_conm_sram", 14, 1 },
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{ "perr_isw_idma0_fifo", 12, 1 },
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{ "perr_isw_idma1_fifo", 11, 1 },
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{ "perr_isw_dbp_fifo", 10, 1 },
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{ "perr_isw_gts_fifo", 9, 1 },
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{ "perr_itp_evr", 8, 1 },
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{ "perr_flm_cntxmem", 7, 1 },
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{ "perr_flm_l1Cache", 6, 1 },
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{ "perr_dbp_hint_fifo", 5, 1 },
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{ "perr_dbp_hp_fifo", 4, 1 },
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{ "perr_dbp_lp_fifo", 3, 1 },
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{ "perr_ing_ctxt_cache", 2, 1 },
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{ "perr_egr_ctxt_cache", 1, 1 },
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{ "perr_base_size", 0, 1 },
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{ "SGE_INT_CAUSE3", 0x103c, 0 },
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{ "err_flm_dbp", 31, 1 },
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{ "err_flm_idma1", 30, 1 },
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{ "err_flm_idma0", 29, 1 },
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{ "err_flm_hint", 28, 1 },
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{ "err_pcie_error3", 27, 1 },
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{ "err_pcie_error2", 26, 1 },
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{ "err_pcie_error1", 25, 1 },
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{ "err_pcie_error0", 24, 1 },
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{ "err_timer_above_max_qid", 23, 1 },
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{ "err_cpl_exceed_iqe_size", 22, 1 },
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{ "err_invalid_cidx_inc", 21, 1 },
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{ "err_itp_time_paused", 20, 1 },
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{ "err_cpl_opcode_0", 19, 1 },
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{ "err_dropped_db", 18, 1 },
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{ "err_data_cpl_on_high_qid1", 17, 1 },
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{ "err_data_cpl_on_high_qid0", 16, 1 },
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{ "err_bad_db_pidx3", 15, 1 },
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{ "err_bad_db_pidx2", 14, 1 },
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{ "err_bad_db_pidx1", 13, 1 },
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{ "err_bad_db_pidx0", 12, 1 },
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{ "err_ing_pcie_chan", 11, 1 },
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{ "err_ing_ctxt_prio", 10, 1 },
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{ "err_egr_ctxt_prio", 9, 1 },
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{ "dbp_tbuf_full", 8, 1 },
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{ "fatal_wre_len", 7, 1 },
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{ "reg_address_err", 6, 1 },
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{ "ingress_size_err", 5, 1 },
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{ "egress_size_err", 4, 1 },
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{ "err_inv_ctxt3", 3, 1 },
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{ "err_inv_ctxt2", 2, 1 },
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{ "err_inv_ctxt1", 1, 1 },
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{ "err_inv_ctxt0", 0, 1 },
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{ "SGE_INT_ENABLE3", 0x1040, 0 },
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{ "err_flm_dbp", 31, 1 },
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{ "err_flm_idma1", 30, 1 },
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{ "err_flm_idma0", 29, 1 },
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{ "err_flm_hint", 28, 1 },
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{ "err_pcie_error3", 27, 1 },
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{ "err_pcie_error2", 26, 1 },
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{ "err_pcie_error1", 25, 1 },
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{ "err_pcie_error0", 24, 1 },
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{ "err_timer_above_max_qid", 23, 1 },
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{ "err_cpl_exceed_iqe_size", 22, 1 },
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{ "err_invalid_cidx_inc", 21, 1 },
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{ "err_itp_time_paused", 20, 1 },
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{ "err_cpl_opcode_0", 19, 1 },
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{ "err_dropped_db", 18, 1 },
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{ "err_data_cpl_on_high_qid1", 17, 1 },
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{ "err_data_cpl_on_high_qid0", 16, 1 },
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{ "err_bad_db_pidx3", 15, 1 },
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{ "err_bad_db_pidx2", 14, 1 },
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{ "err_bad_db_pidx1", 13, 1 },
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{ "err_bad_db_pidx0", 12, 1 },
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{ "err_ing_pcie_chan", 11, 1 },
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{ "err_ing_ctxt_prio", 10, 1 },
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{ "err_egr_ctxt_prio", 9, 1 },
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{ "dbp_tbuf_full", 8, 1 },
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{ "fatal_wre_len", 7, 1 },
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{ "reg_address_err", 6, 1 },
|
|
{ "ingress_size_err", 5, 1 },
|
|
{ "egress_size_err", 4, 1 },
|
|
{ "err_inv_ctxt3", 3, 1 },
|
|
{ "err_inv_ctxt2", 2, 1 },
|
|
{ "err_inv_ctxt1", 1, 1 },
|
|
{ "err_inv_ctxt0", 0, 1 },
|
|
{ "SGE_FL_BUFFER_SIZE0", 0x1044, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE1", 0x1048, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE2", 0x104c, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE3", 0x1050, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE4", 0x1054, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE5", 0x1058, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE6", 0x105c, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE7", 0x1060, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE8", 0x1064, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE9", 0x1068, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE10", 0x106c, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE11", 0x1070, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE12", 0x1074, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE13", 0x1078, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE14", 0x107c, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_FL_BUFFER_SIZE15", 0x1080, 0 },
|
|
{ "Size", 4, 20 },
|
|
{ "SGE_DBQ_CTXT_BADDR", 0x1084, 0 },
|
|
{ "BaseAddr", 3, 29 },
|
|
{ "SGE_IMSG_CTXT_BADDR", 0x1088, 0 },
|
|
{ "BaseAddr", 3, 29 },
|
|
{ "SGE_FLM_CACHE_BADDR", 0x108c, 0 },
|
|
{ "BaseAddr", 3, 29 },
|
|
{ "SGE_FLM_CFG", 0x1090, 0 },
|
|
{ "OpMode", 26, 6 },
|
|
{ "NullPtr", 20, 4 },
|
|
{ "NullPtrEn", 19, 1 },
|
|
{ "NoHdr", 18, 1 },
|
|
{ "CachePtrCnt", 16, 2 },
|
|
{ "EDRAMPtrCnt", 14, 2 },
|
|
{ "HdrStartFLQ", 11, 3 },
|
|
{ "FetchThresh", 6, 5 },
|
|
{ "CreditCnt", 4, 2 },
|
|
{ "CreditCntPacking", 2, 2 },
|
|
{ "NoEDRAM", 0, 1 },
|
|
{ "SGE_CONM_CTRL", 0x1094, 0 },
|
|
{ "EgrThresholdPacking", 16, 8 },
|
|
{ "EgrThreshold", 8, 8 },
|
|
{ "IngThreshold", 2, 6 },
|
|
{ "SGE_TIMESTAMP_LO", 0x1098, 0 },
|
|
{ "SGE_TIMESTAMP_HI", 0x109c, 0 },
|
|
{ "Opcode", 28, 2 },
|
|
{ "Value", 0, 28 },
|
|
{ "SGE_INGRESS_RX_THRESHOLD", 0x10a0, 0 },
|
|
{ "Threshold_0", 24, 6 },
|
|
{ "Threshold_1", 16, 6 },
|
|
{ "Threshold_2", 8, 6 },
|
|
{ "Threshold_3", 0, 6 },
|
|
{ "SGE_DBFIFO_STATUS", 0x10a4, 0 },
|
|
{ "vfifo_cnt", 15, 17 },
|
|
{ "coal_ctl_fifo_cnt", 8, 6 },
|
|
{ "merge_fifo_cnt", 0, 6 },
|
|
{ "SGE_DOORBELL_CONTROL", 0x10a8, 0 },
|
|
{ "HintDepthCtl", 27, 5 },
|
|
{ "NoCoalesce", 26, 1 },
|
|
{ "HP_Weight", 24, 2 },
|
|
{ "HP_Disable", 23, 1 },
|
|
{ "ForceUserDBtoLP", 22, 1 },
|
|
{ "ForceVFPF0DBtoLP", 21, 1 },
|
|
{ "ForceVFPF1DBtoLP", 20, 1 },
|
|
{ "ForceVFPF2DBtoLP", 19, 1 },
|
|
{ "ForceVFPF3DBtoLP", 18, 1 },
|
|
{ "ForceVFPF4DBtoLP", 17, 1 },
|
|
{ "ForceVFPF5DBtoLP", 16, 1 },
|
|
{ "ForceVFPF6DBtoLP", 15, 1 },
|
|
{ "ForceVFPF7DBtoLP", 14, 1 },
|
|
{ "Enable_Drop", 13, 1 },
|
|
{ "Drop_Timeout", 7, 6 },
|
|
{ "InvOnDBSync", 6, 1 },
|
|
{ "InvOnGTSSync", 5, 1 },
|
|
{ "db_dbg_en", 4, 1 },
|
|
{ "gts_dbg_timer_reg", 1, 3 },
|
|
{ "gts_dbg_en", 0, 1 },
|
|
{ "SGE_ITP_CONTROL", 0x10b4, 0 },
|
|
{ "TScale", 28, 4 },
|
|
{ "Critical_Time", 10, 15 },
|
|
{ "LL_Empty", 4, 6 },
|
|
{ "LL_Read_Wait_Disable", 0, 1 },
|
|
{ "SGE_TIMER_VALUE_0_AND_1", 0x10b8, 0 },
|
|
{ "TimerValue0", 16, 16 },
|
|
{ "TimerValue1", 0, 16 },
|
|
{ "SGE_TIMER_VALUE_2_AND_3", 0x10bc, 0 },
|
|
{ "TimerValue2", 16, 16 },
|
|
{ "TimerValue3", 0, 16 },
|
|
{ "SGE_TIMER_VALUE_4_AND_5", 0x10c0, 0 },
|
|
{ "TimerValue4", 16, 16 },
|
|
{ "TimerValue5", 0, 16 },
|
|
{ "SGE_GK_CONTROL", 0x10c4, 0 },
|
|
{ "en_flm_fifth", 29, 1 },
|
|
{ "fl_prog_thresh", 20, 9 },
|
|
{ "coal_all_thread", 19, 1 },
|
|
{ "en_pshb", 18, 1 },
|
|
{ "en_db_fifth", 17, 1 },
|
|
{ "db_prog_thresh", 8, 9 },
|
|
{ "100ns_timer", 0, 8 },
|
|
{ "SGE_GK_CONTROL2", 0x10c8, 0 },
|
|
{ "dbq_timer_tick", 16, 16 },
|
|
{ "fl_merge_cnt_thresh", 8, 4 },
|
|
{ "merge_cnt_thresh", 0, 6 },
|
|
{ "SGE_DEBUG_INDEX", 0x10cc, 0 },
|
|
{ "SGE_DEBUG_DATA_HIGH", 0x10d0, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW", 0x10d4, 0 },
|
|
{ "SGE_REVISION", 0x10d8, 0 },
|
|
{ "SGE_INT_CAUSE4", 0x10dc, 0 },
|
|
{ "err_ishift_ur1", 31, 1 },
|
|
{ "err_ishift_ur0", 30, 1 },
|
|
{ "bar2_egress_len_or_addr_err", 29, 1 },
|
|
{ "err_cpl_exceed_max_iqe_size1", 28, 1 },
|
|
{ "err_cpl_exceed_max_iqe_size0", 27, 1 },
|
|
{ "err_wr_len_too_large3", 26, 1 },
|
|
{ "err_wr_len_too_large2", 25, 1 },
|
|
{ "err_wr_len_too_large1", 24, 1 },
|
|
{ "err_wr_len_too_large0", 23, 1 },
|
|
{ "err_large_minfetch_with_txcoal3", 22, 1 },
|
|
{ "err_large_minfetch_with_txcoal2", 21, 1 },
|
|
{ "err_large_minfetch_with_txcoal1", 20, 1 },
|
|
{ "err_large_minfetch_with_txcoal0", 19, 1 },
|
|
{ "coal_with_hp_disable_err", 18, 1 },
|
|
{ "bar2_egress_coal0_err", 17, 1 },
|
|
{ "bar2_egress_size_err", 16, 1 },
|
|
{ "flm_pc_rsp_err", 15, 1 },
|
|
{ "err_th3_max_fetch", 14, 1 },
|
|
{ "err_th2_max_fetch", 13, 1 },
|
|
{ "err_th1_max_fetch", 12, 1 },
|
|
{ "err_th0_max_fetch", 11, 1 },
|
|
{ "err_rx_cpl_packet_size1", 10, 1 },
|
|
{ "err_rx_cpl_packet_size0", 9, 1 },
|
|
{ "err_bad_upfl_inc_credit3", 8, 1 },
|
|
{ "err_bad_upfl_inc_credit2", 7, 1 },
|
|
{ "err_bad_upfl_inc_credit1", 6, 1 },
|
|
{ "err_bad_upfl_inc_credit0", 5, 1 },
|
|
{ "err_physaddr_len0_idma1", 4, 1 },
|
|
{ "err_physaddr_len0_idma0", 3, 1 },
|
|
{ "err_flm_invalid_pkt_drop1", 2, 1 },
|
|
{ "err_flm_invalid_pkt_drop0", 1, 1 },
|
|
{ "err_unexpected_timer", 0, 1 },
|
|
{ "SGE_INT_ENABLE4", 0x10e0, 0 },
|
|
{ "err_ishift_ur1", 31, 1 },
|
|
{ "err_ishift_ur0", 30, 1 },
|
|
{ "bar2_egress_len_or_addr_err", 29, 1 },
|
|
{ "err_cpl_exceed_max_iqe_size1", 28, 1 },
|
|
{ "err_cpl_exceed_max_iqe_size0", 27, 1 },
|
|
{ "err_wr_len_too_large3", 26, 1 },
|
|
{ "err_wr_len_too_large2", 25, 1 },
|
|
{ "err_wr_len_too_large1", 24, 1 },
|
|
{ "err_wr_len_too_large0", 23, 1 },
|
|
{ "err_large_minfetch_with_txcoal3", 22, 1 },
|
|
{ "err_large_minfetch_with_txcoal2", 21, 1 },
|
|
{ "err_large_minfetch_with_txcoal1", 20, 1 },
|
|
{ "err_large_minfetch_with_txcoal0", 19, 1 },
|
|
{ "coal_with_hp_disable_err", 18, 1 },
|
|
{ "bar2_egress_coal0_err", 17, 1 },
|
|
{ "bar2_egress_size_err", 16, 1 },
|
|
{ "flm_pc_rsp_err", 15, 1 },
|
|
{ "err_th3_max_fetch", 14, 1 },
|
|
{ "err_th2_max_fetch", 13, 1 },
|
|
{ "err_th1_max_fetch", 12, 1 },
|
|
{ "err_th0_max_fetch", 11, 1 },
|
|
{ "err_rx_cpl_packet_size1", 10, 1 },
|
|
{ "err_rx_cpl_packet_size0", 9, 1 },
|
|
{ "err_bad_upfl_inc_credit3", 8, 1 },
|
|
{ "err_bad_upfl_inc_credit2", 7, 1 },
|
|
{ "err_bad_upfl_inc_credit1", 6, 1 },
|
|
{ "err_bad_upfl_inc_credit0", 5, 1 },
|
|
{ "err_physaddr_len0_idma1", 4, 1 },
|
|
{ "err_physaddr_len0_idma0", 3, 1 },
|
|
{ "err_flm_invalid_pkt_drop1", 2, 1 },
|
|
{ "err_flm_invalid_pkt_drop0", 1, 1 },
|
|
{ "err_unexpected_timer", 0, 1 },
|
|
{ "SGE_STAT_TOTAL", 0x10e4, 0 },
|
|
{ "SGE_STAT_MATCH", 0x10e8, 0 },
|
|
{ "SGE_STAT_CFG", 0x10ec, 0 },
|
|
{ "StatSource", 9, 4 },
|
|
{ "ITPOpMode", 8, 1 },
|
|
{ "EgrCtxtOpMode", 6, 2 },
|
|
{ "IngCtxtOpMode", 4, 2 },
|
|
{ "StatMode", 0, 4 },
|
|
{ "SGE_HINT_CFG", 0x10f0, 0 },
|
|
{ "uPCutoffThreshLp", 12, 11 },
|
|
{ "HintsAllowedNoHdr", 6, 6 },
|
|
{ "HintsAllowedHdr", 0, 6 },
|
|
{ "SGE_INGRESS_QUEUES_PER_PAGE_PF", 0x10f4, 0 },
|
|
{ "QueuesPerPagePF7", 28, 4 },
|
|
{ "QueuesPerPagePF6", 24, 4 },
|
|
{ "QueuesPerPagePF5", 20, 4 },
|
|
{ "QueuesPerPagePF4", 16, 4 },
|
|
{ "QueuesPerPagePF3", 12, 4 },
|
|
{ "QueuesPerPagePF2", 8, 4 },
|
|
{ "QueuesPerPagePF1", 4, 4 },
|
|
{ "QueuesPerPagePF0", 0, 4 },
|
|
{ "SGE_INGRESS_QUEUES_PER_PAGE_VF", 0x10f8, 0 },
|
|
{ "QueuesPerPageVFPF7", 28, 4 },
|
|
{ "QueuesPerPageVFPF6", 24, 4 },
|
|
{ "QueuesPerPageVFPF5", 20, 4 },
|
|
{ "QueuesPerPageVFPF4", 16, 4 },
|
|
{ "QueuesPerPageVFPF3", 12, 4 },
|
|
{ "QueuesPerPageVFPF2", 8, 4 },
|
|
{ "QueuesPerPageVFPF1", 4, 4 },
|
|
{ "QueuesPerPageVFPF0", 0, 4 },
|
|
{ "SGE_ERROR_STATS", 0x1100, 0 },
|
|
{ "Cause_Register", 24, 3 },
|
|
{ "Cause_Bit", 19, 5 },
|
|
{ "Uncaptured_Error", 18, 1 },
|
|
{ "Error_QID_Valid", 17, 1 },
|
|
{ "Error_QID", 0, 17 },
|
|
{ "SGE_IDMA0_DROP_CNT", 0x1104, 0 },
|
|
{ "SGE_IDMA1_DROP_CNT", 0x1108, 0 },
|
|
{ "SGE_INT_CAUSE5", 0x110c, 0 },
|
|
{ "err_T_RxCRC", 31, 1 },
|
|
{ "perr_MC_RspData", 30, 1 },
|
|
{ "perr_PC_RspData", 29, 1 },
|
|
{ "perr_PD_RdRspData", 28, 1 },
|
|
{ "perr_U_RxData", 27, 1 },
|
|
{ "perr_UD_RxData", 26, 1 },
|
|
{ "perr_uP_Data", 25, 1 },
|
|
{ "perr_CIM2SGE_RxData", 24, 1 },
|
|
{ "perr_hint_delay_fifo1", 23, 1 },
|
|
{ "perr_hint_delay_fifo0", 22, 1 },
|
|
{ "perr_imsg_pd_fifo", 21, 1 },
|
|
{ "perr_ulptx_fifo1", 20, 1 },
|
|
{ "perr_ulptx_fifo0", 19, 1 },
|
|
{ "perr_idma2imsg_fifo1", 18, 1 },
|
|
{ "perr_idma2imsg_fifo0", 17, 1 },
|
|
{ "perr_pointer_data_fifo0", 16, 1 },
|
|
{ "perr_pointer_data_fifo1", 15, 1 },
|
|
{ "perr_pointer_hdr_fifo0", 14, 1 },
|
|
{ "perr_pointer_hdr_fifo1", 13, 1 },
|
|
{ "perr_payload_fifo0", 12, 1 },
|
|
{ "perr_payload_fifo1", 11, 1 },
|
|
{ "perr_edma_input_fifo3", 10, 1 },
|
|
{ "perr_edma_input_fifo2", 9, 1 },
|
|
{ "perr_edma_input_fifo1", 8, 1 },
|
|
{ "perr_edma_input_fifo0", 7, 1 },
|
|
{ "perr_mgt_bar2_fifo", 6, 1 },
|
|
{ "perr_headersplit_fifo1", 5, 1 },
|
|
{ "perr_headersplit_fifo0", 4, 1 },
|
|
{ "perr_cim_fifo1", 3, 1 },
|
|
{ "perr_cim_fifo0", 2, 1 },
|
|
{ "perr_idma_switch_output_fifo1", 1, 1 },
|
|
{ "perr_idma_switch_output_fifo0", 0, 1 },
|
|
{ "SGE_INT_ENABLE5", 0x1110, 0 },
|
|
{ "err_T_RxCRC", 31, 1 },
|
|
{ "perr_MC_RspData", 30, 1 },
|
|
{ "perr_PC_RspData", 29, 1 },
|
|
{ "perr_PD_RdRspData", 28, 1 },
|
|
{ "perr_U_RxData", 27, 1 },
|
|
{ "perr_UD_RxData", 26, 1 },
|
|
{ "perr_uP_Data", 25, 1 },
|
|
{ "perr_CIM2SGE_RxData", 24, 1 },
|
|
{ "perr_hint_delay_fifo1", 23, 1 },
|
|
{ "perr_hint_delay_fifo0", 22, 1 },
|
|
{ "perr_imsg_pd_fifo", 21, 1 },
|
|
{ "perr_ulptx_fifo1", 20, 1 },
|
|
{ "perr_ulptx_fifo0", 19, 1 },
|
|
{ "perr_idma2imsg_fifo1", 18, 1 },
|
|
{ "perr_idma2imsg_fifo0", 17, 1 },
|
|
{ "perr_pointer_data_fifo0", 16, 1 },
|
|
{ "perr_pointer_data_fifo1", 15, 1 },
|
|
{ "perr_pointer_hdr_fifo0", 14, 1 },
|
|
{ "perr_pointer_hdr_fifo1", 13, 1 },
|
|
{ "perr_payload_fifo0", 12, 1 },
|
|
{ "perr_payload_fifo1", 11, 1 },
|
|
{ "perr_edma_input_fifo3", 10, 1 },
|
|
{ "perr_edma_input_fifo2", 9, 1 },
|
|
{ "perr_edma_input_fifo1", 8, 1 },
|
|
{ "perr_edma_input_fifo0", 7, 1 },
|
|
{ "perr_mgt_bar2_fifo", 6, 1 },
|
|
{ "perr_headersplit_fifo1", 5, 1 },
|
|
{ "perr_headersplit_fifo0", 4, 1 },
|
|
{ "perr_cim_fifo1", 3, 1 },
|
|
{ "perr_cim_fifo0", 2, 1 },
|
|
{ "perr_idma_switch_output_fifo1", 1, 1 },
|
|
{ "perr_idma_switch_output_fifo0", 0, 1 },
|
|
{ "SGE_PERR_ENABLE5", 0x1114, 0 },
|
|
{ "err_T_RxCRC", 31, 1 },
|
|
{ "perr_MC_RspData", 30, 1 },
|
|
{ "perr_PC_RspData", 29, 1 },
|
|
{ "perr_PD_RdRspData", 28, 1 },
|
|
{ "perr_U_RxData", 27, 1 },
|
|
{ "perr_UD_RxData", 26, 1 },
|
|
{ "perr_uP_Data", 25, 1 },
|
|
{ "perr_CIM2SGE_RxData", 24, 1 },
|
|
{ "perr_hint_delay_fifo1", 23, 1 },
|
|
{ "perr_hint_delay_fifo0", 22, 1 },
|
|
{ "perr_imsg_pd_fifo", 21, 1 },
|
|
{ "perr_ulptx_fifo1", 20, 1 },
|
|
{ "perr_ulptx_fifo0", 19, 1 },
|
|
{ "perr_idma2imsg_fifo1", 18, 1 },
|
|
{ "perr_idma2imsg_fifo0", 17, 1 },
|
|
{ "perr_pointer_data_fifo0", 16, 1 },
|
|
{ "perr_pointer_data_fifo1", 15, 1 },
|
|
{ "perr_pointer_hdr_fifo0", 14, 1 },
|
|
{ "perr_pointer_hdr_fifo1", 13, 1 },
|
|
{ "perr_payload_fifo0", 12, 1 },
|
|
{ "perr_payload_fifo1", 11, 1 },
|
|
{ "perr_edma_input_fifo3", 10, 1 },
|
|
{ "perr_edma_input_fifo2", 9, 1 },
|
|
{ "perr_edma_input_fifo1", 8, 1 },
|
|
{ "perr_edma_input_fifo0", 7, 1 },
|
|
{ "perr_mgt_bar2_fifo", 6, 1 },
|
|
{ "perr_headersplit_fifo1", 5, 1 },
|
|
{ "perr_headersplit_fifo0", 4, 1 },
|
|
{ "perr_cim_fifo1", 3, 1 },
|
|
{ "perr_cim_fifo0", 2, 1 },
|
|
{ "perr_idma_switch_output_fifo1", 1, 1 },
|
|
{ "perr_idma_switch_output_fifo0", 0, 1 },
|
|
{ "SGE_FETCH_BURST_MAX_0_AND_1", 0x111c, 0 },
|
|
{ "FetchBurstMax0", 16, 10 },
|
|
{ "FetchBurstMax1", 0, 10 },
|
|
{ "SGE_FETCH_BURST_MAX_2_AND_3", 0x1120, 0 },
|
|
{ "FetchBurstMax2", 16, 10 },
|
|
{ "FetchBurstMax3", 0, 10 },
|
|
{ "SGE_CONTROL2", 0x1124, 0 },
|
|
{ "uPFLCutoffDis", 21, 1 },
|
|
{ "RxCplSizeAutocorrect", 20, 1 },
|
|
{ "IdmaArbRoundRobin", 19, 1 },
|
|
{ "IngPackBoundary", 16, 3 },
|
|
{ "CGEN_Egress_Context", 15, 1 },
|
|
{ "CGEN_Ingress_Context", 14, 1 },
|
|
{ "CGEN_IDMA", 13, 1 },
|
|
{ "CGEN_DBP", 12, 1 },
|
|
{ "CGEN_EDMA", 11, 1 },
|
|
{ "VFIFO_Enable", 10, 1 },
|
|
{ "FLM_Reschedule_Mode", 9, 1 },
|
|
{ "HintDepthCtlFL", 4, 5 },
|
|
{ "Force_Ordering", 3, 1 },
|
|
{ "TX_Coalesce_Size", 2, 1 },
|
|
{ "Coal_Strict_CIM_Pri", 1, 1 },
|
|
{ "TX_Coalesce_Pri", 0, 1 },
|
|
{ "SGE_INT_CAUSE6", 0x1128, 0 },
|
|
{ "err_db_sync", 21, 1 },
|
|
{ "err_gts_sync", 20, 1 },
|
|
{ "fatal_large_coal", 19, 1 },
|
|
{ "pl_bar2_frm_err", 18, 1 },
|
|
{ "silent_drop_tx_coal", 17, 1 },
|
|
{ "err_inv_ctxt4", 16, 1 },
|
|
{ "err_bad_db_pidx4", 15, 1 },
|
|
{ "err_bad_upfl_inc_credit4", 14, 1 },
|
|
{ "fatal_tag_mismatch", 13, 1 },
|
|
{ "fatal_enq_ctl_rdy", 12, 1 },
|
|
{ "err_pc_rsp_len3", 11, 1 },
|
|
{ "err_pc_rsp_len2", 10, 1 },
|
|
{ "err_pc_rsp_len1", 9, 1 },
|
|
{ "err_pc_rsp_len0", 8, 1 },
|
|
{ "fatal_enq2ll_vld", 7, 1 },
|
|
{ "fatal_ll_empty", 6, 1 },
|
|
{ "fatal_off_wdenq", 5, 1 },
|
|
{ "fatal_deq_drdy", 3, 2 },
|
|
{ "fatal_outp_drdy", 1, 2 },
|
|
{ "fatal_deq", 0, 1 },
|
|
{ "SGE_INT_ENABLE6", 0x112c, 0 },
|
|
{ "err_db_sync", 21, 1 },
|
|
{ "err_gts_sync", 20, 1 },
|
|
{ "fatal_large_coal", 19, 1 },
|
|
{ "pl_bar2_frm_err", 18, 1 },
|
|
{ "silent_drop_tx_coal", 17, 1 },
|
|
{ "err_inv_ctxt4", 16, 1 },
|
|
{ "err_bad_db_pidx4", 15, 1 },
|
|
{ "err_bad_upfl_inc_credit4", 14, 1 },
|
|
{ "fatal_tag_mismatch", 13, 1 },
|
|
{ "fatal_enq_ctl_rdy", 12, 1 },
|
|
{ "err_pc_rsp_len3", 11, 1 },
|
|
{ "err_pc_rsp_len2", 10, 1 },
|
|
{ "err_pc_rsp_len1", 9, 1 },
|
|
{ "err_pc_rsp_len0", 8, 1 },
|
|
{ "fatal_enq2ll_vld", 7, 1 },
|
|
{ "fatal_ll_empty", 6, 1 },
|
|
{ "fatal_off_wdenq", 5, 1 },
|
|
{ "fatal_deq_drdy", 3, 2 },
|
|
{ "fatal_outp_drdy", 1, 2 },
|
|
{ "fatal_deq", 0, 1 },
|
|
{ "SGE_DBVFIFO_BADDR", 0x1138, 0 },
|
|
{ "BaseAddr", 3, 29 },
|
|
{ "SGE_DBVFIFO_SIZE", 0x113c, 0 },
|
|
{ "SGE_CHANGESET", 0x1144, 0 },
|
|
{ "SGE_PC_RSP_ERROR", 0x1148, 0 },
|
|
{ "SGE_TBUF_CONTROL", 0x114c, 0 },
|
|
{ "DbpTbufRsv1", 9, 9 },
|
|
{ "DbpTbufRsv0", 0, 9 },
|
|
{ "SGE_PC0_REQ_BIST_CMD", 0x1180, 0 },
|
|
{ "SGE_PC0_REQ_BIST_ERROR_CNT", 0x1184, 0 },
|
|
{ "SGE_PC1_REQ_BIST_CMD", 0x1190, 0 },
|
|
{ "SGE_PC1_REQ_BIST_ERROR_CNT", 0x1194, 0 },
|
|
{ "SGE_PC0_RSP_BIST_CMD", 0x11a0, 0 },
|
|
{ "SGE_PC0_RSP_BIST_ERROR_CNT", 0x11a4, 0 },
|
|
{ "SGE_PC1_RSP_BIST_CMD", 0x11b0, 0 },
|
|
{ "SGE_PC1_RSP_BIST_ERROR_CNT", 0x11b4, 0 },
|
|
{ "SGE_DBQ_TIMER_THRESH0", 0x11b8, 0 },
|
|
{ "TxTimeTh3", 24, 6 },
|
|
{ "TxTimeTh2", 16, 6 },
|
|
{ "TxTimeTh1", 8, 6 },
|
|
{ "TxTimeTh0", 0, 6 },
|
|
{ "SGE_DBQ_TIMER_THRESH1", 0x11bc, 0 },
|
|
{ "TxTimeTh7", 24, 6 },
|
|
{ "TxTimeTh6", 16, 6 },
|
|
{ "TxTimeTh5", 8, 6 },
|
|
{ "TxTimeTh4", 0, 6 },
|
|
{ "SGE_DBQ_TIMER_CONFIG", 0x11c0, 0 },
|
|
{ "SGE_DBQ_TIMER_DBG", 0x11c4, 0 },
|
|
{ "dbq_timer_cmd", 31, 1 },
|
|
{ "dbq_timer_index", 24, 6 },
|
|
{ "dbq_timer_qcnt", 0, 17 },
|
|
{ "SGE_CTXT_CMD", 0x11fc, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Opcode", 28, 2 },
|
|
{ "CtxtType", 24, 2 },
|
|
{ "QID", 0, 17 },
|
|
{ "SGE_CTXT_DATA0", 0x1200, 0 },
|
|
{ "SGE_CTXT_DATA1", 0x1204, 0 },
|
|
{ "SGE_CTXT_DATA2", 0x1208, 0 },
|
|
{ "SGE_CTXT_DATA3", 0x120c, 0 },
|
|
{ "SGE_CTXT_DATA4", 0x1210, 0 },
|
|
{ "SGE_CTXT_DATA5", 0x1214, 0 },
|
|
{ "SGE_CTXT_DATA6", 0x1218, 0 },
|
|
{ "SGE_CTXT_DATA7", 0x121c, 0 },
|
|
{ "SGE_CTXT_MASK0", 0x1220, 0 },
|
|
{ "SGE_CTXT_MASK1", 0x1224, 0 },
|
|
{ "SGE_CTXT_MASK2", 0x1228, 0 },
|
|
{ "SGE_CTXT_MASK3", 0x122c, 0 },
|
|
{ "SGE_CTXT_MASK4", 0x1230, 0 },
|
|
{ "SGE_CTXT_MASK5", 0x1234, 0 },
|
|
{ "SGE_CTXT_MASK6", 0x1238, 0 },
|
|
{ "SGE_CTXT_MASK7", 0x123c, 0 },
|
|
{ "SGE_QBASE_MAP0", 0x1240, 0 },
|
|
{ "Egress0_Size", 24, 5 },
|
|
{ "Egress1_Size", 16, 5 },
|
|
{ "Ingress0_Size", 8, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QBASE_MAP1", 0x1244, 0 },
|
|
{ "SGE_QBASE_MAP2", 0x1248, 0 },
|
|
{ "SGE_QBASE_MAP3", 0x124c, 0 },
|
|
{ "Ingress1_Base", 16, 16 },
|
|
{ "Ingress0_Base", 0, 16 },
|
|
{ "SGE_QBASE_INDEX", 0x1250, 0 },
|
|
{ "SGE_CONM_CTRL2", 0x1254, 0 },
|
|
{ "FlmThreshPack", 8, 7 },
|
|
{ "FlmThresh", 0, 7 },
|
|
{ "SGE_DEBUG_CONM", 0x1258, 0 },
|
|
{ "mps_ch_cng", 16, 16 },
|
|
{ "tp_ch_cng", 14, 2 },
|
|
{ "st_cong", 12, 2 },
|
|
{ "last_xoff", 10, 1 },
|
|
{ "last_qid", 0, 10 },
|
|
{ "SGE_DBG_QUEUE_STAT0_CTRL", 0x125c, 0 },
|
|
{ "imsg_gts_sel", 18, 1 },
|
|
{ "mgt_sel", 17, 1 },
|
|
{ "db_gts_qid", 0, 17 },
|
|
{ "SGE_DBG_QUEUE_STAT1_CTRL", 0x1260, 0 },
|
|
{ "imsg_gts_sel", 18, 1 },
|
|
{ "mgt_sel", 17, 1 },
|
|
{ "db_gts_qid", 0, 17 },
|
|
{ "SGE_DBG_QUEUE_STAT0", 0x1264, 0 },
|
|
{ "SGE_DBG_QUEUE_STAT1", 0x1268, 0 },
|
|
{ "SGE_DBG_BAR2_PKT_CNT", 0x126c, 0 },
|
|
{ "SGE_DBG_DB_PKT_CNT", 0x1270, 0 },
|
|
{ "SGE_DBG_GTS_PKT_CNT", 0x1274, 0 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_0", 0x1280, 0 },
|
|
{ "debug_bar2_sop_cnt", 28, 4 },
|
|
{ "debug_bar2_eop_cnt", 24, 4 },
|
|
{ "debug_uP_SOP_cnt", 20, 4 },
|
|
{ "debug_uP_EOP_cnt", 16, 4 },
|
|
{ "debug_CIM_SOP1_cnt", 12, 4 },
|
|
{ "debug_CIM_EOP1_cnt", 8, 4 },
|
|
{ "debug_CIM_SOP0_cnt", 4, 4 },
|
|
{ "debug_CIM_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_1", 0x1284, 0 },
|
|
{ "debug_T_Rx_SOP1_cnt", 28, 4 },
|
|
{ "debug_T_Rx_EOP1_cnt", 24, 4 },
|
|
{ "debug_T_Rx_SOP0_cnt", 20, 4 },
|
|
{ "debug_T_Rx_EOP0_cnt", 16, 4 },
|
|
{ "debug_U_Rx_SOP1_cnt", 12, 4 },
|
|
{ "debug_U_Rx_EOP1_cnt", 8, 4 },
|
|
{ "debug_U_Rx_SOP0_cnt", 4, 4 },
|
|
{ "debug_U_Rx_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_2", 0x1288, 0 },
|
|
{ "dbg_tbuf_used1", 9, 9 },
|
|
{ "dbg_tbuf_used0", 0, 9 },
|
|
{ "SGE_DEBUG1_DBP_THREAD", 0x128c, 0 },
|
|
{ "wr_deq_cnt", 12, 4 },
|
|
{ "wr_enq_cnt", 8, 4 },
|
|
{ "fl_deq_cnt", 4, 4 },
|
|
{ "fl_enq_cnt", 0, 4 },
|
|
{ "SGE_DEBUG1_DBP_THREAD", 0x1290, 0 },
|
|
{ "wr_deq_cnt", 12, 4 },
|
|
{ "wr_enq_cnt", 8, 4 },
|
|
{ "fl_deq_cnt", 4, 4 },
|
|
{ "fl_enq_cnt", 0, 4 },
|
|
{ "SGE_DEBUG1_DBP_THREAD", 0x1294, 0 },
|
|
{ "wr_deq_cnt", 12, 4 },
|
|
{ "wr_enq_cnt", 8, 4 },
|
|
{ "fl_deq_cnt", 4, 4 },
|
|
{ "fl_enq_cnt", 0, 4 },
|
|
{ "SGE_DEBUG1_DBP_THREAD", 0x1298, 0 },
|
|
{ "wr_deq_cnt", 12, 4 },
|
|
{ "wr_enq_cnt", 8, 4 },
|
|
{ "fl_deq_cnt", 4, 4 },
|
|
{ "fl_enq_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_7", 0x129c, 0 },
|
|
{ "debug_PC_Rsp_SOP_cnt", 28, 4 },
|
|
{ "debug_PC_Rsp_EOP_cnt", 24, 4 },
|
|
{ "debug_PC_Req_SOP_cnt", 20, 4 },
|
|
{ "debug_PC_Req_EOP_cnt", 16, 4 },
|
|
{ "debug_PD_WrReq_SOP1_cnt", 12, 4 },
|
|
{ "debug_PD_WrReq_EOP1_cnt", 8, 4 },
|
|
{ "debug_PD_WrReq_SOP0_cnt", 4, 4 },
|
|
{ "debug_PD_WrReq_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_8", 0x12a0, 0 },
|
|
{ "debug_PL_BAR2_ReqVld", 31, 1 },
|
|
{ "debug_PL_BAR2_ReqFull", 30, 1 },
|
|
{ "GlobalEnable_Off", 29, 1 },
|
|
{ "debug_CIM2SGE_RxAFull_d", 27, 2 },
|
|
{ "debug_CPLSW_CIM_TxAFull_d", 25, 2 },
|
|
{ "debug_uP_Full", 24, 1 },
|
|
{ "debug_M_rd_req_outstanding_PC", 23, 1 },
|
|
{ "debug_M_rd_req_outstanding_VFIFO", 22, 1 },
|
|
{ "debug_M_rd_req_outstanding_IMSG", 21, 1 },
|
|
{ "debug_M_rd_req_outstanding_CMARB", 20, 1 },
|
|
{ "debug_M_rd_req_outstanding_FLM", 19, 1 },
|
|
{ "debug_M_ReqVld", 18, 1 },
|
|
{ "debug_M_ReqRdy", 17, 1 },
|
|
{ "debug_M_RspVld", 16, 1 },
|
|
{ "debug_PD_WrReq_Int3_cnt", 12, 4 },
|
|
{ "debug_PD_WrReq_Int2_cnt", 8, 4 },
|
|
{ "debug_PD_WrReq_Int1_cnt", 4, 4 },
|
|
{ "debug_PD_WrReq_Int0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_9", 0x12a4, 0 },
|
|
{ "debug_CPLSW_TP_Rx_SOP1_cnt", 28, 4 },
|
|
{ "debug_CPLSW_TP_Rx_EOP1_cnt", 24, 4 },
|
|
{ "debug_CPLSW_TP_Rx_SOP0_cnt", 20, 4 },
|
|
{ "debug_CPLSW_TP_Rx_EOP0_cnt", 16, 4 },
|
|
{ "debug_CPLSW_CIM_SOP0_cnt", 4, 4 },
|
|
{ "debug_CPLSW_CIM_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_10", 0x12a8, 0 },
|
|
{ "debug_idma1_s_cpl_flit_remaining", 28, 4 },
|
|
{ "debug_idma1_idma2imsg_cmp_out_srdy", 27, 1 },
|
|
{ "debug_idma1_idma2imsg_cmp_out_rss", 26, 1 },
|
|
{ "debug_idma1_idma2imsg_cmp_out_nocpl", 25, 1 },
|
|
{ "debug_idma1_IDMA2IMSG_Full", 24, 1 },
|
|
{ "debug_idma1_IDMA2IMSG_EOP", 23, 1 },
|
|
{ "debug_idma1_idma2imsg_fifo_in_drdy", 22, 1 },
|
|
{ "debug_idma1_idma2imsg_cmp_in_drdy", 21, 1 },
|
|
{ "debug_idma0_s_cpl_flit_remaining", 17, 4 },
|
|
{ "debug_idma0_idma2imsg_cmp_out_srdy", 16, 1 },
|
|
{ "debug_idma0_idma2imsg_cmp_out_rss", 15, 1 },
|
|
{ "debug_idma0_idma2imsg_cmp_out_nocpl", 14, 1 },
|
|
{ "debug_idma0_IDMA2IMSG_Full", 13, 1 },
|
|
{ "debug_idma0_IDMA2IMSG_EOP", 12, 1 },
|
|
{ "debug_idma0_idma2imsg_cmp_in_drdy", 11, 1 },
|
|
{ "debug_idma0_idma2imsg_fifo_in_drdy", 10, 1 },
|
|
{ "debug_T_RxAFull_d", 8, 2 },
|
|
{ "debug_PD_WrReqAFull_d", 6, 2 },
|
|
{ "debug_PC_RspAFull_d", 5, 1 },
|
|
{ "debug_PC_ReqAFull_d", 4, 1 },
|
|
{ "debug_U_RxAFull_d", 2, 2 },
|
|
{ "debug_CIM_AFull_d", 0, 1 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_11", 0x12ac, 0 },
|
|
{ "debug_flm_idma1_cache_data_active", 24, 1 },
|
|
{ "debug_flm_idma1_cache_hdr_active", 23, 1 },
|
|
{ "debug_flm_idma1_ctxt_data_active", 22, 1 },
|
|
{ "debug_flm_idma1_ctxt_hdr_active", 21, 1 },
|
|
{ "debug_st_flm_idma1_cache", 19, 2 },
|
|
{ "debug_st_flm_idma1_ctxt", 16, 3 },
|
|
{ "debug_flm_idma0_cache_data_active", 8, 1 },
|
|
{ "debug_flm_idma0_cache_hdr_active", 7, 1 },
|
|
{ "debug_flm_idma0_ctxt_data_active", 6, 1 },
|
|
{ "debug_flm_idma0_ctxt_hdr_active", 5, 1 },
|
|
{ "debug_st_flm_idma0_cache", 3, 2 },
|
|
{ "debug_st_flm_idma0_ctxt", 0, 3 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_12", 0x12b0, 0 },
|
|
{ "debug_CPLSW_SOP1_cnt", 28, 4 },
|
|
{ "debug_CPLSW_EOP1_cnt", 24, 4 },
|
|
{ "debug_CPLSW_SOP0_cnt", 20, 4 },
|
|
{ "debug_CPLSW_EOP0_cnt", 16, 4 },
|
|
{ "debug_idma1_ishift_tx_size", 8, 7 },
|
|
{ "debug_idma0_ishift_tx_size", 0, 7 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_13", 0x12b4, 0 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_14", 0x12b8, 0 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_15", 0x12bc, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_0", 0x12c0, 0 },
|
|
{ "debug_st_idma1_flm_req", 29, 3 },
|
|
{ "debug_st_idma0_flm_req", 26, 3 },
|
|
{ "debug_st_imsg_ctxt", 23, 3 },
|
|
{ "debug_st_imsg", 18, 5 },
|
|
{ "debug_st_idma1_ialn", 16, 2 },
|
|
{ "debug_st_idma1_idma2imsg", 15, 1 },
|
|
{ "debug_st_idma1_idma_sm", 9, 6 },
|
|
{ "debug_st_idma0_ialn", 7, 2 },
|
|
{ "debug_st_idma0_idma2imsg", 6, 1 },
|
|
{ "debug_st_idma0_idma_sm", 0, 6 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_1", 0x12c4, 0 },
|
|
{ "debug_itp_empty", 12, 6 },
|
|
{ "debug_itp_expired", 6, 6 },
|
|
{ "debug_itp_pause", 5, 1 },
|
|
{ "debug_itp_del_done", 4, 1 },
|
|
{ "debug_itp_add_done", 3, 1 },
|
|
{ "debug_itp_evr_state", 0, 3 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_2", 0x12c8, 0 },
|
|
{ "debug_st_dbp_upcp_main", 14, 3 },
|
|
{ "debug_st_dbp_dbfifo_main", 13, 1 },
|
|
{ "debug_st_dbp_ctxt", 10, 3 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_3", 0x12cc, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_4", 0x12d0, 0 },
|
|
{ "debug_st_flm_dbptr", 30, 2 },
|
|
{ "debug_flm_cache_locked_count", 23, 7 },
|
|
{ "debug_flm_cache_agent", 20, 3 },
|
|
{ "debug_st_flm_cache", 16, 4 },
|
|
{ "debug_flm_dbptr_cidx_stall", 12, 1 },
|
|
{ "debug_flm_dbptr_qid", 0, 12 },
|
|
{ "SGE_DEBUG0_DBP_THREAD", 0x12d4, 0 },
|
|
{ "thread_st_main", 25, 6 },
|
|
{ "thread_st_cimfl", 21, 4 },
|
|
{ "thread_cmdop", 17, 4 },
|
|
{ "thread_qid", 0, 17 },
|
|
{ "SGE_DEBUG0_DBP_THREAD", 0x12d8, 0 },
|
|
{ "thread_st_main", 25, 6 },
|
|
{ "thread_st_cimfl", 21, 4 },
|
|
{ "thread_cmdop", 17, 4 },
|
|
{ "thread_qid", 0, 17 },
|
|
{ "SGE_DEBUG0_DBP_THREAD", 0x12dc, 0 },
|
|
{ "thread_st_main", 25, 6 },
|
|
{ "thread_st_cimfl", 21, 4 },
|
|
{ "thread_cmdop", 17, 4 },
|
|
{ "thread_qid", 0, 17 },
|
|
{ "SGE_DEBUG0_DBP_THREAD", 0x12e0, 0 },
|
|
{ "thread_st_main", 25, 6 },
|
|
{ "thread_st_cimfl", 21, 4 },
|
|
{ "thread_cmdop", 17, 4 },
|
|
{ "thread_qid", 0, 17 },
|
|
{ "SGE_DEBUG0_DBP_THREAD", 0x12e4, 0 },
|
|
{ "thread_st_main", 25, 6 },
|
|
{ "thread_st_cimfl", 21, 4 },
|
|
{ "thread_cmdop", 17, 4 },
|
|
{ "thread_qid", 0, 17 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_10", 0x12e8, 0 },
|
|
{ "debug_imsg_cpl", 16, 8 },
|
|
{ "debug_imsg_qid", 0, 16 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_11", 0x12ec, 0 },
|
|
{ "debug_idma1_qid", 16, 16 },
|
|
{ "debug_idma0_qid", 0, 16 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_12", 0x12f0, 0 },
|
|
{ "debug_idma1_flm_req_qid", 16, 16 },
|
|
{ "debug_idma0_flm_req_qid", 0, 16 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_13", 0x12f4, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_14", 0x12f8, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_15", 0x12fc, 0 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1300, 0 },
|
|
{ "PfIQsPerPage", 28, 4 },
|
|
{ "PfEQsPerPage", 24, 4 },
|
|
{ "PfWCQsPerPage", 20, 4 },
|
|
{ "PfWCOffEn", 19, 1 },
|
|
{ "PfMaxWCSize", 17, 2 },
|
|
{ "PfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1304, 0 },
|
|
{ "PfIQsPerPage", 28, 4 },
|
|
{ "PfEQsPerPage", 24, 4 },
|
|
{ "PfWCQsPerPage", 20, 4 },
|
|
{ "PfWCOffEn", 19, 1 },
|
|
{ "PfMaxWCSize", 17, 2 },
|
|
{ "PfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1308, 0 },
|
|
{ "PfIQsPerPage", 28, 4 },
|
|
{ "PfEQsPerPage", 24, 4 },
|
|
{ "PfWCQsPerPage", 20, 4 },
|
|
{ "PfWCOffEn", 19, 1 },
|
|
{ "PfMaxWCSize", 17, 2 },
|
|
{ "PfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x130c, 0 },
|
|
{ "PfIQsPerPage", 28, 4 },
|
|
{ "PfEQsPerPage", 24, 4 },
|
|
{ "PfWCQsPerPage", 20, 4 },
|
|
{ "PfWCOffEn", 19, 1 },
|
|
{ "PfMaxWCSize", 17, 2 },
|
|
{ "PfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1310, 0 },
|
|
{ "PfIQsPerPage", 28, 4 },
|
|
{ "PfEQsPerPage", 24, 4 },
|
|
{ "PfWCQsPerPage", 20, 4 },
|
|
{ "PfWCOffEn", 19, 1 },
|
|
{ "PfMaxWCSize", 17, 2 },
|
|
{ "PfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1314, 0 },
|
|
{ "PfIQsPerPage", 28, 4 },
|
|
{ "PfEQsPerPage", 24, 4 },
|
|
{ "PfWCQsPerPage", 20, 4 },
|
|
{ "PfWCOffEn", 19, 1 },
|
|
{ "PfMaxWCSize", 17, 2 },
|
|
{ "PfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1318, 0 },
|
|
{ "PfIQsPerPage", 28, 4 },
|
|
{ "PfEQsPerPage", 24, 4 },
|
|
{ "PfWCQsPerPage", 20, 4 },
|
|
{ "PfWCOffEn", 19, 1 },
|
|
{ "PfMaxWCSize", 17, 2 },
|
|
{ "PfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x131c, 0 },
|
|
{ "PfIQsPerPage", 28, 4 },
|
|
{ "PfEQsPerPage", 24, 4 },
|
|
{ "PfWCQsPerPage", 20, 4 },
|
|
{ "PfWCOffEn", 19, 1 },
|
|
{ "PfMaxWCSize", 17, 2 },
|
|
{ "PfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1320, 0 },
|
|
{ "VfIQsPerPage", 28, 4 },
|
|
{ "VfEQsPerPage", 24, 4 },
|
|
{ "VfWCQsPerPage", 20, 4 },
|
|
{ "VfWCOffEn", 19, 1 },
|
|
{ "VfMaxWCSize", 17, 2 },
|
|
{ "VfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1324, 0 },
|
|
{ "VfIQsPerPage", 28, 4 },
|
|
{ "VfEQsPerPage", 24, 4 },
|
|
{ "VfWCQsPerPage", 20, 4 },
|
|
{ "VfWCOffEn", 19, 1 },
|
|
{ "VfMaxWCSize", 17, 2 },
|
|
{ "VfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1328, 0 },
|
|
{ "VfIQsPerPage", 28, 4 },
|
|
{ "VfEQsPerPage", 24, 4 },
|
|
{ "VfWCQsPerPage", 20, 4 },
|
|
{ "VfWCOffEn", 19, 1 },
|
|
{ "VfMaxWCSize", 17, 2 },
|
|
{ "VfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x132c, 0 },
|
|
{ "VfIQsPerPage", 28, 4 },
|
|
{ "VfEQsPerPage", 24, 4 },
|
|
{ "VfWCQsPerPage", 20, 4 },
|
|
{ "VfWCOffEn", 19, 1 },
|
|
{ "VfMaxWCSize", 17, 2 },
|
|
{ "VfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1330, 0 },
|
|
{ "VfIQsPerPage", 28, 4 },
|
|
{ "VfEQsPerPage", 24, 4 },
|
|
{ "VfWCQsPerPage", 20, 4 },
|
|
{ "VfWCOffEn", 19, 1 },
|
|
{ "VfMaxWCSize", 17, 2 },
|
|
{ "VfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1334, 0 },
|
|
{ "VfIQsPerPage", 28, 4 },
|
|
{ "VfEQsPerPage", 24, 4 },
|
|
{ "VfWCQsPerPage", 20, 4 },
|
|
{ "VfWCOffEn", 19, 1 },
|
|
{ "VfMaxWCSize", 17, 2 },
|
|
{ "VfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1338, 0 },
|
|
{ "VfIQsPerPage", 28, 4 },
|
|
{ "VfEQsPerPage", 24, 4 },
|
|
{ "VfWCQsPerPage", 20, 4 },
|
|
{ "VfWCOffEn", 19, 1 },
|
|
{ "VfMaxWCSize", 17, 2 },
|
|
{ "VfWCOffset", 0, 17 },
|
|
{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x133c, 0 },
|
|
{ "VfIQsPerPage", 28, 4 },
|
|
{ "VfEQsPerPage", 24, 4 },
|
|
{ "VfWCQsPerPage", 20, 4 },
|
|
{ "VfWCOffEn", 19, 1 },
|
|
{ "VfMaxWCSize", 17, 2 },
|
|
{ "VfWCOffset", 0, 17 },
|
|
{ "SGE_LA_RDPTR_0", 0x1800, 0 },
|
|
{ "SGE_LA_RDDATA_0", 0x1804, 0 },
|
|
{ "SGE_LA_WRPTR_0", 0x1808, 0 },
|
|
{ "SGE_LA_RESERVED_0", 0x180c, 0 },
|
|
{ "SGE_LA_RDPTR_1", 0x1810, 0 },
|
|
{ "SGE_LA_RDDATA_1", 0x1814, 0 },
|
|
{ "SGE_LA_WRPTR_1", 0x1818, 0 },
|
|
{ "SGE_LA_RESERVED_1", 0x181c, 0 },
|
|
{ "SGE_LA_RDPTR_2", 0x1820, 0 },
|
|
{ "SGE_LA_RDDATA_2", 0x1824, 0 },
|
|
{ "SGE_LA_WRPTR_2", 0x1828, 0 },
|
|
{ "SGE_LA_RESERVED_2", 0x182c, 0 },
|
|
{ "SGE_LA_RDPTR_3", 0x1830, 0 },
|
|
{ "SGE_LA_RDDATA_3", 0x1834, 0 },
|
|
{ "SGE_LA_WRPTR_3", 0x1838, 0 },
|
|
{ "SGE_LA_RESERVED_3", 0x183c, 0 },
|
|
{ "SGE_LA_RDPTR_4", 0x1840, 0 },
|
|
{ "SGE_LA_RDDATA_4", 0x1844, 0 },
|
|
{ "SGE_LA_WRPTR_4", 0x1848, 0 },
|
|
{ "SGE_LA_RESERVED_4", 0x184c, 0 },
|
|
{ "SGE_LA_RDPTR_5", 0x1850, 0 },
|
|
{ "SGE_LA_RDDATA_5", 0x1854, 0 },
|
|
{ "SGE_LA_WRPTR_5", 0x1858, 0 },
|
|
{ "SGE_LA_RESERVED_5", 0x185c, 0 },
|
|
{ "SGE_LA_RDPTR_6", 0x1860, 0 },
|
|
{ "SGE_LA_RDDATA_6", 0x1864, 0 },
|
|
{ "SGE_LA_WRPTR_6", 0x1868, 0 },
|
|
{ "SGE_LA_RESERVED_6", 0x186c, 0 },
|
|
{ "SGE_LA_RDPTR_7", 0x1870, 0 },
|
|
{ "SGE_LA_RDDATA_7", 0x1874, 0 },
|
|
{ "SGE_LA_WRPTR_7", 0x1878, 0 },
|
|
{ "SGE_LA_RESERVED_7", 0x187c, 0 },
|
|
{ "SGE_LA_RDPTR_8", 0x1880, 0 },
|
|
{ "SGE_LA_RDDATA_8", 0x1884, 0 },
|
|
{ "SGE_LA_WRPTR_8", 0x1888, 0 },
|
|
{ "SGE_LA_RESERVED_8", 0x188c, 0 },
|
|
{ "SGE_LA_RDPTR_9", 0x1890, 0 },
|
|
{ "SGE_LA_RDDATA_9", 0x1894, 0 },
|
|
{ "SGE_LA_WRPTR_9", 0x1898, 0 },
|
|
{ "SGE_LA_RESERVED_9", 0x189c, 0 },
|
|
{ "SGE_LA_RDPTR_10", 0x18a0, 0 },
|
|
{ "SGE_LA_RDDATA_10", 0x18a4, 0 },
|
|
{ "SGE_LA_WRPTR_10", 0x18a8, 0 },
|
|
{ "SGE_LA_RESERVED_10", 0x18ac, 0 },
|
|
{ "SGE_LA_RDPTR_11", 0x18b0, 0 },
|
|
{ "SGE_LA_RDDATA_11", 0x18b4, 0 },
|
|
{ "SGE_LA_WRPTR_11", 0x18b8, 0 },
|
|
{ "SGE_LA_RESERVED_11", 0x18bc, 0 },
|
|
{ "SGE_LA_RDPTR_12", 0x18c0, 0 },
|
|
{ "SGE_LA_RDDATA_12", 0x18c4, 0 },
|
|
{ "SGE_LA_WRPTR_12", 0x18c8, 0 },
|
|
{ "SGE_LA_RESERVED_12", 0x18cc, 0 },
|
|
{ "SGE_LA_RDPTR_13", 0x18d0, 0 },
|
|
{ "SGE_LA_RDDATA_13", 0x18d4, 0 },
|
|
{ "SGE_LA_WRPTR_13", 0x18d8, 0 },
|
|
{ "SGE_LA_RESERVED_13", 0x18dc, 0 },
|
|
{ "SGE_LA_RDPTR_14", 0x18e0, 0 },
|
|
{ "SGE_LA_RDDATA_14", 0x18e4, 0 },
|
|
{ "SGE_LA_WRPTR_14", 0x18e8, 0 },
|
|
{ "SGE_LA_RESERVED_14", 0x18ec, 0 },
|
|
{ "SGE_LA_RDPTR_15", 0x18f0, 0 },
|
|
{ "SGE_LA_RDDATA_15", 0x18f4, 0 },
|
|
{ "SGE_LA_WRPTR_15", 0x18f8, 0 },
|
|
{ "SGE_LA_RESERVED_15", 0x18fc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_pcie_regs[] = {
|
|
{ "PCIE_INT_ENABLE", 0x3000, 0 },
|
|
{ "IPGrpPerr", 31, 1 },
|
|
{ "NonFatalErr", 30, 1 },
|
|
{ "RdRspErr", 29, 1 },
|
|
{ "TRGT1GrpPerr", 28, 1 },
|
|
{ "IPSOTPerr", 27, 1 },
|
|
{ "IPRetryPerr", 26, 1 },
|
|
{ "IPRxDataGrpPerr", 25, 1 },
|
|
{ "IPRxHdrGrpPerr", 24, 1 },
|
|
{ "PIOTagQPerr", 23, 1 },
|
|
{ "MAGrpPerr", 22, 1 },
|
|
{ "VFIDPerr", 21, 1 },
|
|
{ "FIDPerr", 20, 1 },
|
|
{ "CfgSnpPerr", 19, 1 },
|
|
{ "HRspPerr", 18, 1 },
|
|
{ "HReqRdPerr", 17, 1 },
|
|
{ "HReqWrPerr", 16, 1 },
|
|
{ "DRspPerr", 15, 1 },
|
|
{ "DReqRdPerr", 14, 1 },
|
|
{ "DReqWrPerr", 13, 1 },
|
|
{ "CRspPerr", 12, 1 },
|
|
{ "CReqRdPerr", 11, 1 },
|
|
{ "MstTagQPerr", 10, 1 },
|
|
{ "TgtTagQPerr", 9, 1 },
|
|
{ "PIOReqGrpPerr", 8, 1 },
|
|
{ "PIOCplGrpPerr", 7, 1 },
|
|
{ "MSIXDIPerr", 6, 1 },
|
|
{ "MSIXDataPerr", 5, 1 },
|
|
{ "MSIXAddrHPerr", 4, 1 },
|
|
{ "MSIXAddrLPerr", 3, 1 },
|
|
{ "MSIXStiPerr", 2, 1 },
|
|
{ "MstTimeoutPerr", 1, 1 },
|
|
{ "MstGrpPerr", 0, 1 },
|
|
{ "PCIE_INT_CAUSE", 0x3004, 0 },
|
|
{ "IPGrpPerr", 31, 1 },
|
|
{ "NonFatalErr", 30, 1 },
|
|
{ "RdRspErr", 29, 1 },
|
|
{ "TRGT1GrpPerr", 28, 1 },
|
|
{ "IPSOTPerr", 27, 1 },
|
|
{ "IPRetryPerr", 26, 1 },
|
|
{ "IPRxDataGrpPerr", 25, 1 },
|
|
{ "IPRxHdrGrpPerr", 24, 1 },
|
|
{ "PIOTagQPerr", 23, 1 },
|
|
{ "MAGrpPerr", 22, 1 },
|
|
{ "VFIDPerr", 21, 1 },
|
|
{ "FIDPerr", 20, 1 },
|
|
{ "CfgSnpPerr", 19, 1 },
|
|
{ "HRspPerr", 18, 1 },
|
|
{ "HReqRdPerr", 17, 1 },
|
|
{ "HReqWrPerr", 16, 1 },
|
|
{ "DRspPerr", 15, 1 },
|
|
{ "DReqRdPerr", 14, 1 },
|
|
{ "DReqWrPerr", 13, 1 },
|
|
{ "CRspPerr", 12, 1 },
|
|
{ "CReqRdPerr", 11, 1 },
|
|
{ "MstTagQPerr", 10, 1 },
|
|
{ "TgtTagQPerr", 9, 1 },
|
|
{ "PIOReqGrpPerr", 8, 1 },
|
|
{ "PIOCplGrpPerr", 7, 1 },
|
|
{ "MSIXDIPerr", 6, 1 },
|
|
{ "MSIXDataPerr", 5, 1 },
|
|
{ "MSIXAddrHPerr", 4, 1 },
|
|
{ "MSIXAddrLPerr", 3, 1 },
|
|
{ "MSIXStiPerr", 2, 1 },
|
|
{ "MstTimeoutPerr", 1, 1 },
|
|
{ "MstGrpPerr", 0, 1 },
|
|
{ "PCIE_PERR_ENABLE", 0x3008, 0 },
|
|
{ "IPGrpPerr", 31, 1 },
|
|
{ "TRGT1GrpPerr", 28, 1 },
|
|
{ "IPSOTPerr", 27, 1 },
|
|
{ "IPRetryPerr", 26, 1 },
|
|
{ "IPRxDataGrpPerr", 25, 1 },
|
|
{ "IPRxHdrGrpPerr", 24, 1 },
|
|
{ "PIOTagQPerr", 23, 1 },
|
|
{ "MAGrpPerr", 22, 1 },
|
|
{ "VFIDPerr", 21, 1 },
|
|
{ "FIDPerr", 20, 1 },
|
|
{ "CfgSnpPerr", 19, 1 },
|
|
{ "HRspPerr", 18, 1 },
|
|
{ "HReqRdPerr", 17, 1 },
|
|
{ "HReqWrPerr", 16, 1 },
|
|
{ "DRspPerr", 15, 1 },
|
|
{ "DReqRdPerr", 14, 1 },
|
|
{ "DReqWrPerr", 13, 1 },
|
|
{ "CRspPerr", 12, 1 },
|
|
{ "CReqRdPerr", 11, 1 },
|
|
{ "MstTagQPerr", 10, 1 },
|
|
{ "TgtTagQPerr", 9, 1 },
|
|
{ "PIOReqGrpPerr", 8, 1 },
|
|
{ "PIOCplGrpPerr", 7, 1 },
|
|
{ "MSIXDIPerr", 6, 1 },
|
|
{ "MSIXDataPerr", 5, 1 },
|
|
{ "MSIXAddrHPerr", 4, 1 },
|
|
{ "MSIXAddrLPerr", 3, 1 },
|
|
{ "MSIXStiPerr", 2, 1 },
|
|
{ "MstTimeoutPerr", 1, 1 },
|
|
{ "MstGrpPerr", 0, 1 },
|
|
{ "PCIE_PERR_INJECT", 0x300c, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "IDE", 0, 1 },
|
|
{ "PCIE_NONFAT_ERR", 0x3010, 0 },
|
|
{ "MARspUE", 30, 1 },
|
|
{ "MAReqTimeout", 29, 1 },
|
|
{ "TRGT1BARTypeErr", 28, 1 },
|
|
{ "MAExtraRspErr", 27, 1 },
|
|
{ "MARspTimeout", 26, 1 },
|
|
{ "INTVFAllMSIDisErr", 25, 1 },
|
|
{ "INTVFRangeErr", 24, 1 },
|
|
{ "INTPLIRspErr", 23, 1 },
|
|
{ "MEMReqRdTagErr", 22, 1 },
|
|
{ "CFGInitDoneErr", 21, 1 },
|
|
{ "BAR2Timeout", 20, 1 },
|
|
{ "VPDTimeout", 19, 1 },
|
|
{ "MEMRspRdTagErr", 18, 1 },
|
|
{ "MEMRspWrTagErr", 17, 1 },
|
|
{ "PIORspRdTagErr", 16, 1 },
|
|
{ "PIORspWrTagErr", 15, 1 },
|
|
{ "DBITimeout", 14, 1 },
|
|
{ "PIOUnAlindWr", 13, 1 },
|
|
{ "BAR2RdErr", 12, 1 },
|
|
{ "MAWrEOPErr", 11, 1 },
|
|
{ "MARdEOPErr", 10, 1 },
|
|
{ "RdRspErr", 9, 1 },
|
|
{ "VPDRspErr", 8, 1 },
|
|
{ "KDBEOPErr", 7, 1 },
|
|
{ "MemReq", 4, 1 },
|
|
{ "PIOReq", 3, 1 },
|
|
{ "BAR2Req", 2, 1 },
|
|
{ "CfgSnp", 0, 1 },
|
|
{ "PCIE_CFG", 0x3014, 0 },
|
|
{ "PIOStopEn", 31, 1 },
|
|
{ "DiagCtrlBus", 28, 3 },
|
|
{ "IPPerrEn", 27, 1 },
|
|
{ "CfgdExtTagEn", 26, 1 },
|
|
{ "CfgdMaxPyldSz", 23, 3 },
|
|
{ "CfgdMaxRdReqSz", 20, 3 },
|
|
{ "DCAEn", 17, 1 },
|
|
{ "CMDReqPriority", 16, 1 },
|
|
{ "VPDReqProtect", 14, 2 },
|
|
{ "DroppedRdRspData", 12, 1 },
|
|
{ "AI_INTX_ReAssertEn", 11, 1 },
|
|
{ "AutoTxnDisable", 10, 1 },
|
|
{ "TC0_Stamp", 9, 1 },
|
|
{ "AI_TCVal", 6, 3 },
|
|
{ "DMAStopEn", 5, 1 },
|
|
{ "DevStateRstMode", 4, 1 },
|
|
{ "LinkReqRstPCIeCRstMode", 3, 1 },
|
|
{ "LinkDnRstEn", 0, 1 },
|
|
{ "PCIE_CFG2", 0x3018, 0 },
|
|
{ "BAR2Timer", 4, 12 },
|
|
{ "MstReqRdRRASimple", 3, 1 },
|
|
{ "TotMaxTag", 0, 3 },
|
|
{ "PCIE_CFG3", 0x301c, 0 },
|
|
{ "AutoPIOCookieMatch", 6, 1 },
|
|
{ "FLRPndCplMode", 4, 2 },
|
|
{ "HMADCASTFirstOnly", 2, 1 },
|
|
{ "CMDDCASTFirstOnly", 1, 1 },
|
|
{ "DMADCASTFirstOnly", 0, 1 },
|
|
{ "PCIE_CFG4", 0x3020, 0 },
|
|
{ "L1ClkRemovalEn", 17, 1 },
|
|
{ "ReadyEnterL23", 16, 1 },
|
|
{ "ExitL1", 12, 1 },
|
|
{ "EnterL1", 8, 1 },
|
|
{ "GenPME", 0, 8 },
|
|
{ "PCIE_CFG5", 0x3024, 0 },
|
|
{ "EnableSKPParityFix", 2, 1 },
|
|
{ "EnableL2EntryInL1", 1, 1 },
|
|
{ "HoldCplEnteringL1", 0, 1 },
|
|
{ "PCIE_CFG6", 0x3028, 0 },
|
|
{ "PERstTimerCount", 12, 14 },
|
|
{ "PERstTimeout", 8, 1 },
|
|
{ "PERstTimer", 0, 4 },
|
|
{ "PCIE_CFG7", 0x302c, 0 },
|
|
{ "PCIE_CFG_SPACE_REQ", 0x3060, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "AI", 30, 1 },
|
|
{ "CS2", 29, 1 },
|
|
{ "WrBE", 25, 4 },
|
|
{ "VFVld", 24, 1 },
|
|
{ "RVF", 16, 8 },
|
|
{ "PF", 12, 3 },
|
|
{ "ExtRegister", 8, 4 },
|
|
{ "Register", 0, 8 },
|
|
{ "PCIE_CFG_SPACE_DATA", 0x3064, 0 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3068, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x306c, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3070, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x3074, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3078, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x307c, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3080, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x3084, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3088, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x308c, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3090, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x3094, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3098, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x309c, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x30a0, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x30a4, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MAILBOX_BASE_WIN", 0x30a8, 0 },
|
|
{ "PCIEOfst", 6, 26 },
|
|
{ "BIR", 4, 2 },
|
|
{ "Window", 0, 2 },
|
|
{ "PCIE_MAILBOX_OFFSET", 0x30ac, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PCIE_MA_CTRL", 0x30b0, 0 },
|
|
{ "TagFree", 29, 1 },
|
|
{ "MaxRspCnt", 24, 5 },
|
|
{ "MaxReqCnt", 16, 7 },
|
|
{ "MaxReqSize", 8, 3 },
|
|
{ "MaxTag", 0, 5 },
|
|
{ "PCIE_FW", 0x30b8, 0 },
|
|
{ "PCIE_FW_PF", 0x30bc, 0 },
|
|
{ "PCIE_FW_PF", 0x30c0, 0 },
|
|
{ "PCIE_FW_PF", 0x30c4, 0 },
|
|
{ "PCIE_FW_PF", 0x30c8, 0 },
|
|
{ "PCIE_FW_PF", 0x30cc, 0 },
|
|
{ "PCIE_FW_PF", 0x30d0, 0 },
|
|
{ "PCIE_FW_PF", 0x30d4, 0 },
|
|
{ "PCIE_FW_PF", 0x30d8, 0 },
|
|
{ "PCIE_PIO_PAUSE", 0x30dc, 0 },
|
|
{ "PIOPauseDone", 31, 1 },
|
|
{ "MSTPauseDone", 30, 1 },
|
|
{ "PauseTime", 4, 24 },
|
|
{ "MSTPause", 1, 1 },
|
|
{ "PIOPause", 0, 1 },
|
|
{ "PCIE_MA_STAT", 0x30e0, 0 },
|
|
{ "PCIE_STATIC_CFG1", 0x30e4, 0 },
|
|
{ "AUXPOWER_DETECTED", 27, 1 },
|
|
{ "PCIE_STATIC_CFG2", 0x30e8, 0 },
|
|
{ "PL_CONTROL", 16, 16 },
|
|
{ "STATIC_SPARE3", 0, 14 },
|
|
{ "PCIE_DBG_INDIR_REQ", 0x30ec, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "AI", 30, 1 },
|
|
{ "Pointer", 8, 16 },
|
|
{ "Select", 0, 4 },
|
|
{ "PCIE_DBG_INDIR_DATA_0", 0x30f0, 0 },
|
|
{ "PCIE_DBG_INDIR_DATA_1", 0x30f4, 0 },
|
|
{ "PCIE_DBG_INDIR_DATA_2", 0x30f8, 0 },
|
|
{ "PCIE_DBG_INDIR_DATA_3", 0x30fc, 0 },
|
|
{ "PCIE_PF_INT_CFG", 0x3140, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x3144, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3148, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x314c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3150, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x3154, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3158, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x315c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3160, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x3164, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3168, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x316c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3170, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x3174, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3178, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x317c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3180, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3184, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3188, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x318c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3190, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3194, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3198, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x319c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31a0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31a8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31b0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31b8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31c0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31c8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31d0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31d8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31e0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31e8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31f0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31f8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3200, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3204, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3208, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x320c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3210, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3214, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3218, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x321c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3220, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3224, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3228, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x322c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3230, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3234, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3238, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x323c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3240, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3244, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3248, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x324c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3250, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3254, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3258, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x325c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3260, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3264, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3268, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x326c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3270, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3274, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3278, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x327c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3280, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3284, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3288, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x328c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3290, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3294, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3298, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x329c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32a0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32a8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32b0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32b8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32c0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32c8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32d0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32d8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32e0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32e8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32f0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32f8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3300, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3304, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3308, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x330c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3310, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3314, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3318, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x331c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3320, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3324, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3328, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x332c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3330, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3334, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3338, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x333c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3340, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3344, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3348, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x334c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3350, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3354, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3358, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x335c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3360, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3364, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3368, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x336c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3370, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3374, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3378, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x337c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3380, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3384, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3388, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x338c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3390, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3394, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3398, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x339c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33a0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33a8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33b0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33b8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33c0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33c8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33d0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33d8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33e0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33e8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33f0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33f8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3400, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3404, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3408, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x340c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3410, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3414, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3418, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x341c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3420, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3424, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3428, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x342c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3430, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3434, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3438, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x343c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3440, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3444, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3448, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x344c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3450, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3454, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3458, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x345c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3460, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3464, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3468, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x346c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3470, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3474, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3478, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x347c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3480, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3484, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3488, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x348c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3490, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3494, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3498, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x349c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34a0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34a8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34b0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34b8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34c0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34c8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34d0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34d8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34e0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34e8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34f0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34f8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3500, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3504, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3508, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x350c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3510, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3514, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3518, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x351c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3520, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3524, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3528, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x352c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3530, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3534, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3538, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x353c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3540, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3544, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3548, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x354c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3550, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3554, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3558, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x355c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3560, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3564, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3568, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x356c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3570, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3574, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3578, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x357c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_MSI_EN", 0x35a8, 0 },
|
|
{ "PCIE_VF_MSI_EN_0", 0x35ac, 0 },
|
|
{ "PCIE_VF_MSI_EN_1", 0x35b0, 0 },
|
|
{ "PCIE_VF_MSI_EN_2", 0x35b4, 0 },
|
|
{ "PCIE_VF_MSI_EN_3", 0x35b8, 0 },
|
|
{ "PCIE_PF_MSIX_EN", 0x35bc, 0 },
|
|
{ "PCIE_VF_MSIX_EN_0", 0x35c0, 0 },
|
|
{ "PCIE_VF_MSIX_EN_1", 0x35c4, 0 },
|
|
{ "PCIE_VF_MSIX_EN_2", 0x35c8, 0 },
|
|
{ "PCIE_VF_MSIX_EN_3", 0x35cc, 0 },
|
|
{ "PCIE_FID_VFID_SEL", 0x35ec, 0 },
|
|
{ "PCIE_FID_VFID", 0x3600, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3604, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3608, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x360c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3610, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3614, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3618, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x361c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3620, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3624, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3628, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x362c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3630, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3634, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3638, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x363c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3640, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3644, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x3648, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
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{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x5570, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x5574, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x5578, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x557c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x5580, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x5584, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x5588, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x558c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x5590, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x5594, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x5598, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x559c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_FID_VFID", 0x55fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 15, 9 },
|
|
{ "TC", 12, 3 },
|
|
{ "VFVld", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "RVF", 0, 8 },
|
|
{ "PCIE_COOKIE_STAT", 0x5600, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x5604, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x5608, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x560c, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x5610, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x5614, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x5618, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x561c, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_FLR_PIO", 0x5620, 0 },
|
|
{ "RcvdBAR2Cookie", 24, 8 },
|
|
{ "RcvdMARspCookie", 16, 8 },
|
|
{ "RcvdPIORspCookie", 8, 8 },
|
|
{ "ExpdCookie", 0, 8 },
|
|
{ "PCIE_FLR_PIO2", 0x5624, 0 },
|
|
{ "RcvdVDMRxCookie", 24, 8 },
|
|
{ "RcvdVDMTxCookie", 16, 8 },
|
|
{ "RcvdMAReqCookie", 8, 8 },
|
|
{ "RcvdPIOReqCookie", 0, 8 },
|
|
{ "PCIE_VC0_CDTS0", 0x56cc, 0 },
|
|
{ "CPLD0", 20, 12 },
|
|
{ "PH0", 12, 8 },
|
|
{ "PD0", 0, 12 },
|
|
{ "PCIE_VC0_CDTS1", 0x56d0, 0 },
|
|
{ "CPLH0", 20, 8 },
|
|
{ "NPH0", 12, 8 },
|
|
{ "NPD0", 0, 12 },
|
|
{ "PCIE_VC1_CDTS0", 0x56d4, 0 },
|
|
{ "CPLD1", 20, 12 },
|
|
{ "PH1", 12, 8 },
|
|
{ "PD1", 0, 12 },
|
|
{ "PCIE_VC1_CDTS1", 0x56d8, 0 },
|
|
{ "CPLH1", 20, 8 },
|
|
{ "NPH1", 12, 8 },
|
|
{ "NPD1", 0, 12 },
|
|
{ "PCIE_FLR_PF_STATUS", 0x56dc, 0 },
|
|
{ "PCIE_FLR_VF0_STATUS", 0x56e0, 0 },
|
|
{ "PCIE_FLR_VF1_STATUS", 0x56e4, 0 },
|
|
{ "PCIE_FLR_VF2_STATUS", 0x56e8, 0 },
|
|
{ "PCIE_FLR_VF3_STATUS", 0x56ec, 0 },
|
|
{ "PCIE_STAT", 0x56f4, 0 },
|
|
{ "PM_Status", 24, 8 },
|
|
{ "PM_CurrentState", 20, 3 },
|
|
{ "LTSSMEnable", 12, 1 },
|
|
{ "StateCfgInitF", 4, 8 },
|
|
{ "StateCfgInit", 0, 4 },
|
|
{ "PCIE_CRS", 0x56f8, 0 },
|
|
{ "PCIE_LTSSM", 0x56fc, 0 },
|
|
{ "Stall_Disable", 1, 1 },
|
|
{ "Enable", 0, 1 },
|
|
{ "PCIE_PF_CFG", 0x1e040, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1e044, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1e04c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1e440, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1e444, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1e44c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1e840, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1e844, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1e84c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1ec40, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1ec44, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1ec4c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1f040, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1f044, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1f04c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1f440, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1f444, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1f44c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1f840, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1f844, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1f84c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1fc40, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1fc44, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1fc4c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER", 0x5700, 0 },
|
|
{ "Replay_Time_Limit", 16, 16 },
|
|
{ "Ack_Latency_Timer_Limit", 0, 16 },
|
|
{ "PCIE_CORE_VENDOR_SPECIFIC_DLLP", 0x5704, 0 },
|
|
{ "PCIE_CORE_PORT_FORCE_LINK", 0x5708, 0 },
|
|
{ "Low_Power_Entrance_Count", 24, 8 },
|
|
{ "Link_State", 16, 6 },
|
|
{ "Force_Link", 15, 1 },
|
|
{ "Link_Number", 0, 8 },
|
|
{ "PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL", 0x570c, 0 },
|
|
{ "Enter_ASPM_L1_wo_L0s", 30, 1 },
|
|
{ "L1_Entrance_Latency", 27, 3 },
|
|
{ "L0s_Entrance_Latency", 24, 3 },
|
|
{ "Common_Clock_N_FTS", 16, 8 },
|
|
{ "N_FTS", 8, 8 },
|
|
{ "Ack_Frequency", 0, 8 },
|
|
{ "PCIE_CORE_PORT_LINK_CONTROL", 0x5710, 0 },
|
|
{ "Crosslink_Active", 23, 1 },
|
|
{ "Crosslink_Enable", 22, 1 },
|
|
{ "Link_Mode_Enable", 16, 6 },
|
|
{ "Fast_Link_Mode", 7, 1 },
|
|
{ "DLL_Link_Enable", 5, 1 },
|
|
{ "Reset_Assert", 3, 1 },
|
|
{ "Loopback_Enable", 2, 1 },
|
|
{ "Scramble_Disable", 1, 1 },
|
|
{ "Vendor_Specific_DLLP_Request", 0, 1 },
|
|
{ "PCIE_CORE_LANE_SKEW", 0x5714, 0 },
|
|
{ "Disable_DeSkew", 31, 1 },
|
|
{ "Ack_Nak_Disable", 25, 1 },
|
|
{ "Flow_Control_Disable", 24, 1 },
|
|
{ "Insert_TxSkew", 0, 24 },
|
|
{ "PCIE_CORE_SYMBOL_NUMBER", 0x5718, 0 },
|
|
{ "Ack_Nak_Timer_Modifier", 19, 5 },
|
|
{ "Replay_Timer_Modifier", 14, 5 },
|
|
{ "MaxFunc", 0, 3 },
|
|
{ "PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1", 0x571c, 0 },
|
|
{ "Mask_RADM_Filter", 16, 16 },
|
|
{ "Disable_FC_Watchdog", 15, 1 },
|
|
{ "SKP_Interval", 0, 11 },
|
|
{ "PCIE_CORE_FILTER_MASK2", 0x5720, 0 },
|
|
{ "PCIE_CORE_DEBUG_0", 0x5728, 0 },
|
|
{ "PCIE_CORE_DEBUG_1", 0x572c, 0 },
|
|
{ "PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS", 0x5730, 0 },
|
|
{ "TxPH_FC", 12, 8 },
|
|
{ "TxPD_FC", 0, 12 },
|
|
{ "PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS", 0x5734, 0 },
|
|
{ "TxNPH_FC", 12, 8 },
|
|
{ "TxNPD_FC", 0, 12 },
|
|
{ "PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS", 0x5738, 0 },
|
|
{ "TxCPLH_FC", 12, 8 },
|
|
{ "TxCPLD_FC", 0, 12 },
|
|
{ "PCIE_CORE_QUEUE_STATUS", 0x573c, 0 },
|
|
{ "RxQueue_Not_Empty", 2, 1 },
|
|
{ "TxRetryBuf_Not_Empty", 1, 1 },
|
|
{ "RxTLP_FC_Not_Returned", 0, 1 },
|
|
{ "PCIE_CORE_VC_TRANSMIT_ARBITRATION_1", 0x5740, 0 },
|
|
{ "VC3_WRR", 24, 8 },
|
|
{ "VC2_WRR", 16, 8 },
|
|
{ "VC1_WRR", 8, 8 },
|
|
{ "VC0_WRR", 0, 8 },
|
|
{ "PCIE_CORE_VC_TRANSMIT_ARBITRATION_2", 0x5744, 0 },
|
|
{ "VC7_WRR", 24, 8 },
|
|
{ "VC6_WRR", 16, 8 },
|
|
{ "VC5_WRR", 8, 8 },
|
|
{ "VC4_WRR", 0, 8 },
|
|
{ "PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL", 0x5748, 0 },
|
|
{ "VC0_Rx_Ordering", 31, 1 },
|
|
{ "VC0_TLP_Ordering", 30, 1 },
|
|
{ "VC0_PTLP_Queue_Mode", 21, 3 },
|
|
{ "VC0_PH_Credits", 12, 8 },
|
|
{ "VC0_PD_Credits", 0, 12 },
|
|
{ "PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x574c, 0 },
|
|
{ "VC0_NPTLP_Queue_Mode", 21, 3 },
|
|
{ "VC0_NPH_Credits", 12, 8 },
|
|
{ "VC0_NPD_Credits", 0, 12 },
|
|
{ "PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x5750, 0 },
|
|
{ "VC0_CPLTLP_Queue_Mode", 21, 3 },
|
|
{ "VC0_CPLH_Credits", 12, 8 },
|
|
{ "VC0_CPLD_Credits", 0, 12 },
|
|
{ "PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL", 0x5754, 0 },
|
|
{ "VC1_TLP_Ordering", 30, 1 },
|
|
{ "VC1_PTLP_Queue_Mode", 21, 3 },
|
|
{ "VC1_PH_Credits", 12, 8 },
|
|
{ "VC1_PD_Credits", 0, 12 },
|
|
{ "PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x5758, 0 },
|
|
{ "VC1_NPTLP_Queue_Mode", 21, 3 },
|
|
{ "VC1_NPH_Credits", 12, 8 },
|
|
{ "VC1_NPD_Credits", 0, 12 },
|
|
{ "PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x575c, 0 },
|
|
{ "VC1_CPLTLP_Queue_Mode", 21, 3 },
|
|
{ "VC1_CPLH_Credits", 12, 8 },
|
|
{ "VC1_CPLD_Credits", 0, 12 },
|
|
{ "PCIE_CORE_LINK_WIDTH_SPEED_CHANGE", 0x580c, 0 },
|
|
{ "Sel_DeEmphasis", 20, 1 },
|
|
{ "TxCmplRcv", 19, 1 },
|
|
{ "PhyTxSwing", 18, 1 },
|
|
{ "DirSpdChange", 17, 1 },
|
|
{ "Auto_Lane_Flip_Ctrl_En", 16, 1 },
|
|
{ "Num_Lanes", 8, 5 },
|
|
{ "NFTS_Gen2_3", 0, 8 },
|
|
{ "PCIE_CORE_PHY_STATUS", 0x5810, 0 },
|
|
{ "PCIE_CORE_PHY_CONTROL", 0x5814, 0 },
|
|
{ "PCIE_CORE_GEN3_CONTROL", 0x5890, 0 },
|
|
{ "DC_Balance_Disable", 18, 1 },
|
|
{ "DLLP_Delay_Disable", 17, 1 },
|
|
{ "Eql_Disable", 16, 1 },
|
|
{ "Eql_Redo_Disable", 11, 1 },
|
|
{ "Eql_EIEOS_CntRst_Disable", 10, 1 },
|
|
{ "Eql_PH2_PH3_Disable", 9, 1 },
|
|
{ "Disable_Scrambler", 8, 1 },
|
|
{ "PCIE_CORE_GEN3_EQ_FS_LF", 0x5894, 0 },
|
|
{ "Full_Swing", 6, 6 },
|
|
{ "Low_Frequency", 0, 6 },
|
|
{ "PCIE_CORE_GEN3_EQ_PRESET_COEFF", 0x5898, 0 },
|
|
{ "PostCursor", 12, 6 },
|
|
{ "Cursor", 6, 6 },
|
|
{ "PreCursor", 0, 6 },
|
|
{ "PCIE_CORE_GEN3_EQ_PRESET_INDEX", 0x589c, 0 },
|
|
{ "PCIE_CORE_GEN3_EQ_STATUS", 0x58a4, 0 },
|
|
{ "PCIE_CORE_GEN3_EQ_CONTROL", 0x58a8, 0 },
|
|
{ "Include_Initial_FOM", 24, 1 },
|
|
{ "Preset_Request_Vector", 8, 16 },
|
|
{ "Phase23_2ms_Timeout_Disable", 5, 1 },
|
|
{ "After24ms", 4, 1 },
|
|
{ "Feedback_Mode", 0, 4 },
|
|
{ "PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK", 0x58ac, 0 },
|
|
{ "WinAperture_CPlus1", 14, 4 },
|
|
{ "WinAperture_CMins1", 10, 4 },
|
|
{ "Convergence_WinDepth", 5, 5 },
|
|
{ "EQMasterPhase_MinTime", 0, 5 },
|
|
{ "PCIE_CORE_PIPE_CONTROL", 0x58b8, 0 },
|
|
{ "Loopback_Enable", 31, 1 },
|
|
{ "PCIE_CORE_DBI_RO_WE", 0x58bc, 0 },
|
|
{ "PCIE_DMA_CFG", 0x5940, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxReqCnt", 20, 7 },
|
|
{ "MaxRdReqSize", 17, 3 },
|
|
{ "MaxRspCnt", 9, 8 },
|
|
{ "SeqChkDis", 8, 1 },
|
|
{ "MinTag", 0, 8 },
|
|
{ "PCIE_DMA_STAT", 0x5944, 0 },
|
|
{ "RspCnt", 20, 10 },
|
|
{ "RdReqCnt", 12, 6 },
|
|
{ "WrReqCnt", 0, 9 },
|
|
{ "PCIE_DMA_STAT2", 0x5948, 0 },
|
|
{ "CookieCnt", 24, 4 },
|
|
{ "RdSeqNumUpdCnt", 20, 4 },
|
|
{ "SIReqCnt", 16, 4 },
|
|
{ "WrEOPMatchSOP", 12, 1 },
|
|
{ "WrSOPCnt", 8, 4 },
|
|
{ "RdSOPCnt", 0, 8 },
|
|
{ "PCIE_DMA_STAT3", 0x594c, 0 },
|
|
{ "AtmReqSOPCnt", 24, 8 },
|
|
{ "AtmEOPMatchSOP", 17, 1 },
|
|
{ "RspEOPMatchSOP", 16, 1 },
|
|
{ "RspErrCnt", 8, 8 },
|
|
{ "RspSOPCnt", 0, 8 },
|
|
{ "PCIE_DMA_CFG", 0x5950, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxReqCnt", 20, 7 },
|
|
{ "MaxRdReqSize", 17, 3 },
|
|
{ "MaxRspCnt", 9, 8 },
|
|
{ "SeqChkDis", 8, 1 },
|
|
{ "MinTag", 0, 8 },
|
|
{ "PCIE_DMA_STAT", 0x5954, 0 },
|
|
{ "RspCnt", 20, 10 },
|
|
{ "RdReqCnt", 12, 6 },
|
|
{ "WrReqCnt", 0, 9 },
|
|
{ "PCIE_DMA_STAT2", 0x5958, 0 },
|
|
{ "CookieCnt", 24, 4 },
|
|
{ "RdSeqNumUpdCnt", 20, 4 },
|
|
{ "SIReqCnt", 16, 4 },
|
|
{ "WrEOPMatchSOP", 12, 1 },
|
|
{ "WrSOPCnt", 8, 4 },
|
|
{ "RdSOPCnt", 0, 8 },
|
|
{ "PCIE_DMA_STAT3", 0x595c, 0 },
|
|
{ "AtmReqSOPCnt", 24, 8 },
|
|
{ "AtmEOPMatchSOP", 17, 1 },
|
|
{ "RspEOPMatchSOP", 16, 1 },
|
|
{ "RspErrCnt", 8, 8 },
|
|
{ "RspSOPCnt", 0, 8 },
|
|
{ "PCIE_CMD_CFG", 0x5980, 0 },
|
|
{ "MaxRdReqSize", 17, 3 },
|
|
{ "MaxRspCnt", 9, 6 },
|
|
{ "UseCmdPool", 8, 1 },
|
|
{ "MinTag", 0, 8 },
|
|
{ "PCIE_CMD_STAT", 0x5984, 0 },
|
|
{ "RspCnt", 20, 8 },
|
|
{ "RdReqCnt", 12, 4 },
|
|
{ "PCIE_CMD_STAT2", 0x5988, 0 },
|
|
{ "PCIE_CMD_STAT3", 0x598c, 0 },
|
|
{ "RspEOPMatchSOP", 16, 1 },
|
|
{ "RspErrCnt", 8, 8 },
|
|
{ "RspSOPCnt", 0, 8 },
|
|
{ "PCIE_HMA_CFG", 0x59b0, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxReqCnt", 20, 7 },
|
|
{ "MaxRdReqSize", 17, 3 },
|
|
{ "MaxRspCnt", 9, 8 },
|
|
{ "SeqChkDis", 8, 1 },
|
|
{ "MinTag", 0, 8 },
|
|
{ "PCIE_HMA_STAT", 0x59b4, 0 },
|
|
{ "RspCnt", 20, 10 },
|
|
{ "RdReqCnt", 12, 6 },
|
|
{ "WrReqCnt", 0, 9 },
|
|
{ "PCIE_HMA_STAT2", 0x59b8, 0 },
|
|
{ "CookieCnt", 24, 4 },
|
|
{ "RdSeqNumUpdCnt", 20, 4 },
|
|
{ "WrEOPMatchSOP", 12, 1 },
|
|
{ "WrSOPCnt", 8, 4 },
|
|
{ "RdSOPCnt", 0, 8 },
|
|
{ "PCIE_HMA_STAT3", 0x59bc, 0 },
|
|
{ "RspEOPMatchSOP", 16, 1 },
|
|
{ "RspErrCnt", 8, 8 },
|
|
{ "RspSOPCnt", 0, 8 },
|
|
{ "PCIE_CGEN", 0x59c0, 0 },
|
|
{ "VPD_Dynamic_CGEN", 26, 1 },
|
|
{ "MA_Dynamic_CGEN", 25, 1 },
|
|
{ "Tagq_Dynamic_CGEN", 24, 1 },
|
|
{ "ReqCtl_Dynamic_CGEN", 23, 1 },
|
|
{ "RspDataProc_Dynamic_CGEN", 22, 1 },
|
|
{ "RspRdq_Dynamic_CGEN", 21, 1 },
|
|
{ "RspIPif_Dynamic_CGEN", 20, 1 },
|
|
{ "HMA_Static_CGEN", 19, 1 },
|
|
{ "HMA_Dynamic_CGEN", 18, 1 },
|
|
{ "CMD_Static_CGEN", 16, 1 },
|
|
{ "CMD_Dynamic_CGEN", 15, 1 },
|
|
{ "DMA_Static_CGEN", 13, 1 },
|
|
{ "DMA_Dynamic_CGEN", 12, 1 },
|
|
{ "VFID_SleepStatus", 10, 1 },
|
|
{ "VC1_SleepStatus", 9, 1 },
|
|
{ "STI_SleepStatus", 8, 1 },
|
|
{ "VFID_SleepReq", 2, 1 },
|
|
{ "VC1_SleepReq", 1, 1 },
|
|
{ "STI_SleepReq", 0, 1 },
|
|
{ "PCIE_MA_RSP", 0x59c4, 0 },
|
|
{ "TimerValue", 8, 24 },
|
|
{ "MAReqTimerEn", 1, 1 },
|
|
{ "TimerEn", 0, 1 },
|
|
{ "PCIE_HPRD", 0x59c8, 0 },
|
|
{ "NPH_CreditsAvailVC0", 19, 2 },
|
|
{ "NPD_CreditsAvailVC0", 17, 2 },
|
|
{ "NPH_CreditsAvailVC1", 15, 2 },
|
|
{ "NPD_CreditsAvailVC1", 13, 2 },
|
|
{ "NPH_CreditsRequired", 11, 2 },
|
|
{ "NPD_CreditsRequired", 9, 2 },
|
|
{ "ReqBurstCount", 5, 4 },
|
|
{ "ReqBurstFrequency", 1, 4 },
|
|
{ "EnableVC1", 0, 1 },
|
|
{ "PCIE_PERR_GROUP", 0x59d0, 0 },
|
|
{ "MA_RspCtlPerr", 26, 1 },
|
|
{ "MST_DataPathPerr", 25, 1 },
|
|
{ "MST_RspRdQPerr", 24, 1 },
|
|
{ "TRGT1_FIDLkUpHdrPerr", 20, 1 },
|
|
{ "TRGT1_AlindDataPerr", 19, 1 },
|
|
{ "TRGT1_UnAlinDataPerr", 18, 1 },
|
|
{ "TRGT1_ReqDataPerr", 17, 1 },
|
|
{ "TRGT1_ReqHdrPerr", 16, 1 },
|
|
{ "IPRxData_VC0Perr", 15, 1 },
|
|
{ "IPRxHdr_VC0Perr", 14, 1 },
|
|
{ "PIOCpl_VDMTxCtlPerr", 13, 1 },
|
|
{ "PIOCpl_VDMTxDataPerr", 12, 1 },
|
|
{ "MA_RspDataPerr", 11, 1 },
|
|
{ "MA_CplTagQPerr", 10, 1 },
|
|
{ "MA_ReqTagQPerr", 9, 1 },
|
|
{ "PIOReq_BAR2CtlPerr", 8, 1 },
|
|
{ "PIOReq_MEMCtlPerr", 7, 1 },
|
|
{ "PIOReq_PLMCtlPerr", 6, 1 },
|
|
{ "PIOReq_BAR2DataPerr", 5, 1 },
|
|
{ "PIOReq_MEMDataPerr", 4, 1 },
|
|
{ "PIOReq_PLMDataPerr", 3, 1 },
|
|
{ "PIOCpl_CtlPerr", 2, 1 },
|
|
{ "PIOCpl_DataPerr", 1, 1 },
|
|
{ "PIOCpl_PLMRspPerr", 0, 1 },
|
|
{ "PCIE_RSP_ERR_INT_LOG_EN", 0x59d4, 0 },
|
|
{ "CplStatusIntEn", 12, 1 },
|
|
{ "TimeoutIntEn", 11, 1 },
|
|
{ "DisabledIntEn", 10, 1 },
|
|
{ "RspDropFLRIntEn", 9, 1 },
|
|
{ "ReqUnderFLRIntEn", 8, 1 },
|
|
{ "CplStatusLogEn", 4, 1 },
|
|
{ "TimeoutLogEn", 3, 1 },
|
|
{ "DisabledLogEn", 2, 1 },
|
|
{ "RspDropFLRLogEn", 1, 1 },
|
|
{ "ReqUnderFLRLogEn", 0, 1 },
|
|
{ "PCIE_RSP_ERR_LOG1", 0x59d8, 0 },
|
|
{ "Tag", 25, 7 },
|
|
{ "CID", 22, 3 },
|
|
{ "ChNum", 19, 3 },
|
|
{ "ByteLen", 6, 13 },
|
|
{ "Reason", 3, 3 },
|
|
{ "CplStatus", 0, 3 },
|
|
{ "PCIE_RSP_ERR_LOG2", 0x59dc, 0 },
|
|
{ "Valid", 31, 1 },
|
|
{ "Addr10b", 9, 10 },
|
|
{ "VFID", 0, 9 },
|
|
{ "PCIE_REVISION", 0x5a00, 0 },
|
|
{ "PCIE_PDEBUG_INDEX", 0x5a04, 0 },
|
|
{ "PDEBUGSelH", 16, 7 },
|
|
{ "PDEBUGSelL", 0, 7 },
|
|
{ "PCIE_PDEBUG_DATA_HIGH", 0x5a08, 0 },
|
|
{ "PCIE_PDEBUG_DATA_LOW", 0x5a0c, 0 },
|
|
{ "PCIE_CDEBUG_INDEX", 0x5a10, 0 },
|
|
{ "CDEBUGSelH", 16, 8 },
|
|
{ "CDEBUGSelL", 0, 8 },
|
|
{ "PCIE_CDEBUG_DATA_HIGH", 0x5a14, 0 },
|
|
{ "PCIE_CDEBUG_DATA_LOW", 0x5a18, 0 },
|
|
{ "PCIE_BUS_MST_STAT_0", 0x5a60, 0 },
|
|
{ "PCIE_BUS_MST_STAT_1", 0x5a64, 0 },
|
|
{ "PCIE_BUS_MST_STAT_2", 0x5a68, 0 },
|
|
{ "PCIE_BUS_MST_STAT_3", 0x5a6c, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_0", 0x5a80, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_1", 0x5a84, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_2", 0x5a88, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_3", 0x5a8c, 0 },
|
|
{ "PCIE_DBI_TIMEOUT_CTL", 0x5a94, 0 },
|
|
{ "PCIE_DBI_TIMEOUT_STATUS0", 0x5a98, 0 },
|
|
{ "PCIE_DBI_TIMEOUT_STATUS1", 0x5a9c, 0 },
|
|
{ "Valid", 31, 1 },
|
|
{ "Source", 17, 2 },
|
|
{ "Write", 13, 4 },
|
|
{ "CS2", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VFVld", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "PCIE_PB_CTL", 0x5b94, 0 },
|
|
{ "PB_Sel", 16, 8 },
|
|
{ "PB_SelReg", 8, 8 },
|
|
{ "PB_Func", 0, 3 },
|
|
{ "PCIE_PB_DATA", 0x5b98, 0 },
|
|
{ "PCIE_CHANGESET", 0x59fc, 0 },
|
|
{ "PCIE_CUR_LINK", 0x5b9c, 0 },
|
|
{ "CfgInitCoeffDoneSeen", 22, 1 },
|
|
{ "CfgInitCoeffDone", 21, 1 },
|
|
{ "xmlh_link_up", 20, 1 },
|
|
{ "pm_linkst_in_l0s", 19, 1 },
|
|
{ "pm_linkst_in_l1", 18, 1 },
|
|
{ "pm_linkst_in_l2", 17, 1 },
|
|
{ "pm_linkst_l2_exit", 16, 1 },
|
|
{ "xmlh_in_rl0s", 15, 1 },
|
|
{ "xmlh_ltssm_state_rcvry_eq", 14, 1 },
|
|
{ "NegotiatedWidth", 8, 6 },
|
|
{ "ActiveLanes", 0, 8 },
|
|
{ "PCIE_PHY_REQRXPWR", 0x5ba0, 0 },
|
|
{ "Req_LnH_RxStateDone", 31, 1 },
|
|
{ "Req_LnH_RxStateReq", 30, 1 },
|
|
{ "Req_LnH_RxPwrState", 28, 2 },
|
|
{ "Req_LnG_RxStateDone", 27, 1 },
|
|
{ "Req_LnG_RxStateReq", 26, 1 },
|
|
{ "Req_LnG_RxPwrState", 24, 2 },
|
|
{ "Req_LnF_RxStateDone", 23, 1 },
|
|
{ "Req_LnF_RxStateReq", 22, 1 },
|
|
{ "Req_LnF_RxPwrState", 20, 2 },
|
|
{ "Req_LnE_RxStateDone", 19, 1 },
|
|
{ "Req_LnE_RxStateReq", 18, 1 },
|
|
{ "Req_LnE_RxPwrState", 16, 2 },
|
|
{ "Req_LnD_RxStateDone", 15, 1 },
|
|
{ "Req_LnD_RxStateReq", 14, 1 },
|
|
{ "Req_LnD_RxPwrState", 12, 2 },
|
|
{ "Req_LnC_RxStateDone", 11, 1 },
|
|
{ "Req_LnC_RxStateReq", 10, 1 },
|
|
{ "Req_LnC_RxPwrState", 8, 2 },
|
|
{ "Req_LnB_RxStateDone", 7, 1 },
|
|
{ "Req_LnB_RxStateReq", 6, 1 },
|
|
{ "Req_LnB_RxPwrState", 4, 2 },
|
|
{ "Req_LnA_RxStateDone", 3, 1 },
|
|
{ "Req_LnA_RxStateReq", 2, 1 },
|
|
{ "Req_LnA_RxPwrState", 0, 2 },
|
|
{ "PCIE_PHY_CURRXPWR", 0x5ba4, 0 },
|
|
{ "Cur_LnH_RxPwrState", 28, 3 },
|
|
{ "Cur_LnG_RxPwrState", 24, 3 },
|
|
{ "Cur_LnF_RxPwrState", 20, 3 },
|
|
{ "Cur_LnE_RxPwrState", 16, 3 },
|
|
{ "Cur_LnD_RxPwrState", 12, 3 },
|
|
{ "Cur_LnC_RxPwrState", 8, 3 },
|
|
{ "Cur_LnB_RxPwrState", 4, 3 },
|
|
{ "Cur_LnA_RxPwrState", 0, 3 },
|
|
{ "PCIE_PHY_GEN3_AE0", 0x5ba8, 0 },
|
|
{ "LnD_STAT", 28, 3 },
|
|
{ "LnD_CMD", 24, 3 },
|
|
{ "LnC_STAT", 20, 3 },
|
|
{ "LnC_CMD", 16, 3 },
|
|
{ "LnB_STAT", 12, 3 },
|
|
{ "LnB_CMD", 8, 3 },
|
|
{ "LnA_STAT", 4, 3 },
|
|
{ "LnA_CMD", 0, 3 },
|
|
{ "PCIE_PHY_GEN3_AE1", 0x5bac, 0 },
|
|
{ "LnH_STAT", 28, 3 },
|
|
{ "LnH_CMD", 24, 3 },
|
|
{ "LnG_STAT", 20, 3 },
|
|
{ "LnG_CMD", 16, 3 },
|
|
{ "LnF_STAT", 12, 3 },
|
|
{ "LnF_CMD", 8, 3 },
|
|
{ "LnE_STAT", 4, 3 },
|
|
{ "LnE_CMD", 0, 3 },
|
|
{ "PCIE_PHY_FS_LF0", 0x5bb0, 0 },
|
|
{ "Lane1LF", 24, 6 },
|
|
{ "Lane1FS", 16, 6 },
|
|
{ "Lane0LF", 8, 6 },
|
|
{ "Lane0FS", 0, 6 },
|
|
{ "PCIE_PHY_FS_LF1", 0x5bb4, 0 },
|
|
{ "Lane3LF", 24, 6 },
|
|
{ "Lane3FS", 16, 6 },
|
|
{ "Lane2LF", 8, 6 },
|
|
{ "Lane2FS", 0, 6 },
|
|
{ "PCIE_PHY_FS_LF2", 0x5bb8, 0 },
|
|
{ "Lane5LF", 24, 6 },
|
|
{ "Lane5FS", 16, 6 },
|
|
{ "Lane4LF", 8, 6 },
|
|
{ "Lane4FS", 0, 6 },
|
|
{ "PCIE_PHY_FS_LF3", 0x5bbc, 0 },
|
|
{ "Lane7LF", 24, 6 },
|
|
{ "Lane7FS", 16, 6 },
|
|
{ "Lane6LF", 8, 6 },
|
|
{ "Lane6FS", 0, 6 },
|
|
{ "PCIE_PHY_PRESET_REQ", 0x5bc0, 0 },
|
|
{ "CoeffDone", 16, 1 },
|
|
{ "CoeffLane", 8, 4 },
|
|
{ "CoeffStart", 0, 1 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bc4, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bc8, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bcc, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bd0, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bd4, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bd8, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bdc, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5be0, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5be4, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5be8, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bec, 0 },
|
|
{ "PCIE_PHY_INDIR_REQ", 0x5bf0, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "RegAddr", 0, 16 },
|
|
{ "PCIE_PHY_INDIR_DATA", 0x5bf4, 0 },
|
|
{ "PCIE_STATIC_SPARE1", 0x5bf8, 0 },
|
|
{ "PCIE_STATIC_SPARE2", 0x5bfc, 0 },
|
|
{ "PCIE_KDOORBELL_GTS_PF_BASE_LEN", 0x5c10, 0 },
|
|
{ "KDB_PF_Len", 24, 5 },
|
|
{ "KDB_PF_BaseAddr", 0, 20 },
|
|
{ "PCIE_KDOORBELL_GTS_VF_BASE_LEN", 0x5c14, 0 },
|
|
{ "KDB_VF_Len", 24, 5 },
|
|
{ "KDB_VF_BaseAddr", 0, 20 },
|
|
{ "PCIE_KDOORBELL_GTS_VF_OFFSET", 0x5c18, 0 },
|
|
{ "PCIE_PHY_REQRXPWR1", 0x5c1c, 0 },
|
|
{ "Req_LnP_RxStateDone", 31, 1 },
|
|
{ "Req_LnP_RxStateReq", 30, 1 },
|
|
{ "Req_LnP_RxPwrState", 28, 2 },
|
|
{ "Req_LnO_RxStateDone", 27, 1 },
|
|
{ "Req_LnO_RxStateReq", 26, 1 },
|
|
{ "Req_LnO_RxPwrState", 24, 2 },
|
|
{ "Req_LnN_RxStateDone", 23, 1 },
|
|
{ "Req_LnN_RxStateReq", 22, 1 },
|
|
{ "Req_LnN_RxPwrState", 20, 2 },
|
|
{ "Req_LnM_RxStateDone", 19, 1 },
|
|
{ "Req_LnM_RxStateReq", 18, 1 },
|
|
{ "Req_LnM_RxPwrState", 16, 2 },
|
|
{ "Req_LnL_RxStateDone", 15, 1 },
|
|
{ "Req_LnL_RxStateReq", 14, 1 },
|
|
{ "Req_LnL_RxPwrState", 12, 2 },
|
|
{ "Req_LnK_RxStateDone", 11, 1 },
|
|
{ "Req_LnK_RxStateReq", 10, 1 },
|
|
{ "Req_LnK_RxPwrState", 8, 2 },
|
|
{ "Req_LnJ_RxStateDone", 7, 1 },
|
|
{ "Req_LnJ_RxStateReq", 6, 1 },
|
|
{ "Req_LnJ_RxPwrState", 4, 2 },
|
|
{ "Req_LnI_RxStateDone", 3, 1 },
|
|
{ "Req_LnI_RxStateReq", 2, 1 },
|
|
{ "Req_LnI_RxPwrState", 0, 2 },
|
|
{ "PCIE_PHY_CURRXPWR1", 0x5c20, 0 },
|
|
{ "Cur_LnP_RxPwrState", 28, 3 },
|
|
{ "Cur_LnO_RxPwrState", 24, 3 },
|
|
{ "Cur_LnN_RxPwrState", 20, 3 },
|
|
{ "Cur_LnM_RxPwrState", 16, 3 },
|
|
{ "Cur_LnL_RxPwrState", 12, 3 },
|
|
{ "Cur_LnK_RxPwrState", 8, 3 },
|
|
{ "Cur_LnJ_RxPwrState", 4, 3 },
|
|
{ "Cur_LnI_RxPwrState", 0, 3 },
|
|
{ "PCIE_PHY_GEN3_AE2", 0x5c24, 0 },
|
|
{ "LnL_STAT", 28, 3 },
|
|
{ "LnL_CMD", 24, 3 },
|
|
{ "LnK_STAT", 20, 3 },
|
|
{ "LnK_CMD", 16, 3 },
|
|
{ "LnJ_STAT", 12, 3 },
|
|
{ "LnJ_CMD", 8, 3 },
|
|
{ "LnI_STAT", 4, 3 },
|
|
{ "LnI_CMD", 0, 3 },
|
|
{ "PCIE_PHY_GEN3_AE3", 0x5c28, 0 },
|
|
{ "LnP_STAT", 28, 3 },
|
|
{ "LnP_CMD", 24, 3 },
|
|
{ "LnO_STAT", 20, 3 },
|
|
{ "LnO_CMD", 16, 3 },
|
|
{ "LnN_STAT", 12, 3 },
|
|
{ "LnN_CMD", 8, 3 },
|
|
{ "LnM_STAT", 4, 3 },
|
|
{ "LnM_CMD", 0, 3 },
|
|
{ "PCIE_PHY_FS_LF4", 0x5c2c, 0 },
|
|
{ "Lane9LF", 24, 6 },
|
|
{ "Lane9FS", 16, 6 },
|
|
{ "Lane8LF", 8, 6 },
|
|
{ "Lane8FS", 0, 6 },
|
|
{ "PCIE_PHY_FS_LF5", 0x5c30, 0 },
|
|
{ "Lane11LF", 24, 6 },
|
|
{ "Lane11FS", 16, 6 },
|
|
{ "Lane10LF", 8, 6 },
|
|
{ "Lane10FS", 0, 6 },
|
|
{ "PCIE_PHY_FS_LF6", 0x5c34, 0 },
|
|
{ "Lane13LF", 24, 6 },
|
|
{ "Lane13FS", 16, 6 },
|
|
{ "Lane12LF", 8, 6 },
|
|
{ "Lane12FS", 0, 6 },
|
|
{ "PCIE_PHY_FS_LF7", 0x5c38, 0 },
|
|
{ "Lane15LF", 24, 6 },
|
|
{ "Lane15FS", 16, 6 },
|
|
{ "Lane14LF", 8, 6 },
|
|
{ "Lane14FS", 0, 6 },
|
|
{ "PCIE_MULTI_PHY_INDIR_REQ", 0x5c3c, 0 },
|
|
{ "Phy_Reg_Enable", 31, 1 },
|
|
{ "Phy_Reg_Select", 22, 2 },
|
|
{ "Phy_Reg_RegAddr", 0, 16 },
|
|
{ "PCIE_MULTI_PHY_INDIR_DATA", 0x5c40, 0 },
|
|
{ "PCIE_VF_INT_INDIR_REQ", 0x5c44, 0 },
|
|
{ "Enable", 24, 1 },
|
|
{ "AI", 23, 1 },
|
|
{ "VFID", 0, 10 },
|
|
{ "PCIE_VF_INT_INDIR_DATA", 0x5c48, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c4c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c50, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c54, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c58, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c5c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c60, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c64, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c68, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c6c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c70, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c74, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c78, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c7c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c80, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c84, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c88, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c8c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c90, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c94, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c98, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5c9c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5ca0, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5ca4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5ca8, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cb0, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cb4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cb8, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cbc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cc0, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cc4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cc8, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5ccc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cd0, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cd4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cd8, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cdc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5ce0, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5ce4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5ce8, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cf0, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cf4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cf8, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5cfc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d00, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d04, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d08, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d0c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d10, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d14, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d18, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d1c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d20, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d24, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d28, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d2c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d30, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d34, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d38, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d3c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d40, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d44, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d48, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d4c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d50, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d54, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d58, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d5c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d60, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d64, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d68, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d6c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d70, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d74, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d78, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d7c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d80, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d84, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d88, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d8c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d90, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d94, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d98, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5d9c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5da0, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5da4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5da8, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5dac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5db0, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5db4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5db8, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5dbc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5dc0, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5dc4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5dc8, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5dcc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5dd0, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5dd4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5dd8, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5ddc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5de0, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5de4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5de8, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5dec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5df0, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5df4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5df8, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5dfc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e00, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e04, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e08, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e0c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e10, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e14, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e18, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e1c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e20, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e24, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e28, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e2c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e30, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e34, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e38, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e3c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e40, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e44, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_256_INT_CFG2", 0x5e48, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_MSI_EN_4", 0x5e50, 0 },
|
|
{ "PCIE_VF_MSI_EN_5", 0x5e54, 0 },
|
|
{ "PCIE_VF_MSI_EN_6", 0x5e58, 0 },
|
|
{ "PCIE_VF_MSI_EN_7", 0x5e5c, 0 },
|
|
{ "PCIE_VF_MSIX_EN_4", 0x5e60, 0 },
|
|
{ "PCIE_VF_MSIX_EN_5", 0x5e64, 0 },
|
|
{ "PCIE_VF_MSIX_EN_6", 0x5e68, 0 },
|
|
{ "PCIE_VF_MSIX_EN_7", 0x5e6c, 0 },
|
|
{ "PCIE_FLR_VF4_STATUS", 0x5e70, 0 },
|
|
{ "PCIE_FLR_VF5_STATUS", 0x5e74, 0 },
|
|
{ "PCIE_FLR_VF6_STATUS", 0x5e78, 0 },
|
|
{ "PCIE_FLR_VF7_STATUS", 0x5e7c, 0 },
|
|
{ "PCIE_BUS_MST_STAT_4", 0x5e80, 0 },
|
|
{ "PCIE_BUS_MST_STAT_5", 0x5e84, 0 },
|
|
{ "PCIE_BUS_MST_STAT_6", 0x5e88, 0 },
|
|
{ "PCIE_BUS_MST_STAT_7", 0x5e8c, 0 },
|
|
{ "PCIE_BUS_MST_STAT_8", 0x5e90, 0 },
|
|
{ "PCIE_TGT_SKID_FIFO", 0x5e94, 0 },
|
|
{ "HdrFreeCnt", 16, 12 },
|
|
{ "DataFreeCnt", 0, 12 },
|
|
{ "PCIE_RSP_ERR_STAT_4", 0x5ea0, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_5", 0x5ea4, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_6", 0x5ea8, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_7", 0x5eac, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_8", 0x5eb0, 0 },
|
|
{ "PCIE_PHY_STAT1", 0x5ec0, 0 },
|
|
{ "PHY0_RTune_Ack", 31, 1 },
|
|
{ "PHY1_RTune_Ack", 30, 1 },
|
|
{ "PCIE_PHY_CTRL1", 0x5ec4, 0 },
|
|
{ "PHY0_RTune_Req", 31, 1 },
|
|
{ "PHY1_RTune_Req", 30, 1 },
|
|
{ "TxDeemph_gen1", 16, 8 },
|
|
{ "TxDeemph_gen2_3p5db", 8, 8 },
|
|
{ "TxDeemph_gen2_6db", 0, 8 },
|
|
{ "PCIE_PCIE_SPARE0", 0x5ec8, 0 },
|
|
{ "PCIE_RESET_STAT", 0x5ecc, 0 },
|
|
{ "PON_RST_STATE_flag", 11, 1 },
|
|
{ "BUS_RST_STATE_flag", 10, 1 },
|
|
{ "DL_DOWN_PCIeCRST_MODE0_STATE_flag", 9, 1 },
|
|
{ "DL_DOWN_PCIeCRST_MODE1_STATE_flag", 8, 1 },
|
|
{ "PCIe_WARM_RST_MODE0_STATE_flag", 7, 1 },
|
|
{ "PCIe_WARM_RST_MODE1_STATE_flag", 6, 1 },
|
|
{ "PIO_WARM_RST_MODE0_STATE_flag", 5, 1 },
|
|
{ "PIO_WARM_RST_MODE1_STATE_flag", 4, 1 },
|
|
{ "LastResetState", 0, 3 },
|
|
{ "PCIE_FUNC_DSTATE", 0x5ed0, 0 },
|
|
{ "PF7_DState", 21, 3 },
|
|
{ "PF6_DState", 18, 3 },
|
|
{ "PF5_DState", 15, 3 },
|
|
{ "PF4_DState", 12, 3 },
|
|
{ "PF3_DState", 9, 3 },
|
|
{ "PF2_DState", 6, 3 },
|
|
{ "PF1_DState", 3, 3 },
|
|
{ "PF0_DState", 0, 3 },
|
|
{ "PCIE_DEBUG_ADDR_RANGE1", 0x5ee0, 0 },
|
|
{ "PCIE_DEBUG_ADDR_RANGE2", 0x5ef0, 0 },
|
|
{ "PCIE_DEBUG_ADDR_RANGE_CNT", 0x5f00, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_dbg_regs[] = {
|
|
{ "DBG_DBG0_CFG", 0x6000, 0 },
|
|
{ "ModuleSelect", 12, 8 },
|
|
{ "RegSelect", 4, 8 },
|
|
{ "ClkSelect", 0, 4 },
|
|
{ "DBG_DBG0_EN", 0x6004, 0 },
|
|
{ "SDRHalfWord0", 8, 1 },
|
|
{ "DDREn", 4, 1 },
|
|
{ "PortEn", 0, 1 },
|
|
{ "DBG_DBG1_CFG", 0x6008, 0 },
|
|
{ "ModuleSelect", 12, 8 },
|
|
{ "RegSelect", 4, 8 },
|
|
{ "ClkSelect", 0, 4 },
|
|
{ "DBG_DBG1_EN", 0x600c, 0 },
|
|
{ "Clk_en_on_dbg1", 20, 1 },
|
|
{ "SDRHalfWord0", 8, 1 },
|
|
{ "DDREn", 4, 1 },
|
|
{ "PortEn", 0, 1 },
|
|
{ "DBG_GPIO_EN", 0x6010, 0 },
|
|
{ "GPIO15_OEn", 31, 1 },
|
|
{ "GPIO14_OEn", 30, 1 },
|
|
{ "GPIO13_OEn", 29, 1 },
|
|
{ "GPIO12_OEn", 28, 1 },
|
|
{ "GPIO11_OEn", 27, 1 },
|
|
{ "GPIO10_OEn", 26, 1 },
|
|
{ "GPIO9_OEn", 25, 1 },
|
|
{ "GPIO8_OEn", 24, 1 },
|
|
{ "GPIO7_OEn", 23, 1 },
|
|
{ "GPIO6_OEn", 22, 1 },
|
|
{ "GPIO5_OEn", 21, 1 },
|
|
{ "GPIO4_OEn", 20, 1 },
|
|
{ "GPIO3_OEn", 19, 1 },
|
|
{ "GPIO2_OEn", 18, 1 },
|
|
{ "GPIO1_OEn", 17, 1 },
|
|
{ "GPIO0_OEn", 16, 1 },
|
|
{ "GPIO15_Out_Val", 15, 1 },
|
|
{ "GPIO14_Out_Val", 14, 1 },
|
|
{ "GPIO13_Out_Val", 13, 1 },
|
|
{ "GPIO12_Out_Val", 12, 1 },
|
|
{ "GPIO11_Out_Val", 11, 1 },
|
|
{ "GPIO10_Out_Val", 10, 1 },
|
|
{ "GPIO9_Out_Val", 9, 1 },
|
|
{ "GPIO8_Out_Val", 8, 1 },
|
|
{ "GPIO7_Out_Val", 7, 1 },
|
|
{ "GPIO6_Out_Val", 6, 1 },
|
|
{ "GPIO5_Out_Val", 5, 1 },
|
|
{ "GPIO4_Out_Val", 4, 1 },
|
|
{ "GPIO3_Out_Val", 3, 1 },
|
|
{ "GPIO2_Out_Val", 2, 1 },
|
|
{ "GPIO1_Out_Val", 1, 1 },
|
|
{ "GPIO0_Out_Val", 0, 1 },
|
|
{ "DBG_GPIO_IN", 0x6014, 0 },
|
|
{ "GPIO15_CHG_DET", 31, 1 },
|
|
{ "GPIO14_CHG_DET", 30, 1 },
|
|
{ "GPIO13_CHG_DET", 29, 1 },
|
|
{ "GPIO12_CHG_DET", 28, 1 },
|
|
{ "GPIO11_CHG_DET", 27, 1 },
|
|
{ "GPIO10_CHG_DET", 26, 1 },
|
|
{ "GPIO9_CHG_DET", 25, 1 },
|
|
{ "GPIO8_CHG_DET", 24, 1 },
|
|
{ "GPIO7_CHG_DET", 23, 1 },
|
|
{ "GPIO6_CHG_DET", 22, 1 },
|
|
{ "GPIO5_CHG_DET", 21, 1 },
|
|
{ "GPIO4_CHG_DET", 20, 1 },
|
|
{ "GPIO3_CHG_DET", 19, 1 },
|
|
{ "GPIO2_CHG_DET", 18, 1 },
|
|
{ "GPIO1_CHG_DET", 17, 1 },
|
|
{ "GPIO0_CHG_DET", 16, 1 },
|
|
{ "GPIO15_IN", 15, 1 },
|
|
{ "GPIO14_IN", 14, 1 },
|
|
{ "GPIO13_IN", 13, 1 },
|
|
{ "GPIO12_IN", 12, 1 },
|
|
{ "GPIO11_IN", 11, 1 },
|
|
{ "GPIO10_IN", 10, 1 },
|
|
{ "GPIO9_IN", 9, 1 },
|
|
{ "GPIO8_IN", 8, 1 },
|
|
{ "GPIO7_IN", 7, 1 },
|
|
{ "GPIO6_IN", 6, 1 },
|
|
{ "GPIO5_IN", 5, 1 },
|
|
{ "GPIO4_IN", 4, 1 },
|
|
{ "GPIO3_IN", 3, 1 },
|
|
{ "GPIO2_IN", 2, 1 },
|
|
{ "GPIO1_IN", 1, 1 },
|
|
{ "GPIO0_IN", 0, 1 },
|
|
{ "DBG_GPIO_EN_NEW", 0x6100, 0 },
|
|
{ "GPIO16_OEn", 7, 1 },
|
|
{ "GPIO17_OEn", 6, 1 },
|
|
{ "GPIO18_OEn", 5, 1 },
|
|
{ "GPIO19_OEn", 4, 1 },
|
|
{ "GPIO16_Out_Val", 3, 1 },
|
|
{ "GPIO17_Out_Val", 2, 1 },
|
|
{ "GPIO18_Out_Val", 1, 1 },
|
|
{ "GPIO19_Out_Val", 0, 1 },
|
|
{ "DBG_GPIO_IN_NEW", 0x6104, 0 },
|
|
{ "GPIO16_CHG_DET", 7, 1 },
|
|
{ "GPIO17_CHG_DET", 6, 1 },
|
|
{ "GPIO18_CHG_DET", 5, 1 },
|
|
{ "GPIO19_CHG_DET", 4, 1 },
|
|
{ "GPIO19_IN", 3, 1 },
|
|
{ "GPIO18_IN", 2, 1 },
|
|
{ "GPIO17_IN", 1, 1 },
|
|
{ "GPIO16_IN", 0, 1 },
|
|
{ "DBG_INT_ENABLE", 0x6018, 0 },
|
|
{ "GPIO19", 29, 1 },
|
|
{ "GPIO18", 28, 1 },
|
|
{ "GPIO17", 27, 1 },
|
|
{ "GPIO16", 26, 1 },
|
|
{ "IBM_FDL_FAIL_int_enbl", 25, 1 },
|
|
{ "pll_lock_lost_int_enbl", 22, 1 },
|
|
{ "C_LOCK", 21, 1 },
|
|
{ "M_LOCK", 20, 1 },
|
|
{ "U_LOCK", 19, 1 },
|
|
{ "PCIe_LOCK", 18, 1 },
|
|
{ "KX_LOCK", 17, 1 },
|
|
{ "KR_LOCK", 16, 1 },
|
|
{ "GPIO15", 15, 1 },
|
|
{ "GPIO14", 14, 1 },
|
|
{ "GPIO13", 13, 1 },
|
|
{ "GPIO12", 12, 1 },
|
|
{ "GPIO11", 11, 1 },
|
|
{ "GPIO10", 10, 1 },
|
|
{ "GPIO9", 9, 1 },
|
|
{ "GPIO8", 8, 1 },
|
|
{ "GPIO7", 7, 1 },
|
|
{ "GPIO6", 6, 1 },
|
|
{ "GPIO5", 5, 1 },
|
|
{ "GPIO4", 4, 1 },
|
|
{ "GPIO3", 3, 1 },
|
|
{ "GPIO2", 2, 1 },
|
|
{ "GPIO1", 1, 1 },
|
|
{ "GPIO0", 0, 1 },
|
|
{ "DBG_INT_CAUSE", 0x601c, 0 },
|
|
{ "GPIO19", 29, 1 },
|
|
{ "GPIO18", 28, 1 },
|
|
{ "GPIO17", 27, 1 },
|
|
{ "GPIO16", 26, 1 },
|
|
{ "IBM_FDL_FAIL_int_cause", 25, 1 },
|
|
{ "pll_lock_lost_int_cause", 22, 1 },
|
|
{ "C_LOCK", 21, 1 },
|
|
{ "M_LOCK", 20, 1 },
|
|
{ "U_LOCK", 19, 1 },
|
|
{ "PCIe_LOCK", 18, 1 },
|
|
{ "KX_LOCK", 17, 1 },
|
|
{ "KR_LOCK", 16, 1 },
|
|
{ "GPIO15", 15, 1 },
|
|
{ "GPIO14", 14, 1 },
|
|
{ "GPIO13", 13, 1 },
|
|
{ "GPIO12", 12, 1 },
|
|
{ "GPIO11", 11, 1 },
|
|
{ "GPIO10", 10, 1 },
|
|
{ "GPIO9", 9, 1 },
|
|
{ "GPIO8", 8, 1 },
|
|
{ "GPIO7", 7, 1 },
|
|
{ "GPIO6", 6, 1 },
|
|
{ "GPIO5", 5, 1 },
|
|
{ "GPIO4", 4, 1 },
|
|
{ "GPIO3", 3, 1 },
|
|
{ "GPIO2", 2, 1 },
|
|
{ "GPIO1", 1, 1 },
|
|
{ "GPIO0", 0, 1 },
|
|
{ "DBG_DBG0_RST_VALUE", 0x6020, 0 },
|
|
{ "DBG_PLL_OCLK_PAD_EN", 0x6028, 0 },
|
|
{ "PCIE_OCLK_En", 20, 1 },
|
|
{ "KX_OCLK_En", 16, 1 },
|
|
{ "U_OCLK_En", 12, 1 },
|
|
{ "KR_OCLK_En", 8, 1 },
|
|
{ "M_OCLK_En", 4, 1 },
|
|
{ "C_OCLK_En", 0, 1 },
|
|
{ "DBG_PLL_LOCK", 0x602c, 0 },
|
|
{ "P_LOCK", 20, 1 },
|
|
{ "KX_LOCK", 16, 1 },
|
|
{ "U_LOCK", 12, 1 },
|
|
{ "KR_LOCK", 8, 1 },
|
|
{ "M_LOCK", 4, 1 },
|
|
{ "C_LOCK", 0, 1 },
|
|
{ "DBG_GPIO_ACT_LOW", 0x6030, 0 },
|
|
{ "GPIO19_ACT_LOW", 25, 1 },
|
|
{ "GPIO18_ACT_LOW", 24, 1 },
|
|
{ "GPIO17_ACT_LOW", 23, 1 },
|
|
{ "GPIO16_ACT_LOW", 22, 1 },
|
|
{ "P_LOCK_ACT_LOW", 21, 1 },
|
|
{ "C_LOCK_ACT_LOW", 20, 1 },
|
|
{ "M_LOCK_ACT_LOW", 19, 1 },
|
|
{ "U_LOCK_ACT_LOW", 18, 1 },
|
|
{ "KR_LOCK_ACT_LOW", 17, 1 },
|
|
{ "KX_LOCK_ACT_LOW", 16, 1 },
|
|
{ "GPIO15_ACT_LOW", 15, 1 },
|
|
{ "GPIO14_ACT_LOW", 14, 1 },
|
|
{ "GPIO13_ACT_LOW", 13, 1 },
|
|
{ "GPIO12_ACT_LOW", 12, 1 },
|
|
{ "GPIO11_ACT_LOW", 11, 1 },
|
|
{ "GPIO10_ACT_LOW", 10, 1 },
|
|
{ "GPIO9_ACT_LOW", 9, 1 },
|
|
{ "GPIO8_ACT_LOW", 8, 1 },
|
|
{ "GPIO7_ACT_LOW", 7, 1 },
|
|
{ "GPIO6_ACT_LOW", 6, 1 },
|
|
{ "GPIO5_ACT_LOW", 5, 1 },
|
|
{ "GPIO4_ACT_LOW", 4, 1 },
|
|
{ "GPIO3_ACT_LOW", 3, 1 },
|
|
{ "GPIO2_ACT_LOW", 2, 1 },
|
|
{ "GPIO1_ACT_LOW", 1, 1 },
|
|
{ "GPIO0_ACT_LOW", 0, 1 },
|
|
{ "DBG_EFUSE_BYTE0_3", 0x6034, 0 },
|
|
{ "DBG_EFUSE_BYTE4_7", 0x6038, 0 },
|
|
{ "DBG_EFUSE_BYTE8_11", 0x603c, 0 },
|
|
{ "DBG_EFUSE_BYTE12_15", 0x6040, 0 },
|
|
{ "DBG_EXTRA_STATIC_BITS_CONF", 0x6058, 0 },
|
|
{ "STATIC_M_PLL_RESET", 30, 1 },
|
|
{ "STATIC_M_PLL_SLEEP", 29, 1 },
|
|
{ "STATIC_M_PLL_BYPASS", 28, 1 },
|
|
{ "STATIC_MPLL_CLK_SEL", 27, 1 },
|
|
{ "STATIC_U_PLL_SLEEP", 26, 1 },
|
|
{ "STATIC_C_PLL_SLEEP", 25, 1 },
|
|
{ "STATIC_LVDS_CLKOUT_SEL", 23, 2 },
|
|
{ "STATIC_LVDS_CLKOUT_EN", 22, 1 },
|
|
{ "STATIC_CCLK_FREQ_SEL", 20, 2 },
|
|
{ "STATIC_UCLK_FREQ_SEL", 18, 2 },
|
|
{ "ExPHYClk_sel_en", 17, 1 },
|
|
{ "ExPHYClk_sel", 15, 2 },
|
|
{ "STATIC_U_PLL_BYPASS", 14, 1 },
|
|
{ "STATIC_C_PLL_BYPASS", 13, 1 },
|
|
{ "STATIC_KR_PLL_BYPASS", 12, 1 },
|
|
{ "STATIC_KX_PLL_BYPASS", 11, 1 },
|
|
{ "STATIC_KX_PLL_V", 7, 4 },
|
|
{ "STATIC_KR_PLL_V", 3, 4 },
|
|
{ "DBG_STATIC_OCLK_MUXSEL_CONF", 0x605c, 0 },
|
|
{ "P_OCLK_MUXSEL", 13, 4 },
|
|
{ "M_OCLK_MUXSEL", 12, 1 },
|
|
{ "C_OCLK_MUXSEL", 10, 2 },
|
|
{ "U_OCLK_MUXSEL", 8, 2 },
|
|
{ "KX_OCLK_MUXSEL", 3, 3 },
|
|
{ "KR_OCLK_MUXSEL", 0, 3 },
|
|
{ "DBG_TRACE0_CONF_COMPREG0", 0x6060, 0 },
|
|
{ "DBG_TRACE0_CONF_COMPREG1", 0x6064, 0 },
|
|
{ "DBG_TRACE1_CONF_COMPREG0", 0x6068, 0 },
|
|
{ "DBG_TRACE1_CONF_COMPREG1", 0x606c, 0 },
|
|
{ "DBG_TRACE0_CONF_MASKREG0", 0x6070, 0 },
|
|
{ "DBG_TRACE0_CONF_MASKREG1", 0x6074, 0 },
|
|
{ "DBG_TRACE1_CONF_MASKREG0", 0x6078, 0 },
|
|
{ "DBG_TRACE1_CONF_MASKREG1", 0x607c, 0 },
|
|
{ "DBG_TRACE_COUNTER", 0x6080, 0 },
|
|
{ "Counter1", 16, 16 },
|
|
{ "Counter0", 0, 16 },
|
|
{ "DBG_STATIC_REFCLK_PERIOD", 0x6084, 0 },
|
|
{ "DBG_TRACE_CONF", 0x6088, 0 },
|
|
{ "dbg_trace_operate_with_trg", 5, 1 },
|
|
{ "dbg_trace_operate_en", 4, 1 },
|
|
{ "dbg_operate_indv_combined", 3, 1 },
|
|
{ "dbg_operate_order_of_trigger", 2, 1 },
|
|
{ "dbg_operate_sgl_dbl_trigger", 1, 1 },
|
|
{ "dbg_operate0_or_1", 0, 1 },
|
|
{ "DBG_TRACE_RDEN", 0x608c, 0 },
|
|
{ "RD_ADDR1", 11, 9 },
|
|
{ "RD_ADDR0", 2, 9 },
|
|
{ "Rd_en1", 1, 1 },
|
|
{ "Rd_en0", 0, 1 },
|
|
{ "DBG_TRACE_WRADDR", 0x6090, 0 },
|
|
{ "Wr_pointer_addr1", 16, 9 },
|
|
{ "Wr_pointer_addr0", 0, 9 },
|
|
{ "DBG_TRACE0_DATA_OUT", 0x6094, 0 },
|
|
{ "DBG_TRACE1_DATA_OUT", 0x6098, 0 },
|
|
{ "DBG_FUSE_SENSE_DONE", 0x609c, 0 },
|
|
{ "PSRO_sel", 1, 4 },
|
|
{ "FUSE_DONE_SENSE", 0, 1 },
|
|
{ "DBG_TVSENSE_EN", 0x60a8, 0 },
|
|
{ "MCIMPED1_out", 29, 1 },
|
|
{ "MCIMPED2_out", 28, 1 },
|
|
{ "TVSENSE_SNSOUT", 17, 9 },
|
|
{ "TVSENSE_OUTPUTVALID", 16, 1 },
|
|
{ "TVSENSE_SLEEP", 11, 1 },
|
|
{ "TVSENSE_SENSV", 10, 1 },
|
|
{ "TVSENSE_RST", 9, 1 },
|
|
{ "TVSENSE_RATIO", 0, 8 },
|
|
{ "DBG_CUST_EFUSE_OUT_EN", 0x60ac, 0 },
|
|
{ "DBG_CUST_EFUSE_SEL1_EN", 0x60b0, 0 },
|
|
{ "DBG_CUST_EFUSE_SEL2_EN", 0x60b4, 0 },
|
|
{ "DBG_FEENABLE", 29, 1 },
|
|
{ "DBG_FEF", 23, 6 },
|
|
{ "DBG_FEMIMICN", 22, 1 },
|
|
{ "DBG_FEGATEC", 21, 1 },
|
|
{ "DBG_FEPROGP", 20, 1 },
|
|
{ "DBG_FEREADCLK", 19, 1 },
|
|
{ "DBG_FERSEL", 3, 16 },
|
|
{ "DBG_FETIME", 0, 3 },
|
|
{ "DBG_STATIC_M_PLL_CONF1", 0x60b8, 0 },
|
|
{ "STATIC_M_PLL_MULTFRAC", 8, 24 },
|
|
{ "STATIC_M_PLL_FFSLEWRATE", 0, 8 },
|
|
{ "DBG_STATIC_M_PLL_CONF2", 0x60bc, 0 },
|
|
{ "STATIC_M_PLL_PREDIV", 24, 6 },
|
|
{ "STATIC_M_PLL_DCO_BYPASS", 23, 1 },
|
|
{ "STATIC_M_PLL_SDORDER", 21, 2 },
|
|
{ "STATIC_M_PLL_FFENABLE", 20, 1 },
|
|
{ "STATIC_M_PLL_STOPCLKB", 19, 1 },
|
|
{ "STATIC_M_PLL_STOPCLKA", 18, 1 },
|
|
{ "STATIC_M_PLL_SLEEP", 17, 1 },
|
|
{ "STATIC_M_PLL_BYPASS", 16, 1 },
|
|
{ "STATIC_M_PLL_LOCKTUNE", 0, 5 },
|
|
{ "DBG_STATIC_M_PLL_CONF3", 0x60c0, 0 },
|
|
{ "STATIC_M_PLL_MULTPRE", 30, 2 },
|
|
{ "STATIC_M_PLL_LOCKSEL", 28, 1 },
|
|
{ "STATIC_M_PLL_FFTUNE", 12, 16 },
|
|
{ "STATIC_M_PLL_RANGEPRE", 10, 2 },
|
|
{ "STATIC_M_PLL_RANGEB", 5, 5 },
|
|
{ "STATIC_M_PLL_RANGEA", 0, 5 },
|
|
{ "DBG_STATIC_M_PLL_CONF4", 0x60c4, 0 },
|
|
{ "DBG_STATIC_M_PLL_CONF5", 0x60c8, 0 },
|
|
{ "STATIC_M_PLL_VCVTUNE", 24, 3 },
|
|
{ "STATIC_M_PLL_RESET", 23, 1 },
|
|
{ "STATIC_MPLL_REFCLK_SEL", 22, 1 },
|
|
{ "STATIC_M_PLL_LFTUNE_32_40", 13, 9 },
|
|
{ "STATIC_M_PLL_MULT", 0, 8 },
|
|
{ "DBG_STATIC_M_PLL_CONF6", 0x60cc, 0 },
|
|
{ "STATIC_M_PLL_DIVCHANGE", 30, 1 },
|
|
{ "STATIC_M_PLL_FRAMESTOP", 29, 1 },
|
|
{ "STATIC_M_PLL_FASTSTOP", 28, 1 },
|
|
{ "STATIC_M_PLL_FFBYPASS", 27, 1 },
|
|
{ "STATIC_M_PLL_STARTUP", 25, 2 },
|
|
{ "STATIC_M_PLL_VREGTUNE", 6, 19 },
|
|
{ "STATIC_PHY0RecRst_", 5, 1 },
|
|
{ "STATIC_PHY1RecRst_", 4, 1 },
|
|
{ "STATIC_SWMC0Rst_", 3, 1 },
|
|
{ "STATIC_SWMC0CfgRst_", 2, 1 },
|
|
{ "STATIC_SWMC1Rst_", 1, 1 },
|
|
{ "STATIC_SWMC1CfgRst_", 0, 1 },
|
|
{ "DBG_STATIC_C_PLL_CONF1", 0x60d0, 0 },
|
|
{ "STATIC_C_PLL_MULTFRAC", 8, 24 },
|
|
{ "STATIC_C_PLL_FFSLEWRATE", 0, 8 },
|
|
{ "DBG_STATIC_C_PLL_CONF2", 0x60d4, 0 },
|
|
{ "STATIC_C_PLL_PREDIV", 26, 6 },
|
|
{ "STATIC_C_PLL_STARTUP", 24, 2 },
|
|
{ "STATIC_C_PLL_DCO_BYPASS", 23, 1 },
|
|
{ "STATIC_C_PLL_SDORDER", 21, 2 },
|
|
{ "STATIC_C_PLL_DIVCHANGE", 20, 1 },
|
|
{ "STATIC_C_PLL_STOPCLKB", 19, 1 },
|
|
{ "STATIC_C_PLL_STOPCLKA", 18, 1 },
|
|
{ "STATIC_C_PLL_SLEEP", 17, 1 },
|
|
{ "STATIC_C_PLL_BYPASS", 16, 1 },
|
|
{ "STATIC_C_PLL_LOCKTUNE", 0, 5 },
|
|
{ "DBG_STATIC_C_PLL_CONF3", 0x60d8, 0 },
|
|
{ "STATIC_C_PLL_MULTPRE", 30, 2 },
|
|
{ "STATIC_C_PLL_LOCKSEL", 28, 1 },
|
|
{ "STATIC_C_PLL_FFTUNE", 12, 16 },
|
|
{ "STATIC_C_PLL_RANGEPRE", 10, 2 },
|
|
{ "STATIC_C_PLL_RANGEB", 5, 5 },
|
|
{ "STATIC_C_PLL_RANGEA", 0, 5 },
|
|
{ "DBG_STATIC_C_PLL_CONF4", 0x60dc, 0 },
|
|
{ "DBG_STATIC_C_PLL_CONF5", 0x60e0, 0 },
|
|
{ "STATIC_C_PLL_FFBYPASS", 27, 1 },
|
|
{ "STATIC_C_PLL_FASTSTOP", 26, 1 },
|
|
{ "STATIC_C_PLL_FRAMESTOP", 25, 1 },
|
|
{ "STATIC_C_PLL_VCVTUNE", 22, 3 },
|
|
{ "STATIC_C_PLL_LFTUNE_32_40", 13, 9 },
|
|
{ "STATIC_C_PLL_PREDIV", 8, 5 },
|
|
{ "STATIC_C_PLL_MULT", 0, 8 },
|
|
{ "DBG_STATIC_U_PLL_CONF1", 0x60e4, 0 },
|
|
{ "STATIC_U_PLL_MULTFRAC", 8, 24 },
|
|
{ "STATIC_U_PLL_FFSLEWRATE", 0, 8 },
|
|
{ "DBG_STATIC_U_PLL_CONF2", 0x60e8, 0 },
|
|
{ "STATIC_U_PLL_PREDIV", 26, 6 },
|
|
{ "STATIC_U_PLL_STARTUP", 24, 2 },
|
|
{ "STATIC_U_PLL_DCO_BYPASS", 23, 1 },
|
|
{ "STATIC_U_PLL_SDORDER", 21, 2 },
|
|
{ "STATIC_U_PLL_DIVCHANGE", 20, 1 },
|
|
{ "STATIC_U_PLL_STOPCLKB", 19, 1 },
|
|
{ "STATIC_U_PLL_STOPCLKA", 18, 1 },
|
|
{ "STATIC_U_PLL_SLEEP", 17, 1 },
|
|
{ "STATIC_U_PLL_BYPASS", 16, 1 },
|
|
{ "STATIC_U_PLL_LOCKTUNE", 0, 5 },
|
|
{ "DBG_STATIC_U_PLL_CONF3", 0x60ec, 0 },
|
|
{ "STATIC_U_PLL_MULTPRE", 30, 2 },
|
|
{ "STATIC_U_PLL_LOCKSEL", 28, 1 },
|
|
{ "STATIC_U_PLL_FFTUNE", 12, 16 },
|
|
{ "STATIC_U_PLL_RANGEPRE", 10, 2 },
|
|
{ "STATIC_U_PLL_RANGEB", 5, 5 },
|
|
{ "STATIC_U_PLL_RANGEA", 0, 5 },
|
|
{ "DBG_STATIC_U_PLL_CONF4", 0x60f0, 0 },
|
|
{ "DBG_STATIC_U_PLL_CONF5", 0x60f4, 0 },
|
|
{ "STATIC_U_PLL_FFBYPASS", 27, 1 },
|
|
{ "STATIC_U_PLL_FASTSTOP", 26, 1 },
|
|
{ "STATIC_U_PLL_FRAMESTOP", 25, 1 },
|
|
{ "STATIC_U_PLL_VCVTUNE", 22, 3 },
|
|
{ "STATIC_U_PLL_LFTUNE_32_40", 13, 9 },
|
|
{ "STATIC_U_PLL_PREDIV", 8, 5 },
|
|
{ "STATIC_U_PLL_MULT", 0, 8 },
|
|
{ "DBG_STATIC_KR_PLL_CONF1", 0x60f8, 0 },
|
|
{ "STATIC_KR_PLL_BYPASS", 30, 1 },
|
|
{ "STATIC_KR_PLL_VBOOSTDIV", 27, 3 },
|
|
{ "STATIC_KR_PLL_CPISEL", 24, 3 },
|
|
{ "STATIC_KR_PLL_CCALMETHOD", 23, 1 },
|
|
{ "STATIC_KR_PLL_CCALLOAD", 22, 1 },
|
|
{ "STATIC_KR_PLL_CCALFMIN", 21, 1 },
|
|
{ "STATIC_KR_PLL_CCALFMAX", 20, 1 },
|
|
{ "STATIC_KR_PLL_CCALCVHOLD", 19, 1 },
|
|
{ "STATIC_KR_PLL_CCALBANDSEL", 15, 4 },
|
|
{ "STATIC_KR_PLL_BGOFFSET", 11, 4 },
|
|
{ "STATIC_KR_PLL_P", 8, 3 },
|
|
{ "STATIC_KR_PLL_N2", 4, 4 },
|
|
{ "STATIC_KR_PLL_N1", 0, 4 },
|
|
{ "DBG_STATIC_KR_PLL_CONF2", 0x60fc, 0 },
|
|
{ "STATIC_KR_PLL_M", 11, 9 },
|
|
{ "STATIC_KR_PLL_ANALOGTUNE", 0, 11 },
|
|
{ "DBG_STATIC_KX_PLL_CONF1", 0x6108, 0 },
|
|
{ "STATIC_KX_PLL_BYPASS", 30, 1 },
|
|
{ "STATIC_KX_PLL_VBOOSTDIV", 27, 3 },
|
|
{ "STATIC_KX_PLL_CPISEL", 24, 3 },
|
|
{ "STATIC_KX_PLL_CCALMETHOD", 23, 1 },
|
|
{ "STATIC_KX_PLL_CCALLOAD", 22, 1 },
|
|
{ "STATIC_KX_PLL_CCALFMIN", 21, 1 },
|
|
{ "STATIC_KX_PLL_CCALFMAX", 20, 1 },
|
|
{ "STATIC_KX_PLL_CCALCVHOLD", 19, 1 },
|
|
{ "STATIC_KX_PLL_CCALBANDSEL", 15, 4 },
|
|
{ "STATIC_KX_PLL_BGOFFSET", 11, 4 },
|
|
{ "STATIC_KX_PLL_P", 8, 3 },
|
|
{ "STATIC_KX_PLL_N2", 4, 4 },
|
|
{ "STATIC_KX_PLL_N1", 0, 4 },
|
|
{ "DBG_STATIC_KX_PLL_CONF2", 0x610c, 0 },
|
|
{ "STATIC_KX_PLL_M", 11, 9 },
|
|
{ "STATIC_KX_PLL_ANALOGTUNE", 0, 11 },
|
|
{ "DBG_STATIC_C_DFS_CONF", 0x6110, 0 },
|
|
{ "STATIC_C_DFS_RANGEA", 8, 5 },
|
|
{ "STATIC_C_DFS_RANGEB", 3, 5 },
|
|
{ "STATIC_C_DFS_FFTUNE4", 2, 1 },
|
|
{ "STATIC_C_DFS_FFTUNE5", 1, 1 },
|
|
{ "STATIC_C_DFS_ENABLE", 0, 1 },
|
|
{ "DBG_STATIC_U_DFS_CONF", 0x6114, 0 },
|
|
{ "STATIC_U_DFS_RANGEA", 8, 5 },
|
|
{ "STATIC_U_DFS_RANGEB", 3, 5 },
|
|
{ "STATIC_U_DFS_FFTUNE4", 2, 1 },
|
|
{ "STATIC_U_DFS_FFTUNE5", 1, 1 },
|
|
{ "STATIC_U_DFS_ENABLE", 0, 1 },
|
|
{ "DBG_GPIO_PE_EN", 0x6118, 0 },
|
|
{ "GPIO19_PE_En", 19, 1 },
|
|
{ "GPIO18_PE_En", 18, 1 },
|
|
{ "GPIO17_PE_En", 17, 1 },
|
|
{ "GPIO16_PE_En", 16, 1 },
|
|
{ "GPIO15_PE_En", 15, 1 },
|
|
{ "GPIO14_PE_En", 14, 1 },
|
|
{ "GPIO13_PE_En", 13, 1 },
|
|
{ "GPIO12_PE_En", 12, 1 },
|
|
{ "GPIO11_PE_En", 11, 1 },
|
|
{ "GPIO10_PE_En", 10, 1 },
|
|
{ "GPIO9_PE_En", 9, 1 },
|
|
{ "GPIO8_PE_En", 8, 1 },
|
|
{ "GPIO7_PE_En", 7, 1 },
|
|
{ "GPIO6_PE_En", 6, 1 },
|
|
{ "GPIO5_PE_En", 5, 1 },
|
|
{ "GPIO4_PE_En", 4, 1 },
|
|
{ "GPIO3_PE_En", 3, 1 },
|
|
{ "GPIO2_PE_En", 2, 1 },
|
|
{ "GPIO1_PE_En", 1, 1 },
|
|
{ "GPIO0_PE_En", 0, 1 },
|
|
{ "DBG_GPIO_PS_EN", 0x611c, 0 },
|
|
{ "GPIO19_PS_En", 19, 1 },
|
|
{ "GPIO18_PS_En", 18, 1 },
|
|
{ "GPIO17_PS_En", 17, 1 },
|
|
{ "GPIO16_PS_En", 16, 1 },
|
|
{ "GPIO15_PS_En", 15, 1 },
|
|
{ "GPIO14_PS_En", 14, 1 },
|
|
{ "GPIO13_PS_En", 13, 1 },
|
|
{ "GPIO12_PS_En", 12, 1 },
|
|
{ "GPIO11_PS_En", 11, 1 },
|
|
{ "GPIO10_PS_En", 10, 1 },
|
|
{ "GPIO9_PS_En", 9, 1 },
|
|
{ "GPIO8_PS_En", 8, 1 },
|
|
{ "GPIO7_PS_En", 7, 1 },
|
|
{ "GPIO6_PS_En", 6, 1 },
|
|
{ "GPIO5_PS_En", 5, 1 },
|
|
{ "GPIO4_PS_En", 4, 1 },
|
|
{ "GPIO3_PS_En", 3, 1 },
|
|
{ "GPIO2_PS_En", 2, 1 },
|
|
{ "GPIO1_PS_En", 1, 1 },
|
|
{ "GPIO0_PS_En", 0, 1 },
|
|
{ "DBG_EFUSE_BYTE16_19", 0x6120, 0 },
|
|
{ "DBG_EFUSE_BYTE20_23", 0x6124, 0 },
|
|
{ "DBG_EFUSE_BYTE24_27", 0x6128, 0 },
|
|
{ "DBG_EFUSE_BYTE28_31", 0x612c, 0 },
|
|
{ "DBG_EFUSE_BYTE32_35", 0x6130, 0 },
|
|
{ "DBG_EFUSE_BYTE36_39", 0x6134, 0 },
|
|
{ "DBG_EFUSE_BYTE40_43", 0x6138, 0 },
|
|
{ "DBG_EFUSE_BYTE44_47", 0x613c, 0 },
|
|
{ "DBG_EFUSE_BYTE48_51", 0x6140, 0 },
|
|
{ "DBG_EFUSE_BYTE52_55", 0x6144, 0 },
|
|
{ "DBG_EFUSE_BYTE56_59", 0x6148, 0 },
|
|
{ "DBG_EFUSE_BYTE60_63", 0x614c, 0 },
|
|
{ "DBG_STATIC_U_PLL_CONF6", 0x6150, 0 },
|
|
{ "DBG_STATIC_C_PLL_CONF6", 0x6154, 0 },
|
|
{ "DBG_CUST_EFUSE_PROGRAM", 0x6158, 0 },
|
|
{ "EFUSE_PROG_PERIOD", 16, 16 },
|
|
{ "EFUSE_OPER_TYP", 14, 2 },
|
|
{ "EFUSE_ADDR", 8, 6 },
|
|
{ "EFUSE_DIN", 0, 8 },
|
|
{ "DBG_CUST_EFUSE_OUT", 0x615c, 0 },
|
|
{ "EFUSE_OPER_DONE", 8, 1 },
|
|
{ "EFUSE_DOUT", 0, 8 },
|
|
{ "DBG_CUST_EFUSE_BYTE0_3", 0x6160, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE4_7", 0x6164, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE8_11", 0x6168, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE12_15", 0x616c, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE16_19", 0x6170, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE20_23", 0x6174, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE24_27", 0x6178, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE28_31", 0x617c, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE32_35", 0x6180, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE36_39", 0x6184, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE40_43", 0x6188, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE44_47", 0x618c, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE48_51", 0x6190, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE52_55", 0x6194, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE56_59", 0x6198, 0 },
|
|
{ "DBG_CUST_EFUSE_BYTE60_63", 0x619c, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_ma_regs[] = {
|
|
{ "MA_CLIENT0_RD_LATENCY_THRESHOLD", 0x7700, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT0_WR_LATENCY_THRESHOLD", 0x7704, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT1_RD_LATENCY_THRESHOLD", 0x7708, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT1_WR_LATENCY_THRESHOLD", 0x770c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT2_RD_LATENCY_THRESHOLD", 0x7710, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT2_WR_LATENCY_THRESHOLD", 0x7714, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT3_RD_LATENCY_THRESHOLD", 0x7718, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT3_WR_LATENCY_THRESHOLD", 0x771c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT4_RD_LATENCY_THRESHOLD", 0x7720, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT4_WR_LATENCY_THRESHOLD", 0x7724, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT5_RD_LATENCY_THRESHOLD", 0x7728, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT5_WR_LATENCY_THRESHOLD", 0x772c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT6_RD_LATENCY_THRESHOLD", 0x7730, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT6_WR_LATENCY_THRESHOLD", 0x7734, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT7_RD_LATENCY_THRESHOLD", 0x7738, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT7_WR_LATENCY_THRESHOLD", 0x773c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT8_RD_LATENCY_THRESHOLD", 0x7740, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT8_WR_LATENCY_THRESHOLD", 0x7744, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT9_RD_LATENCY_THRESHOLD", 0x7748, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT9_WR_LATENCY_THRESHOLD", 0x774c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT10_RD_LATENCY_THRESHOLD", 0x7750, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT10_WR_LATENCY_THRESHOLD", 0x7754, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT11_RD_LATENCY_THRESHOLD", 0x7758, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT11_WR_LATENCY_THRESHOLD", 0x775c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT12_RD_LATENCY_THRESHOLD", 0x7760, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT12_WR_LATENCY_THRESHOLD", 0x7764, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_SGE_TH0_DEBUG_CNT", 0x7768, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_SGE_TH1_DEBUG_CNT", 0x776c, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_ULPTX_DEBUG_CNT", 0x7770, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_ULPRX_DEBUG_CNT", 0x7774, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_ULPTXRX_DEBUG_CNT", 0x7778, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_TP_TH0_DEBUG_CNT", 0x777c, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_TP_TH1_DEBUG_CNT", 0x7780, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_LE_DEBUG_CNT", 0x7784, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_CIM_DEBUG_CNT", 0x7788, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_PCIE_DEBUG_CNT", 0x778c, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_PMTX_DEBUG_CNT", 0x7790, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_PMRX_DEBUG_CNT", 0x7794, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_HMA_DEBUG_CNT", 0x7798, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_EDRAM0_BAR", 0x77c0, 0 },
|
|
{ "EDRAM0_BASE", 16, 12 },
|
|
{ "EDRAM0_SIZE", 0, 12 },
|
|
{ "MA_EDRAM1_BAR", 0x77c4, 0 },
|
|
{ "EDRAM1_BASE", 16, 12 },
|
|
{ "EDRAM1_SIZE", 0, 12 },
|
|
{ "MA_EXT_MEMORY0_BAR", 0x77c8, 0 },
|
|
{ "EXT_MEM0_BASE", 16, 12 },
|
|
{ "EXT_MEM0_SIZE", 0, 12 },
|
|
{ "MA_HOST_MEMORY_BAR", 0x77cc, 0 },
|
|
{ "HMA_BASE", 16, 12 },
|
|
{ "HMA_SIZE", 0, 12 },
|
|
{ "MA_EXT_MEM_PAGE_SIZE", 0x77d0, 0 },
|
|
{ "BRBC_MODE", 4, 1 },
|
|
{ "BRC_MODE", 3, 1 },
|
|
{ "EXT_MEM_PAGE_SIZE", 0, 3 },
|
|
{ "MA_ARB_CTRL", 0x77d4, 0 },
|
|
{ "HMA_WRT_EN", 26, 1 },
|
|
{ "HMA_NUM_PG_128B_FDBK", 21, 5 },
|
|
{ "HMA_DIS_128B_PG_CNT_FDBK", 20, 1 },
|
|
{ "HMA_DIS_BG_ARB", 19, 1 },
|
|
{ "HMA_DIS_BANK_FAIR", 18, 1 },
|
|
{ "HMA_DIS_PAGE_HINT", 17, 1 },
|
|
{ "HMA_DIS_ADV_ARB", 16, 1 },
|
|
{ "NUM_PG_128B_FDBK", 5, 5 },
|
|
{ "DIS_128B_PG_CNT_FDBK", 4, 1 },
|
|
{ "DIS_BG_ARB", 3, 1 },
|
|
{ "DIS_BANK_FAIR", 2, 1 },
|
|
{ "DIS_PAGE_HINT", 1, 1 },
|
|
{ "DIS_ADV_ARB", 0, 1 },
|
|
{ "MA_TARGET_MEM_ENABLE", 0x77d8, 0 },
|
|
{ "MC_SPLIT", 6, 1 },
|
|
{ "HMA_MUX", 5, 1 },
|
|
{ "EXT_MEM1_ENABLE", 4, 1 },
|
|
{ "HMA_ENABLE", 3, 1 },
|
|
{ "EXT_MEM0_ENABLE", 2, 1 },
|
|
{ "EDRAM1_ENABLE", 1, 1 },
|
|
{ "EDRAM0_ENABLE", 0, 1 },
|
|
{ "MA_INT_ENABLE", 0x77dc, 0 },
|
|
{ "MEM_TO_INT_ENABLE", 2, 1 },
|
|
{ "MEM_PERR_INT_ENABLE", 1, 1 },
|
|
{ "MEM_WRAP_INT_ENABLE", 0, 1 },
|
|
{ "MA_INT_CAUSE", 0x77e0, 0 },
|
|
{ "MEM_TO_INT_CAUSE", 2, 1 },
|
|
{ "MEM_PERR_INT_CAUSE", 1, 1 },
|
|
{ "MEM_WRAP_INT_CAUSE", 0, 1 },
|
|
{ "MA_INT_WRAP_STATUS", 0x77e4, 0 },
|
|
{ "MEM_WRAP_ADDRESS", 4, 28 },
|
|
{ "MEM_WRAP_CLIENT_NUM", 0, 4 },
|
|
{ "MA_TP_THREAD1_MAPPER", 0x77e8, 0 },
|
|
{ "MA_SGE_THREAD1_MAPPER", 0x77ec, 0 },
|
|
{ "MA_PARITY_ERROR_ENABLE1", 0x77f0, 0 },
|
|
{ "TP_DMARBT_PAR_ERROR_EN", 31, 1 },
|
|
{ "LOGIC_FIFO_PAR_ERROR_EN", 30, 1 },
|
|
{ "ARB3_PAR_WRQUEUE_ERROR_EN", 29, 1 },
|
|
{ "ARB2_PAR_WRQUEUE_ERROR_EN", 28, 1 },
|
|
{ "ARB1_PAR_WRQUEUE_ERROR_EN", 27, 1 },
|
|
{ "ARB0_PAR_WRQUEUE_ERROR_EN", 26, 1 },
|
|
{ "ARB3_PAR_RDQUEUE_ERROR_EN", 25, 1 },
|
|
{ "ARB2_PAR_RDQUEUE_ERROR_EN", 24, 1 },
|
|
{ "ARB1_PAR_RDQUEUE_ERROR_EN", 23, 1 },
|
|
{ "ARB0_PAR_RDQUEUE_ERROR_EN", 22, 1 },
|
|
{ "CL10_PAR_WRQUEUE_ERROR_EN", 21, 1 },
|
|
{ "CL9_PAR_WRQUEUE_ERROR_EN", 20, 1 },
|
|
{ "CL8_PAR_WRQUEUE_ERROR_EN", 19, 1 },
|
|
{ "CL7_PAR_WRQUEUE_ERROR_EN", 18, 1 },
|
|
{ "CL6_PAR_WRQUEUE_ERROR_EN", 17, 1 },
|
|
{ "CL5_PAR_WRQUEUE_ERROR_EN", 16, 1 },
|
|
{ "CL4_PAR_WRQUEUE_ERROR_EN", 15, 1 },
|
|
{ "CL3_PAR_WRQUEUE_ERROR_EN", 14, 1 },
|
|
{ "CL2_PAR_WRQUEUE_ERROR_EN", 13, 1 },
|
|
{ "CL1_PAR_WRQUEUE_ERROR_EN", 12, 1 },
|
|
{ "CL0_PAR_WRQUEUE_ERROR_EN", 11, 1 },
|
|
{ "CL10_PAR_RDQUEUE_ERROR_EN", 10, 1 },
|
|
{ "CL9_PAR_RDQUEUE_ERROR_EN", 9, 1 },
|
|
{ "CL8_PAR_RDQUEUE_ERROR_EN", 8, 1 },
|
|
{ "CL7_PAR_RDQUEUE_ERROR_EN", 7, 1 },
|
|
{ "CL6_PAR_RDQUEUE_ERROR_EN", 6, 1 },
|
|
{ "CL5_PAR_RDQUEUE_ERROR_EN", 5, 1 },
|
|
{ "CL4_PAR_RDQUEUE_ERROR_EN", 4, 1 },
|
|
{ "CL3_PAR_RDQUEUE_ERROR_EN", 3, 1 },
|
|
{ "CL2_PAR_RDQUEUE_ERROR_EN", 2, 1 },
|
|
{ "CL1_PAR_RDQUEUE_ERROR_EN", 1, 1 },
|
|
{ "CL0_PAR_RDQUEUE_ERROR_EN", 0, 1 },
|
|
{ "MA_PARITY_ERROR_STATUS1", 0x77f4, 0 },
|
|
{ "TP_DMARBT_PAR_ERROR", 31, 1 },
|
|
{ "LOGIC_FIFO_PAR_ERROR", 30, 1 },
|
|
{ "ARB3_PAR_WRQUEUE_ERROR", 29, 1 },
|
|
{ "ARB2_PAR_WRQUEUE_ERROR", 28, 1 },
|
|
{ "ARB1_PAR_WRQUEUE_ERROR", 27, 1 },
|
|
{ "ARB0_PAR_WRQUEUE_ERROR", 26, 1 },
|
|
{ "ARB3_PAR_RDQUEUE_ERROR", 25, 1 },
|
|
{ "ARB2_PAR_RDQUEUE_ERROR", 24, 1 },
|
|
{ "ARB1_PAR_RDQUEUE_ERROR", 23, 1 },
|
|
{ "ARB0_PAR_RDQUEUE_ERROR", 22, 1 },
|
|
{ "CL10_PAR_WRQUEUE_ERROR", 21, 1 },
|
|
{ "CL9_PAR_WRQUEUE_ERROR", 20, 1 },
|
|
{ "CL8_PAR_WRQUEUE_ERROR", 19, 1 },
|
|
{ "CL7_PAR_WRQUEUE_ERROR", 18, 1 },
|
|
{ "CL6_PAR_WRQUEUE_ERROR", 17, 1 },
|
|
{ "CL5_PAR_WRQUEUE_ERROR", 16, 1 },
|
|
{ "CL4_PAR_WRQUEUE_ERROR", 15, 1 },
|
|
{ "CL3_PAR_WRQUEUE_ERROR", 14, 1 },
|
|
{ "CL2_PAR_WRQUEUE_ERROR", 13, 1 },
|
|
{ "CL1_PAR_WRQUEUE_ERROR", 12, 1 },
|
|
{ "CL0_PAR_WRQUEUE_ERROR", 11, 1 },
|
|
{ "CL10_PAR_RDQUEUE_ERROR", 10, 1 },
|
|
{ "CL9_PAR_RDQUEUE_ERROR", 9, 1 },
|
|
{ "CL8_PAR_RDQUEUE_ERROR", 8, 1 },
|
|
{ "CL7_PAR_RDQUEUE_ERROR", 7, 1 },
|
|
{ "CL6_PAR_RDQUEUE_ERROR", 6, 1 },
|
|
{ "CL5_PAR_RDQUEUE_ERROR", 5, 1 },
|
|
{ "CL4_PAR_RDQUEUE_ERROR", 4, 1 },
|
|
{ "CL3_PAR_RDQUEUE_ERROR", 3, 1 },
|
|
{ "CL2_PAR_RDQUEUE_ERROR", 2, 1 },
|
|
{ "CL1_PAR_RDQUEUE_ERROR", 1, 1 },
|
|
{ "CL0_PAR_RDQUEUE_ERROR", 0, 1 },
|
|
{ "MA_SGE_PCIE_COHERANCY_CTRL", 0x77f8, 0 },
|
|
{ "BONUS_REG", 6, 26 },
|
|
{ "COHERANCY_CMD_TYPE", 4, 2 },
|
|
{ "COHERANCY_THREAD_NUM", 1, 3 },
|
|
{ "COHERANCY_ENABLE", 0, 1 },
|
|
{ "MA_ERROR_ENABLE", 0x77fc, 0 },
|
|
{ "FUTURE_EXPANSION_EE", 1, 31 },
|
|
{ "UE_ENABLE", 0, 1 },
|
|
{ "MA_PARITY_ERROR_ENABLE2", 0x7800, 0 },
|
|
{ "ARB4_PAR_WRQUEUE_ERROR_EN", 1, 1 },
|
|
{ "ARB4_PAR_RDQUEUE_ERROR_EN", 0, 1 },
|
|
{ "MA_PARITY_ERROR_STATUS2", 0x7804, 0 },
|
|
{ "ARB4_PAR_WRQUEUE_ERROR", 1, 1 },
|
|
{ "ARB4_PAR_RDQUEUE_ERROR", 0, 1 },
|
|
{ "MA_EXT_MEMORY1_BAR", 0x7808, 0 },
|
|
{ "EXT_MEM1_BASE", 16, 12 },
|
|
{ "EXT_MEM1_SIZE", 0, 12 },
|
|
{ "MA_PMTX_THROTTLE", 0x780c, 0 },
|
|
{ "FL_ENABLE", 31, 1 },
|
|
{ "FL_LIMIT", 0, 8 },
|
|
{ "MA_PMRX_THROTTLE", 0x7810, 0 },
|
|
{ "FL_ENABLE", 31, 1 },
|
|
{ "FL_LIMIT", 0, 8 },
|
|
{ "MA_SGE_TH0_WRDATA_CNT", 0x7814, 0 },
|
|
{ "MA_SGE_TH1_WRDATA_CNT", 0x7818, 0 },
|
|
{ "MA_ULPTX_WRDATA_CNT", 0x781c, 0 },
|
|
{ "MA_ULPRX_WRDATA_CNT", 0x7820, 0 },
|
|
{ "MA_ULPTXRX_WRDATA_CNT", 0x7824, 0 },
|
|
{ "MA_TP_TH0_WRDATA_CNT", 0x7828, 0 },
|
|
{ "MA_TP_TH1_WRDATA_CNT", 0x782c, 0 },
|
|
{ "MA_LE_WRDATA_CNT", 0x7830, 0 },
|
|
{ "MA_CIM_WRDATA_CNT", 0x7834, 0 },
|
|
{ "MA_PCIE_WRDATA_CNT", 0x7838, 0 },
|
|
{ "MA_PMTX_WRDATA_CNT", 0x783c, 0 },
|
|
{ "MA_PMRX_WRDATA_CNT", 0x7840, 0 },
|
|
{ "MA_HMA_WRDATA_CNT", 0x7844, 0 },
|
|
{ "MA_SGE_TH0_RDDATA_CNT", 0x7848, 0 },
|
|
{ "MA_SGE_TH1_RDDATA_CNT", 0x784c, 0 },
|
|
{ "MA_ULPTX_RDDATA_CNT", 0x7850, 0 },
|
|
{ "MA_ULPRX_RDDATA_CNT", 0x7854, 0 },
|
|
{ "MA_ULPTXRX_RDDATA_CNT", 0x7858, 0 },
|
|
{ "MA_TP_TH0_RDDATA_CNT", 0x785c, 0 },
|
|
{ "MA_TP_TH1_RDDATA_CNT", 0x7860, 0 },
|
|
{ "MA_LE_RDDATA_CNT", 0x7864, 0 },
|
|
{ "MA_CIM_RDDATA_CNT", 0x7868, 0 },
|
|
{ "MA_PCIE_RDDATA_CNT", 0x786c, 0 },
|
|
{ "MA_PMTX_RDDATA_CNT", 0x7870, 0 },
|
|
{ "MA_PMRX_RDDATA_CNT", 0x7874, 0 },
|
|
{ "MA_HMA_RDDATA_CNT", 0x7878, 0 },
|
|
{ "MA_EXIT_ADDR_FAULT", 0x787c, 0 },
|
|
{ "MA_DDR_DEVICE_CFG", 0x7880, 0 },
|
|
{ "MEM_WIDTH", 1, 3 },
|
|
{ "DDR_MODE", 0, 1 },
|
|
{ "MA_TIMEOUT_CFG", 0x78cc, 0 },
|
|
{ "CLR", 31, 1 },
|
|
{ "CNT_LOCK", 30, 1 },
|
|
{ "WRN", 24, 1 },
|
|
{ "DIR", 23, 1 },
|
|
{ "TYPE", 22, 1 },
|
|
{ "CLIENT", 16, 4 },
|
|
{ "DELAY", 0, 16 },
|
|
{ "MA_TIMEOUT_CNT", 0x78d0, 0 },
|
|
{ "DIR", 23, 1 },
|
|
{ "TYPE", 22, 1 },
|
|
{ "CLIENT", 16, 4 },
|
|
{ "CNT_VAL", 0, 16 },
|
|
{ "MA_WRITE_TIMEOUT_ERROR_ENABLE", 0x78d4, 0 },
|
|
{ "FUTURE_CEXPANSION_WTE", 29, 3 },
|
|
{ "CL12_WR_CMD_TO_EN", 28, 1 },
|
|
{ "CL11_WR_CMD_TO_EN", 27, 1 },
|
|
{ "CL10_WR_CMD_TO_EN", 26, 1 },
|
|
{ "CL9_WR_CMD_TO_EN", 25, 1 },
|
|
{ "CL8_WR_CMD_TO_EN", 24, 1 },
|
|
{ "CL7_WR_CMD_TO_EN", 23, 1 },
|
|
{ "CL6_WR_CMD_TO_EN", 22, 1 },
|
|
{ "CL5_WR_CMD_TO_EN", 21, 1 },
|
|
{ "CL4_WR_CMD_TO_EN", 20, 1 },
|
|
{ "CL3_WR_CMD_TO_EN", 19, 1 },
|
|
{ "CL2_WR_CMD_TO_EN", 18, 1 },
|
|
{ "CL1_WR_CMD_TO_EN", 17, 1 },
|
|
{ "CL0_WR_CMD_TO_EN", 16, 1 },
|
|
{ "FUTURE_DEXPANSION_WTE", 13, 3 },
|
|
{ "CL12_WR_DATA_TO_EN", 12, 1 },
|
|
{ "CL11_WR_DATA_TO_EN", 11, 1 },
|
|
{ "CL10_WR_DATA_TO_EN", 10, 1 },
|
|
{ "CL9_WR_DATA_TO_EN", 9, 1 },
|
|
{ "CL8_WR_DATA_TO_EN", 8, 1 },
|
|
{ "CL7_WR_DATA_TO_EN", 7, 1 },
|
|
{ "CL6_WR_DATA_TO_EN", 6, 1 },
|
|
{ "CL5_WR_DATA_TO_EN", 5, 1 },
|
|
{ "CL4_WR_DATA_TO_EN", 4, 1 },
|
|
{ "CL3_WR_DATA_TO_EN", 3, 1 },
|
|
{ "CL2_WR_DATA_TO_EN", 2, 1 },
|
|
{ "CL1_WR_DATA_TO_EN", 1, 1 },
|
|
{ "CL0_WR_DATA_TO_EN", 0, 1 },
|
|
{ "MA_WRITE_TIMEOUT_ERROR_STATUS", 0x78d8, 0 },
|
|
{ "FUTURE_CEXPANSION_WTS", 29, 3 },
|
|
{ "CL12_WR_CMD_TO_ERROR", 28, 1 },
|
|
{ "CL11_WR_CMD_TO_ERROR", 27, 1 },
|
|
{ "CL10_WR_CMD_TO_ERROR", 26, 1 },
|
|
{ "CL9_WR_CMD_TO_ERROR", 25, 1 },
|
|
{ "CL8_WR_CMD_TO_ERROR", 24, 1 },
|
|
{ "CL7_WR_CMD_TO_ERROR", 23, 1 },
|
|
{ "CL6_WR_CMD_TO_ERROR", 22, 1 },
|
|
{ "CL5_WR_CMD_TO_ERROR", 21, 1 },
|
|
{ "CL4_WR_CMD_TO_ERROR", 20, 1 },
|
|
{ "CL3_WR_CMD_TO_ERROR", 19, 1 },
|
|
{ "CL2_WR_CMD_TO_ERROR", 18, 1 },
|
|
{ "CL1_WR_CMD_TO_ERROR", 17, 1 },
|
|
{ "CL0_WR_CMD_TO_ERROR", 16, 1 },
|
|
{ "FUTURE_DEXPANSION_WTS", 13, 3 },
|
|
{ "CL12_WR_DATA_TO_ERROR", 12, 1 },
|
|
{ "CL11_WR_DATA_TO_ERROR", 11, 1 },
|
|
{ "CL10_WR_DATA_TO_ERROR", 10, 1 },
|
|
{ "CL9_WR_DATA_TO_ERROR", 9, 1 },
|
|
{ "CL8_WR_DATA_TO_ERROR", 8, 1 },
|
|
{ "CL7_WR_DATA_TO_ERROR", 7, 1 },
|
|
{ "CL6_WR_DATA_TO_ERROR", 6, 1 },
|
|
{ "CL5_WR_DATA_TO_ERROR", 5, 1 },
|
|
{ "CL4_WR_DATA_TO_ERROR", 4, 1 },
|
|
{ "CL3_WR_DATA_TO_ERROR", 3, 1 },
|
|
{ "CL2_WR_DATA_TO_ERROR", 2, 1 },
|
|
{ "CL1_WR_DATA_TO_ERROR", 1, 1 },
|
|
{ "CL0_WR_DATA_TO_ERROR", 0, 1 },
|
|
{ "MA_READ_TIMEOUT_ERROR_ENABLE", 0x78dc, 0 },
|
|
{ "FUTURE_CEXPANSION_RTE", 29, 3 },
|
|
{ "CL12_RD_CMD_TO_EN", 28, 1 },
|
|
{ "CL11_RD_CMD_TO_EN", 27, 1 },
|
|
{ "CL10_RD_CMD_TO_EN", 26, 1 },
|
|
{ "CL9_RD_CMD_TO_EN", 25, 1 },
|
|
{ "CL8_RD_CMD_TO_EN", 24, 1 },
|
|
{ "CL7_RD_CMD_TO_EN", 23, 1 },
|
|
{ "CL6_RD_CMD_TO_EN", 22, 1 },
|
|
{ "CL5_RD_CMD_TO_EN", 21, 1 },
|
|
{ "CL4_RD_CMD_TO_EN", 20, 1 },
|
|
{ "CL3_RD_CMD_TO_EN", 19, 1 },
|
|
{ "CL2_RD_CMD_TO_EN", 18, 1 },
|
|
{ "CL1_RD_CMD_TO_EN", 17, 1 },
|
|
{ "CL0_RD_CMD_TO_EN", 16, 1 },
|
|
{ "FUTURE_DEXPANSION_RTE", 13, 3 },
|
|
{ "CL12_RD_DATA_TO_EN", 12, 1 },
|
|
{ "CL11_RD_DATA_TO_EN", 11, 1 },
|
|
{ "CL10_RD_DATA_TO_EN", 10, 1 },
|
|
{ "CL9_RD_DATA_TO_EN", 9, 1 },
|
|
{ "CL8_RD_DATA_TO_EN", 8, 1 },
|
|
{ "CL7_RD_DATA_TO_EN", 7, 1 },
|
|
{ "CL6_RD_DATA_TO_EN", 6, 1 },
|
|
{ "CL5_RD_DATA_TO_EN", 5, 1 },
|
|
{ "CL4_RD_DATA_TO_EN", 4, 1 },
|
|
{ "CL3_RD_DATA_TO_EN", 3, 1 },
|
|
{ "CL2_RD_DATA_TO_EN", 2, 1 },
|
|
{ "CL1_RD_DATA_TO_EN", 1, 1 },
|
|
{ "CL0_RD_DATA_TO_EN", 0, 1 },
|
|
{ "MA_READ_TIMEOUT_ERROR_STATUS", 0x78e0, 0 },
|
|
{ "FUTURE_CEXPANSION_RTS", 29, 3 },
|
|
{ "CL12_RD_CMD_TO_ERROR", 28, 1 },
|
|
{ "CL11_RD_CMD_TO_ERROR", 27, 1 },
|
|
{ "CL10_RD_CMD_TO_ERROR", 26, 1 },
|
|
{ "CL9_RD_CMD_TO_ERROR", 25, 1 },
|
|
{ "CL8_RD_CMD_TO_ERROR", 24, 1 },
|
|
{ "CL7_RD_CMD_TO_ERROR", 23, 1 },
|
|
{ "CL6_RD_CMD_TO_ERROR", 22, 1 },
|
|
{ "CL5_RD_CMD_TO_ERROR", 21, 1 },
|
|
{ "CL4_RD_CMD_TO_ERROR", 20, 1 },
|
|
{ "CL3_RD_CMD_TO_ERROR", 19, 1 },
|
|
{ "CL2_RD_CMD_TO_ERROR", 18, 1 },
|
|
{ "CL1_RD_CMD_TO_ERROR", 17, 1 },
|
|
{ "CL0_RD_CMD_TO_ERROR", 16, 1 },
|
|
{ "FUTURE_DEXPANSION_RTS", 13, 3 },
|
|
{ "CL12_RD_DATA_TO_ERROR", 12, 1 },
|
|
{ "CL11_RD_DATA_TO_ERROR", 11, 1 },
|
|
{ "CL10_RD_DATA_TO_ERROR", 10, 1 },
|
|
{ "CL9_RD_DATA_TO_ERROR", 9, 1 },
|
|
{ "CL8_RD_DATA_TO_ERROR", 8, 1 },
|
|
{ "CL7_RD_DATA_TO_ERROR", 7, 1 },
|
|
{ "CL6_RD_DATA_TO_ERROR", 6, 1 },
|
|
{ "CL5_RD_DATA_TO_ERROR", 5, 1 },
|
|
{ "CL4_RD_DATA_TO_ERROR", 4, 1 },
|
|
{ "CL3_RD_DATA_TO_ERROR", 3, 1 },
|
|
{ "CL2_RD_DATA_TO_ERROR", 2, 1 },
|
|
{ "CL1_RD_DATA_TO_ERROR", 1, 1 },
|
|
{ "CL0_RD_DATA_TO_ERROR", 0, 1 },
|
|
{ "MA_BKP_CNT_SEL", 0x78e4, 0 },
|
|
{ "TYPE", 30, 2 },
|
|
{ "CLIENT", 24, 4 },
|
|
{ "MA_BKP_CNT", 0x78e8, 0 },
|
|
{ "MA_WRT_ARB", 0x78ec, 0 },
|
|
{ "WRT_EN", 31, 1 },
|
|
{ "WR_TIM", 16, 8 },
|
|
{ "RD_WIN", 8, 8 },
|
|
{ "WR_WIN", 0, 8 },
|
|
{ "MA_IF_PARITY_ERROR_ENABLE", 0x78f0, 0 },
|
|
{ "FUTURE_DEXPANSION_IPE", 13, 19 },
|
|
{ "CL12_IF_PAR_EN", 12, 1 },
|
|
{ "CL11_IF_PAR_EN", 11, 1 },
|
|
{ "CL10_IF_PAR_EN", 10, 1 },
|
|
{ "CL9_IF_PAR_EN", 9, 1 },
|
|
{ "CL8_IF_PAR_EN", 8, 1 },
|
|
{ "CL7_IF_PAR_EN", 7, 1 },
|
|
{ "CL6_IF_PAR_EN", 6, 1 },
|
|
{ "CL5_IF_PAR_EN", 5, 1 },
|
|
{ "CL4_IF_PAR_EN", 4, 1 },
|
|
{ "CL3_IF_PAR_EN", 3, 1 },
|
|
{ "CL2_IF_PAR_EN", 2, 1 },
|
|
{ "CL1_IF_PAR_EN", 1, 1 },
|
|
{ "CL0_IF_PAR_EN", 0, 1 },
|
|
{ "MA_IF_PARITY_ERROR_STATUS", 0x78f4, 0 },
|
|
{ "FUTURE_DEXPANSION_IPS", 13, 19 },
|
|
{ "CL12_IF_PAR_ERROR", 12, 1 },
|
|
{ "CL11_IF_PAR_ERROR", 11, 1 },
|
|
{ "CL10_IF_PAR_ERROR", 10, 1 },
|
|
{ "CL9_IF_PAR_ERROR", 9, 1 },
|
|
{ "CL8_IF_PAR_ERROR", 8, 1 },
|
|
{ "CL7_IF_PAR_ERROR", 7, 1 },
|
|
{ "CL6_IF_PAR_ERROR", 6, 1 },
|
|
{ "CL5_IF_PAR_ERROR", 5, 1 },
|
|
{ "CL4_IF_PAR_ERROR", 4, 1 },
|
|
{ "CL3_IF_PAR_ERROR", 3, 1 },
|
|
{ "CL2_IF_PAR_ERROR", 2, 1 },
|
|
{ "CL1_IF_PAR_ERROR", 1, 1 },
|
|
{ "CL0_IF_PAR_ERROR", 0, 1 },
|
|
{ "MA_LOCAL_DEBUG_CFG", 0x78f8, 0 },
|
|
{ "DEBUG_OR", 15, 1 },
|
|
{ "DEBUG_HI", 14, 1 },
|
|
{ "DEBUG_RPT", 13, 1 },
|
|
{ "DEBUGPAGE", 10, 3 },
|
|
{ "DEBUGSELH", 5, 5 },
|
|
{ "DEBUGSELL", 0, 5 },
|
|
{ "MA_LOCAL_DEBUG_RPT", 0x78fc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_cim_regs[] = {
|
|
{ "CIM_BOOT_CFG", 0x7b00, 0 },
|
|
{ "BootAddr", 8, 24 },
|
|
{ "uPGen", 2, 6 },
|
|
{ "BootSdram", 1, 1 },
|
|
{ "uPCRst", 0, 1 },
|
|
{ "CIM_BOOT_LEN", 0x7bf0, 0 },
|
|
{ "BootLen", 4, 28 },
|
|
{ "CIM_FLASH_BASE_ADDR", 0x7b04, 0 },
|
|
{ "FlashBaseAddr", 6, 18 },
|
|
{ "CIM_FLASH_ADDR_SIZE", 0x7b08, 0 },
|
|
{ "FlashAddrSize", 4, 20 },
|
|
{ "CIM_EEPROM_BASE_ADDR", 0x7b0c, 0 },
|
|
{ "EEPROMBaseAddr", 6, 18 },
|
|
{ "CIM_EEPROM_ADDR_SIZE", 0x7b10, 0 },
|
|
{ "EEPROMAddrSize", 4, 20 },
|
|
{ "CIM_SDRAM_BASE_ADDR", 0x7b14, 0 },
|
|
{ "SdramBaseAddr", 6, 26 },
|
|
{ "CIM_SDRAM_ADDR_SIZE", 0x7b18, 0 },
|
|
{ "SdramAddrSize", 4, 28 },
|
|
{ "CIM_EXTMEM2_BASE_ADDR", 0x7b1c, 0 },
|
|
{ "ExtMem2BaseAddr", 6, 26 },
|
|
{ "CIM_EXTMEM2_ADDR_SIZE", 0x7b20, 0 },
|
|
{ "ExtMem2AddrSize", 4, 28 },
|
|
{ "CIM_UP_SPARE_INT", 0x7b24, 0 },
|
|
{ "TDebugInt", 4, 1 },
|
|
{ "BootVecSel", 3, 1 },
|
|
{ "uPSpareInt", 0, 3 },
|
|
{ "CIM_HOST_INT_ENABLE", 0x7b28, 0 },
|
|
{ "PCIE2CIMIntfParErr", 29, 1 },
|
|
{ "ma_cim_IntfPerr", 28, 1 },
|
|
{ "PLCIM_MstRspDataParErr", 27, 1 },
|
|
{ "NCSI2CIMIntfParErr", 26, 1 },
|
|
{ "SGE2CIMIntfParErr", 25, 1 },
|
|
{ "ULP2CIMIntfParErr", 24, 1 },
|
|
{ "TP2CIMIntfParErr", 23, 1 },
|
|
{ "OBQSGERx1ParErr", 22, 1 },
|
|
{ "OBQSGERx0ParErr", 21, 1 },
|
|
{ "TieQOutParErrIntEn", 20, 1 },
|
|
{ "TieQInParErrIntEn", 19, 1 },
|
|
{ "MBHostParErr", 18, 1 },
|
|
{ "MBuPParErr", 17, 1 },
|
|
{ "IBQTP0ParErr", 16, 1 },
|
|
{ "IBQTP1ParErr", 15, 1 },
|
|
{ "IBQULPParErr", 14, 1 },
|
|
{ "IBQSGELOParErr", 13, 1 },
|
|
{ "IBQPCIEParErr", 12, 1 },
|
|
{ "IBQNCSIParErr", 11, 1 },
|
|
{ "OBQULP0ParErr", 10, 1 },
|
|
{ "OBQULP1ParErr", 9, 1 },
|
|
{ "OBQULP2ParErr", 8, 1 },
|
|
{ "OBQULP3ParErr", 7, 1 },
|
|
{ "OBQSGEParErr", 6, 1 },
|
|
{ "OBQNCSIParErr", 5, 1 },
|
|
{ "Timer1IntEn", 3, 1 },
|
|
{ "Timer0IntEn", 2, 1 },
|
|
{ "PrefDropIntEn", 1, 1 },
|
|
{ "CIM_HOST_INT_CAUSE", 0x7b2c, 0 },
|
|
{ "PCIE2CIMIntfParErr", 29, 1 },
|
|
{ "ma_cim_IntfPerr", 28, 1 },
|
|
{ "PLCIM_MstRspDataParErr", 27, 1 },
|
|
{ "NCSI2CIMIntfParErr", 26, 1 },
|
|
{ "SGE2CIMIntfParErr", 25, 1 },
|
|
{ "ULP2CIMIntfParErr", 24, 1 },
|
|
{ "TP2CIMIntfParErr", 23, 1 },
|
|
{ "OBQSGERx1ParErr", 22, 1 },
|
|
{ "OBQSGERx0ParErr", 21, 1 },
|
|
{ "TieQOutParErrInt", 20, 1 },
|
|
{ "TieQInParErrInt", 19, 1 },
|
|
{ "MBHostParErr", 18, 1 },
|
|
{ "IBQTP0ParErr", 16, 1 },
|
|
{ "IBQTP1ParErr", 15, 1 },
|
|
{ "IBQULPParErr", 14, 1 },
|
|
{ "IBQSGELOParErr", 13, 1 },
|
|
{ "IBQPCIEParErr", 12, 1 },
|
|
{ "IBQNCSIParErr", 11, 1 },
|
|
{ "OBQULP0ParErr", 10, 1 },
|
|
{ "OBQULP1ParErr", 9, 1 },
|
|
{ "OBQULP2ParErr", 8, 1 },
|
|
{ "OBQULP3ParErr", 7, 1 },
|
|
{ "OBQSGEParErr", 6, 1 },
|
|
{ "OBQNCSIParErr", 5, 1 },
|
|
{ "Timer1Int", 3, 1 },
|
|
{ "Timer0Int", 2, 1 },
|
|
{ "PrefDropInt", 1, 1 },
|
|
{ "uPAccNonZero", 0, 1 },
|
|
{ "CIM_HOST_UPACC_INT_ENABLE", 0x7b30, 0 },
|
|
{ "EEPROMWRIntEn", 30, 1 },
|
|
{ "TimeOutMAIntEn", 29, 1 },
|
|
{ "TimeOutIntEn", 28, 1 },
|
|
{ "RspOvrLookupIntEn", 27, 1 },
|
|
{ "ReqOvrLookupIntEn", 26, 1 },
|
|
{ "BlkWrPlIntEn", 25, 1 },
|
|
{ "BlkRdPlIntEn", 24, 1 },
|
|
{ "SglWrPlIntEn", 23, 1 },
|
|
{ "SglRdPlIntEn", 22, 1 },
|
|
{ "BlkWrCtlIntEn", 21, 1 },
|
|
{ "BlkRdCtlIntEn", 20, 1 },
|
|
{ "SglWrCtlIntEn", 19, 1 },
|
|
{ "SglRdCtlIntEn", 18, 1 },
|
|
{ "BlkWrEEPROMIntEn", 17, 1 },
|
|
{ "BlkRdEEPROMIntEn", 16, 1 },
|
|
{ "SglWrEEPROMIntEn", 15, 1 },
|
|
{ "SglRdEEPROMIntEn", 14, 1 },
|
|
{ "BlkWrFlashIntEn", 13, 1 },
|
|
{ "BlkRdFlashIntEn", 12, 1 },
|
|
{ "SglWrFlashIntEn", 11, 1 },
|
|
{ "SglRdFlashIntEn", 10, 1 },
|
|
{ "BlkWrBootIntEn", 9, 1 },
|
|
{ "BlkRdBootIntEn", 8, 1 },
|
|
{ "SglWrBootIntEn", 7, 1 },
|
|
{ "SglRdBootIntEn", 6, 1 },
|
|
{ "IllWrBEIntEn", 5, 1 },
|
|
{ "IllRdBEIntEn", 4, 1 },
|
|
{ "IllRdIntEn", 3, 1 },
|
|
{ "IllWrIntEn", 2, 1 },
|
|
{ "IllTransIntEn", 1, 1 },
|
|
{ "RsvdSpaceIntEn", 0, 1 },
|
|
{ "CIM_HOST_UPACC_INT_CAUSE", 0x7b34, 0 },
|
|
{ "EEPROMWRInt", 30, 1 },
|
|
{ "TimeOutMAInt", 29, 1 },
|
|
{ "TimeOutInt", 28, 1 },
|
|
{ "RspOvrLookupInt", 27, 1 },
|
|
{ "ReqOvrLookupInt", 26, 1 },
|
|
{ "BlkWrPlInt", 25, 1 },
|
|
{ "BlkRdPlInt", 24, 1 },
|
|
{ "SglWrPlInt", 23, 1 },
|
|
{ "SglRdPlInt", 22, 1 },
|
|
{ "BlkWrCtlInt", 21, 1 },
|
|
{ "BlkRdCtlInt", 20, 1 },
|
|
{ "SglWrCtlInt", 19, 1 },
|
|
{ "SglRdCtlInt", 18, 1 },
|
|
{ "BlkWrEEPROMInt", 17, 1 },
|
|
{ "BlkRdEEPROMInt", 16, 1 },
|
|
{ "SglWrEEPROMInt", 15, 1 },
|
|
{ "SglRdEEPROMInt", 14, 1 },
|
|
{ "BlkWrFlashInt", 13, 1 },
|
|
{ "BlkRdFlashInt", 12, 1 },
|
|
{ "SglWrFlashInt", 11, 1 },
|
|
{ "SglRdFlashInt", 10, 1 },
|
|
{ "BlkWrBootInt", 9, 1 },
|
|
{ "BlkRdBootInt", 8, 1 },
|
|
{ "SglWrBootInt", 7, 1 },
|
|
{ "SglRdBootInt", 6, 1 },
|
|
{ "IllWrBEInt", 5, 1 },
|
|
{ "IllRdBEInt", 4, 1 },
|
|
{ "IllRdInt", 3, 1 },
|
|
{ "IllWrInt", 2, 1 },
|
|
{ "IllTransInt", 1, 1 },
|
|
{ "RsvdSpaceInt", 0, 1 },
|
|
{ "CIM_UP_INT_ENABLE", 0x7b38, 0 },
|
|
{ "PCIE2CIMIntfParErr", 29, 1 },
|
|
{ "ma_cim_IntfPerr", 28, 1 },
|
|
{ "PLCIM_MstRspDataParErr", 27, 1 },
|
|
{ "NCSI2CIMIntfParErr", 26, 1 },
|
|
{ "SGE2CIMIntfParErr", 25, 1 },
|
|
{ "ULP2CIMIntfParErr", 24, 1 },
|
|
{ "TP2CIMIntfParErr", 23, 1 },
|
|
{ "OBQSGERx1ParErr", 22, 1 },
|
|
{ "OBQSGERx0ParErr", 21, 1 },
|
|
{ "TieQOutParErrIntEn", 20, 1 },
|
|
{ "TieQInParErrIntEn", 19, 1 },
|
|
{ "MBHostParErr", 18, 1 },
|
|
{ "MBuPParErr", 17, 1 },
|
|
{ "IBQTP0ParErr", 16, 1 },
|
|
{ "IBQTP1ParErr", 15, 1 },
|
|
{ "IBQULPParErr", 14, 1 },
|
|
{ "IBQSGELOParErr", 13, 1 },
|
|
{ "IBQPCIEParErr", 12, 1 },
|
|
{ "IBQNCSIParErr", 11, 1 },
|
|
{ "OBQULP0ParErr", 10, 1 },
|
|
{ "OBQULP1ParErr", 9, 1 },
|
|
{ "OBQULP2ParErr", 8, 1 },
|
|
{ "OBQULP3ParErr", 7, 1 },
|
|
{ "OBQSGEParErr", 6, 1 },
|
|
{ "OBQNCSIParErr", 5, 1 },
|
|
{ "MstPlIntEn", 4, 1 },
|
|
{ "Timer1IntEn", 3, 1 },
|
|
{ "Timer0IntEn", 2, 1 },
|
|
{ "PrefDropIntEn", 1, 1 },
|
|
{ "CIM_UP_INT_CAUSE", 0x7b3c, 0 },
|
|
{ "PCIE2CIMIntfParErr", 29, 1 },
|
|
{ "ma_cim_IntfPerr", 28, 1 },
|
|
{ "PLCIM_MstRspDataParErr", 27, 1 },
|
|
{ "NCSI2CIMIntfParErr", 26, 1 },
|
|
{ "SGE2CIMIntfParErr", 25, 1 },
|
|
{ "ULP2CIMIntfParErr", 24, 1 },
|
|
{ "TP2CIMIntfParErr", 23, 1 },
|
|
{ "OBQSGERx1ParErr", 22, 1 },
|
|
{ "OBQSGERx0ParErr", 21, 1 },
|
|
{ "TieQOutParErrInt", 20, 1 },
|
|
{ "TieQInParErrInt", 19, 1 },
|
|
{ "MBHostParErr", 18, 1 },
|
|
{ "IBQTP0ParErr", 16, 1 },
|
|
{ "IBQTP1ParErr", 15, 1 },
|
|
{ "IBQULPParErr", 14, 1 },
|
|
{ "IBQSGELOParErr", 13, 1 },
|
|
{ "IBQPCIEParErr", 12, 1 },
|
|
{ "IBQNCSIParErr", 11, 1 },
|
|
{ "OBQULP0ParErr", 10, 1 },
|
|
{ "OBQULP1ParErr", 9, 1 },
|
|
{ "OBQULP2ParErr", 8, 1 },
|
|
{ "OBQULP3ParErr", 7, 1 },
|
|
{ "OBQSGEParErr", 6, 1 },
|
|
{ "OBQNCSIParErr", 5, 1 },
|
|
{ "MstPlInt", 4, 1 },
|
|
{ "Timer1Int", 3, 1 },
|
|
{ "Timer0Int", 2, 1 },
|
|
{ "PrefDropInt", 1, 1 },
|
|
{ "uPAccNonZero", 0, 1 },
|
|
{ "CIM_UP_ACC_INT_ENABLE", 0x7b40, 0 },
|
|
{ "EEPROMWRIntEn", 30, 1 },
|
|
{ "TimeOutMAIntEn", 29, 1 },
|
|
{ "TimeOutIntEn", 28, 1 },
|
|
{ "RspOvrLookupIntEn", 27, 1 },
|
|
{ "ReqOvrLookupIntEn", 26, 1 },
|
|
{ "BlkWrPlIntEn", 25, 1 },
|
|
{ "BlkRdPlIntEn", 24, 1 },
|
|
{ "SglWrPlIntEn", 23, 1 },
|
|
{ "SglRdPlIntEn", 22, 1 },
|
|
{ "BlkWrCtlIntEn", 21, 1 },
|
|
{ "BlkRdCtlIntEn", 20, 1 },
|
|
{ "SglWrCtlIntEn", 19, 1 },
|
|
{ "SglRdCtlIntEn", 18, 1 },
|
|
{ "BlkWrEEPROMIntEn", 17, 1 },
|
|
{ "BlkRdEEPROMIntEn", 16, 1 },
|
|
{ "SglWrEEPROMIntEn", 15, 1 },
|
|
{ "SglRdEEPROMIntEn", 14, 1 },
|
|
{ "BlkWrFlashIntEn", 13, 1 },
|
|
{ "BlkRdFlashIntEn", 12, 1 },
|
|
{ "SglWrFlashIntEn", 11, 1 },
|
|
{ "SglRdFlashIntEn", 10, 1 },
|
|
{ "BlkWrBootIntEn", 9, 1 },
|
|
{ "BlkRdBootIntEn", 8, 1 },
|
|
{ "SglWrBootIntEn", 7, 1 },
|
|
{ "SglRdBootIntEn", 6, 1 },
|
|
{ "IllWrBEIntEn", 5, 1 },
|
|
{ "IllRdBEIntEn", 4, 1 },
|
|
{ "IllRdIntEn", 3, 1 },
|
|
{ "IllWrIntEn", 2, 1 },
|
|
{ "IllTransIntEn", 1, 1 },
|
|
{ "RsvdSpaceIntEn", 0, 1 },
|
|
{ "CIM_UP_ACC_INT_CAUSE", 0x7b44, 0 },
|
|
{ "EEPROMWRInt", 30, 1 },
|
|
{ "TimeOutMAInt", 29, 1 },
|
|
{ "TimeOutInt", 28, 1 },
|
|
{ "RspOvrLookupInt", 27, 1 },
|
|
{ "ReqOvrLookupInt", 26, 1 },
|
|
{ "BlkWrPlInt", 25, 1 },
|
|
{ "BlkRdPlInt", 24, 1 },
|
|
{ "SglWrPlInt", 23, 1 },
|
|
{ "SglRdPlInt", 22, 1 },
|
|
{ "BlkWrCtlInt", 21, 1 },
|
|
{ "BlkRdCtlInt", 20, 1 },
|
|
{ "SglWrCtlInt", 19, 1 },
|
|
{ "SglRdCtlInt", 18, 1 },
|
|
{ "BlkWrEEPROMInt", 17, 1 },
|
|
{ "BlkRdEEPROMInt", 16, 1 },
|
|
{ "SglWrEEPROMInt", 15, 1 },
|
|
{ "SglRdEEPROMInt", 14, 1 },
|
|
{ "BlkWrFlashInt", 13, 1 },
|
|
{ "BlkRdFlashInt", 12, 1 },
|
|
{ "SglWrFlashInt", 11, 1 },
|
|
{ "SglRdFlashInt", 10, 1 },
|
|
{ "BlkWrBootInt", 9, 1 },
|
|
{ "BlkRdBootInt", 8, 1 },
|
|
{ "SglWrBootInt", 7, 1 },
|
|
{ "SglRdBootInt", 6, 1 },
|
|
{ "IllWrBEInt", 5, 1 },
|
|
{ "IllRdBEInt", 4, 1 },
|
|
{ "IllRdInt", 3, 1 },
|
|
{ "IllWrInt", 2, 1 },
|
|
{ "IllTransInt", 1, 1 },
|
|
{ "RsvdSpaceInt", 0, 1 },
|
|
{ "CIM_QUEUE_CONFIG_REF", 0x7b48, 0 },
|
|
{ "OBQSelect", 4, 1 },
|
|
{ "IBQSelect", 3, 1 },
|
|
{ "QueNumSelect", 0, 3 },
|
|
{ "CIM_QUEUE_CONFIG_CTRL", 0x7b4c, 0 },
|
|
{ "Que1KEn", 30, 1 },
|
|
{ "QueSize", 24, 6 },
|
|
{ "QueBase", 16, 6 },
|
|
{ "QueDbg8BEn", 9, 1 },
|
|
{ "QueFullThrsh", 0, 9 },
|
|
{ "CIM_HOST_ACC_CTRL", 0x7b50, 0 },
|
|
{ "HostBusy", 17, 1 },
|
|
{ "HostWrite", 16, 1 },
|
|
{ "HostAddr", 0, 16 },
|
|
{ "CIM_HOST_ACC_DATA", 0x7b54, 0 },
|
|
{ "CIM_CDEBUGDATA", 0x7b58, 0 },
|
|
{ "CDebugDataH", 16, 16 },
|
|
{ "CDebugDataL", 0, 16 },
|
|
{ "CIM_IBQ_DBG_CFG", 0x7b60, 0 },
|
|
{ "IbqDbgAddr", 16, 12 },
|
|
{ "IbqDbgWr", 2, 1 },
|
|
{ "IbqDbgBusy", 1, 1 },
|
|
{ "IbqDbgEn", 0, 1 },
|
|
{ "CIM_OBQ_DBG_CFG", 0x7b64, 0 },
|
|
{ "ObqDbgAddr", 16, 12 },
|
|
{ "ObqDbgWr", 2, 1 },
|
|
{ "ObqDbgBusy", 1, 1 },
|
|
{ "ObqDbgEn", 0, 1 },
|
|
{ "CIM_IBQ_DBG_DATA", 0x7b68, 0 },
|
|
{ "CIM_OBQ_DBG_DATA", 0x7b6c, 0 },
|
|
{ "CIM_DEBUGCFG", 0x7b70, 0 },
|
|
{ "POLADbgRdPtr", 23, 9 },
|
|
{ "PILADbgRdPtr", 14, 9 },
|
|
{ "LAMaskTrig", 13, 1 },
|
|
{ "LADbgEn", 12, 1 },
|
|
{ "LAFillOnce", 11, 1 },
|
|
{ "LAMaskStop", 10, 1 },
|
|
{ "DebugSelH", 5, 5 },
|
|
{ "DebugSelL", 0, 5 },
|
|
{ "CIM_DEBUGSTS", 0x7b74, 0 },
|
|
{ "LAReset", 31, 1 },
|
|
{ "POLADbgWrPtr", 16, 9 },
|
|
{ "PILADbgWrPtr", 0, 9 },
|
|
{ "CIM_PO_LA_DEBUGDATA", 0x7b78, 0 },
|
|
{ "CIM_PI_LA_DEBUGDATA", 0x7b7c, 0 },
|
|
{ "CIM_PO_LA_MADEBUGDATA", 0x7b80, 0 },
|
|
{ "CIM_PI_LA_MADEBUGDATA", 0x7b84, 0 },
|
|
{ "CIM_PO_LA_PIFSMDEBUGDATA", 0x7b8c, 0 },
|
|
{ "CIM_MEM_ZONE0_VA", 0x7b90, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE0_BA", 0x7b94, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE0_LEN", 0x7b98, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE1_VA", 0x7b9c, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE1_BA", 0x7ba0, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE1_LEN", 0x7ba4, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE2_VA", 0x7ba8, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE2_BA", 0x7bac, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE2_LEN", 0x7bb0, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE3_VA", 0x7bb4, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE3_BA", 0x7bb8, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE3_LEN", 0x7bbc, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE4_VA", 0x7bc0, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE4_BA", 0x7bc4, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE4_LEN", 0x7bc8, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE5_VA", 0x7bcc, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE5_BA", 0x7bd0, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE5_LEN", 0x7bd4, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE6_VA", 0x7bd8, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE6_BA", 0x7bdc, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE6_LEN", 0x7be0, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE7_VA", 0x7be4, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE7_BA", 0x7be8, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE7_LEN", 0x7bec, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_GLB_TIMER_CTL", 0x7bf4, 0 },
|
|
{ "Timer1En", 4, 1 },
|
|
{ "Timer0En", 3, 1 },
|
|
{ "TimerEn", 1, 1 },
|
|
{ "CIM_GLB_TIMER", 0x7bf8, 0 },
|
|
{ "CIM_GLB_TIMER_TICK", 0x7bfc, 0 },
|
|
{ "CIM_TIMER0", 0x7c00, 0 },
|
|
{ "CIM_TIMER1", 0x7c04, 0 },
|
|
{ "CIM_DEBUG_ADDR_TIMEOUT", 0x7c08, 0 },
|
|
{ "DAddrTimeOut", 2, 30 },
|
|
{ "DAddrTimeOutType", 0, 2 },
|
|
{ "CIM_DEBUG_ADDR_ILLEGAL", 0x7c0c, 0 },
|
|
{ "DAddrIllegal", 2, 30 },
|
|
{ "DAddrIllegalType", 0, 2 },
|
|
{ "CIM_DEBUG_PIF_CAUSE_MASK", 0x7c10, 0 },
|
|
{ "CIM_DEBUG_PIF_UPACC_CAUSE_MASK", 0x7c14, 0 },
|
|
{ "CIM_DEBUG_UP_CAUSE_MASK", 0x7c18, 0 },
|
|
{ "CIM_DEBUG_UP_UPACC_CAUSE_MASK", 0x7c1c, 0 },
|
|
{ "CIM_PERR_INJECT", 0x7c20, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "CIM_PERR_ENABLE", 0x7c24, 0 },
|
|
{ "CIM_EEPROM_BUSY_BIT", 0x7c28, 0 },
|
|
{ "CIM_MA_TIMER_EN", 0x7c2c, 0 },
|
|
{ "slow_timer_enable", 1, 1 },
|
|
{ "ma_timer_enable", 0, 1 },
|
|
{ "CIM_UP_PO_SINGLE_OUTSTANDING", 0x7c30, 0 },
|
|
{ "CIM_CIM_DEBUG_SPARE", 0x7c34, 0 },
|
|
{ "CIM_UP_OPERATION_FREQ", 0x7c38, 0 },
|
|
{ "CIM_CIM_IBQ_ERR_CODE", 0x7c3c, 0 },
|
|
{ "CIM_ULP_TX_PKT_ERR_CODE", 16, 8 },
|
|
{ "CIM_PCIE_PKT_ERR_CODE", 8, 8 },
|
|
{ "CIM_SGE0_PKT_ERR_CODE", 0, 8 },
|
|
{ "CIM_IBQ_DBG_WAIT_COUNTER", 0x7c40, 0 },
|
|
{ "CIM_PIO_UP_MST_CFG_SEL", 0x7c44, 0 },
|
|
{ "CIM_CGEN", 0x7c48, 0 },
|
|
{ "CIM_QUEUE_FEATURE_DISABLE", 0x7c4c, 0 },
|
|
{ "pcie_obq_if_disable", 5, 1 },
|
|
{ "obq_throuttle_on_eop", 4, 1 },
|
|
{ "obq_read_ctl_perf_mode_disable", 3, 1 },
|
|
{ "obq_wait_for_eop_flush_disable", 2, 1 },
|
|
{ "ibq_rra_dsbl", 1, 1 },
|
|
{ "ibq_skid_fifo_eop_flsh_dsbl", 0, 1 },
|
|
{ "CIM_CGEN_GLOBAL", 0x7c50, 0 },
|
|
{ "CIM_DPSLP_EN", 0x7c54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e240, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e244, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e248, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e24c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e250, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e254, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e258, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e25c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e260, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e264, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e268, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e26c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e270, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e274, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e278, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e27c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1e280, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1e284, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1e288, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1e28c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e290, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e640, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e644, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e648, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e64c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e650, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e654, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e658, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e65c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e660, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e664, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e668, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e66c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e670, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e674, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e678, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e67c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1e680, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1e684, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1e688, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1e68c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e690, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea40, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea44, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea48, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea4c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea50, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea58, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea5c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea60, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea64, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea68, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea6c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea70, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea74, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea78, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea7c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1ea80, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1ea84, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1ea88, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1ea8c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ea90, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee40, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee44, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee48, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee4c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee50, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee58, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee5c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee60, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee64, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee68, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee6c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee70, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee74, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee78, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee7c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1ee80, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1ee84, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1ee88, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1ee8c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ee90, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f240, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f244, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f248, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f24c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f250, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f254, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f258, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f25c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f260, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f264, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f268, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f26c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f270, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f274, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f278, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f27c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1f280, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1f284, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1f288, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1f28c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f290, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f640, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f644, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f648, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f64c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f650, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f654, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f658, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f65c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f660, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f664, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f668, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f66c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f670, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f674, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f678, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f67c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1f680, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1f684, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1f688, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1f68c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f690, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa40, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa44, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa48, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa4c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa50, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa58, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa5c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa60, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa64, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa68, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa6c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa70, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa74, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa78, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa7c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1fa80, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1fa84, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1fa88, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1fa8c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fa90, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe40, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe44, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe48, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe4c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe50, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe58, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe5c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe60, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe64, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe68, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe6c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe70, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe74, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe78, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe7c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1fe80, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1fe84, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1fe88, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1fe8c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fe90, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_tp_regs[] = {
|
|
{ "TP_IN_CONFIG", 0x7d00, 0 },
|
|
{ "VLANExtEnPort3", 31, 1 },
|
|
{ "VLANExtEnPort2", 30, 1 },
|
|
{ "VLANExtEnPort1", 29, 1 },
|
|
{ "VLANExtEnPort0", 28, 1 },
|
|
{ "TcpOptParserDisCh3", 27, 1 },
|
|
{ "TcpOptParserDisCh2", 26, 1 },
|
|
{ "TcpOptParserDisCh1", 25, 1 },
|
|
{ "TcpOptParserDisCh0", 24, 1 },
|
|
{ "CrcPassPrt3", 23, 1 },
|
|
{ "CrcPassPrt2", 22, 1 },
|
|
{ "CrcPassPrt1", 21, 1 },
|
|
{ "CrcPassPrt0", 20, 1 },
|
|
{ "VepaMode", 19, 1 },
|
|
{ "FipUpEn", 18, 1 },
|
|
{ "FcoeUpEn", 17, 1 },
|
|
{ "FcoeEnable", 16, 1 },
|
|
{ "IPv6Enable", 15, 1 },
|
|
{ "NICMode", 14, 1 },
|
|
{ "VnTagDefaultVal", 13, 1 },
|
|
{ "ECheckUDPLen", 12, 1 },
|
|
{ "EReportUdpHdrLen", 11, 1 },
|
|
{ "FcoeFPMA", 10, 1 },
|
|
{ "VnTagEnable", 9, 1 },
|
|
{ "VnTagEthEnable", 8, 1 },
|
|
{ "CChecksumCheckIP", 7, 1 },
|
|
{ "CChecksumCheckUDP", 6, 1 },
|
|
{ "CChecksumCheckTCP", 5, 1 },
|
|
{ "CTag", 4, 1 },
|
|
{ "CXoffOverride", 3, 1 },
|
|
{ "EthUpEn", 2, 1 },
|
|
{ "EGreDropEn", 1, 1 },
|
|
{ "CFastDemuxEn", 0, 1 },
|
|
{ "TP_OUT_CONFIG", 0x7d04, 0 },
|
|
{ "PortQfcEn", 28, 4 },
|
|
{ "EPktDistChn3", 23, 1 },
|
|
{ "EPktDistChn2", 22, 1 },
|
|
{ "EPktDistChn1", 21, 1 },
|
|
{ "EPktDistChn0", 20, 1 },
|
|
{ "TtlMode", 19, 1 },
|
|
{ "EQfcDmac", 18, 1 },
|
|
{ "ELpbkIncMpsStat", 17, 1 },
|
|
{ "IPIDSplitMode", 16, 1 },
|
|
{ "CCplAckMode", 13, 1 },
|
|
{ "RMWHintEnable", 12, 1 },
|
|
{ "EChecksumInsertTCP", 11, 1 },
|
|
{ "EChecksumInsertIP", 10, 1 },
|
|
{ "EVnTagEn", 9, 1 },
|
|
{ "EV6FlwEn", 8, 1 },
|
|
{ "EPriority", 7, 1 },
|
|
{ "EVlanPrio", 6, 1 },
|
|
{ "CChecksumInsertTCP", 5, 1 },
|
|
{ "CChecksumInsertIP", 4, 1 },
|
|
{ "CRxPktEnc", 3, 1 },
|
|
{ "CCPL", 2, 1 },
|
|
{ "CRxPktXt", 1, 1 },
|
|
{ "CEthernet", 0, 1 },
|
|
{ "TP_GLOBAL_CONFIG", 0x7d08, 0 },
|
|
{ "SYNCookieParams", 26, 6 },
|
|
{ "RXFlowControlDisable", 25, 1 },
|
|
{ "TXPacingEnable", 24, 1 },
|
|
{ "ActiveFilterCounts", 22, 1 },
|
|
{ "ProtectedMode", 21, 1 },
|
|
{ "FiveTupleLookup", 17, 2 },
|
|
{ "OfdMpsStats", 16, 1 },
|
|
{ "DontFragment", 15, 1 },
|
|
{ "IPIdentSplit", 14, 1 },
|
|
{ "RssSynSteerEnable", 12, 1 },
|
|
{ "IssFromCplEnable", 11, 1 },
|
|
{ "RssLoopbackEnable", 10, 1 },
|
|
{ "TCAMServerUse", 8, 2 },
|
|
{ "IPTTL", 0, 8 },
|
|
{ "TP_DB_CONFIG", 0x7d0c, 0 },
|
|
{ "DBMaxOpCnt", 24, 8 },
|
|
{ "CxMaxOpCntDisable", 23, 1 },
|
|
{ "CxMaxOpCnt", 16, 7 },
|
|
{ "TxMaxOpCntDisable", 15, 1 },
|
|
{ "TxMaxOpCnt", 8, 7 },
|
|
{ "RxMaxOpCntDisable", 7, 1 },
|
|
{ "RxMaxOpCnt", 0, 7 },
|
|
{ "TP_CMM_TCB_BASE", 0x7d10, 0 },
|
|
{ "TP_CMM_MM_BASE", 0x7d14, 0 },
|
|
{ "TP_CMM_TIMER_BASE", 0x7d18, 0 },
|
|
{ "TP_CMM_MM_FLST_SIZE", 0x7d1c, 0 },
|
|
{ "RxPoolSize", 16, 16 },
|
|
{ "TxPoolSize", 0, 16 },
|
|
{ "TP_PMM_TX_BASE", 0x7d20, 0 },
|
|
{ "TP_PMM_DEFRAG_BASE", 0x7d24, 0 },
|
|
{ "TP_PMM_RX_BASE", 0x7d28, 0 },
|
|
{ "TP_PMM_RX_PAGE_SIZE", 0x7d2c, 0 },
|
|
{ "TP_PMM_RX_MAX_PAGE", 0x7d30, 0 },
|
|
{ "PMRxNumChn", 31, 1 },
|
|
{ "PMRxMaxPage", 0, 21 },
|
|
{ "TP_PMM_TX_PAGE_SIZE", 0x7d34, 0 },
|
|
{ "TP_PMM_TX_MAX_PAGE", 0x7d38, 0 },
|
|
{ "PMTxNumChn", 30, 2 },
|
|
{ "PMTxMaxPage", 0, 21 },
|
|
{ "TP_TCP_OPTIONS", 0x7d40, 0 },
|
|
{ "MTUDefault", 16, 16 },
|
|
{ "MTUEnable", 10, 1 },
|
|
{ "SACKTx", 9, 1 },
|
|
{ "SACKRx", 8, 1 },
|
|
{ "SACKMode", 4, 2 },
|
|
{ "WindowScaleMode", 2, 2 },
|
|
{ "TimestampsMode", 0, 2 },
|
|
{ "TP_DACK_CONFIG", 0x7d44, 0 },
|
|
{ "AutoState3", 30, 2 },
|
|
{ "AutoState2", 28, 2 },
|
|
{ "AutoState1", 26, 2 },
|
|
{ "ByteThreshold", 8, 18 },
|
|
{ "MSSThreshold", 4, 3 },
|
|
{ "AutoCareful", 2, 1 },
|
|
{ "AutoEnable", 1, 1 },
|
|
{ "Mode", 0, 1 },
|
|
{ "TP_PC_CONFIG", 0x7d48, 0 },
|
|
{ "EnableFinCheck", 31, 1 },
|
|
{ "EnableOcspiFull", 30, 1 },
|
|
{ "EnableFLMErrorDDP", 29, 1 },
|
|
{ "LockTid", 28, 1 },
|
|
{ "DisableInvPend", 27, 1 },
|
|
{ "EnableFilterCount", 26, 1 },
|
|
{ "RddpCongEn", 25, 1 },
|
|
{ "EnableOnFlyPDU", 24, 1 },
|
|
{ "EnableMinRcvWnd", 23, 1 },
|
|
{ "EnableMaxRcvWnd", 22, 1 },
|
|
{ "EnableMibVfPld", 21, 1 },
|
|
{ "TxDeferEnable", 20, 1 },
|
|
{ "RxCongestionMode", 19, 1 },
|
|
{ "HearbeatOnceDACK", 18, 1 },
|
|
{ "HearbeatOnceHeap", 17, 1 },
|
|
{ "HearbeatDACK", 16, 1 },
|
|
{ "TxCongestionMode", 15, 1 },
|
|
{ "AcceptLatestRcvAdv", 14, 1 },
|
|
{ "DisableSYNData", 13, 1 },
|
|
{ "DisableWindowPSH", 12, 1 },
|
|
{ "DisableFINOldData", 11, 1 },
|
|
{ "EnableFLMError", 10, 1 },
|
|
{ "EnableOptMtu", 9, 1 },
|
|
{ "FilterPeerFIN", 8, 1 },
|
|
{ "EnableFeedbackSend", 7, 1 },
|
|
{ "EnableRDMAError", 6, 1 },
|
|
{ "EnableFilterNat", 5, 1 },
|
|
{ "DisableSepPshFlag", 4, 1 },
|
|
{ "EnableOfdoVLAN", 3, 1 },
|
|
{ "DisableTimeWait", 2, 1 },
|
|
{ "EnableVlanCheck", 1, 1 },
|
|
{ "TxDataAckPageEnable", 0, 1 },
|
|
{ "TP_PC_CONFIG2", 0x7d4c, 0 },
|
|
{ "EnableMtuVfMode", 31, 1 },
|
|
{ "EnableMibVfMode", 30, 1 },
|
|
{ "DisableLbkCheck", 29, 1 },
|
|
{ "EnableUrgDdpOff", 28, 1 },
|
|
{ "EnableFilterLpbk", 27, 1 },
|
|
{ "DisableTblMmgr", 26, 1 },
|
|
{ "CngRecSndNxt", 25, 1 },
|
|
{ "EnableLbkChn", 24, 1 },
|
|
{ "EnableLroEcn", 23, 1 },
|
|
{ "EnablePcmdCheck", 22, 1 },
|
|
{ "EnableELbkAFull", 21, 1 },
|
|
{ "EnableCLbkAFull", 20, 1 },
|
|
{ "EnableOespiFull", 19, 1 },
|
|
{ "DisableHitCheck", 18, 1 },
|
|
{ "EnableRssErrCheck", 17, 1 },
|
|
{ "DisableNewPshFlag", 16, 1 },
|
|
{ "EnableRddpRcvAdvClr", 15, 1 },
|
|
{ "EnableFinDdpOff", 14, 1 },
|
|
{ "EnableArpMiss", 13, 1 },
|
|
{ "EnableRstPaws", 12, 1 },
|
|
{ "EnableIPv6RSS", 11, 1 },
|
|
{ "EnableNonOfdHybRss", 10, 1 },
|
|
{ "EnableUDP4TupRss", 9, 1 },
|
|
{ "EnableRxPktTmstpRss", 8, 1 },
|
|
{ "EnableEPCMDAFull", 7, 1 },
|
|
{ "EnableCPCMDAFull", 6, 1 },
|
|
{ "EnableEHdrAFull", 5, 1 },
|
|
{ "EnableCHdrAFull", 4, 1 },
|
|
{ "EnableEMacAFull", 3, 1 },
|
|
{ "EnableNonOfdTidRss", 2, 1 },
|
|
{ "EnableNonOfdTcbRss", 1, 1 },
|
|
{ "EnableTnlOfdClosed", 0, 1 },
|
|
{ "TP_TCP_BACKOFF_REG0", 0x7d50, 0 },
|
|
{ "TimerBackoffIndex3", 24, 8 },
|
|
{ "TimerBackoffIndex2", 16, 8 },
|
|
{ "TimerBackoffIndex1", 8, 8 },
|
|
{ "TimerBackoffIndex0", 0, 8 },
|
|
{ "TP_TCP_BACKOFF_REG1", 0x7d54, 0 },
|
|
{ "TimerBackoffIndex7", 24, 8 },
|
|
{ "TimerBackoffIndex6", 16, 8 },
|
|
{ "TimerBackoffIndex5", 8, 8 },
|
|
{ "TimerBackoffIndex4", 0, 8 },
|
|
{ "TP_TCP_BACKOFF_REG2", 0x7d58, 0 },
|
|
{ "TimerBackoffIndex11", 24, 8 },
|
|
{ "TimerBackoffIndex10", 16, 8 },
|
|
{ "TimerBackoffIndex9", 8, 8 },
|
|
{ "TimerBackoffIndex8", 0, 8 },
|
|
{ "TP_TCP_BACKOFF_REG3", 0x7d5c, 0 },
|
|
{ "TimerBackoffIndex15", 24, 8 },
|
|
{ "TimerBackoffIndex14", 16, 8 },
|
|
{ "TimerBackoffIndex13", 8, 8 },
|
|
{ "TimerBackoffIndex12", 0, 8 },
|
|
{ "TP_PARA_REG0", 0x7d60, 0 },
|
|
{ "LimTxThresh", 28, 4 },
|
|
{ "InitCwndIdle", 27, 1 },
|
|
{ "InitCwnd", 24, 3 },
|
|
{ "DupAckThresh", 20, 4 },
|
|
{ "EcnCngFifo", 19, 1 },
|
|
{ "EcnSynAck", 18, 1 },
|
|
{ "EcnThresh", 16, 2 },
|
|
{ "EcnMode", 15, 1 },
|
|
{ "EcnModeCwr", 14, 1 },
|
|
{ "SetTimeEnable", 13, 1 },
|
|
{ "CplErrEnable", 12, 1 },
|
|
{ "FastTnlCnt", 11, 1 },
|
|
{ "ForceShove", 10, 1 },
|
|
{ "TpTcamKey", 9, 1 },
|
|
{ "SwsMode", 8, 1 },
|
|
{ "TsmpMode", 6, 2 },
|
|
{ "ByteCountLimit", 4, 2 },
|
|
{ "SwsShove", 3, 1 },
|
|
{ "TblTimer", 2, 1 },
|
|
{ "RxtPace", 1, 1 },
|
|
{ "SwsTimer", 0, 1 },
|
|
{ "TP_PARA_REG1", 0x7d64, 0 },
|
|
{ "InitRwnd", 16, 16 },
|
|
{ "InitialSSThresh", 0, 16 },
|
|
{ "TP_PARA_REG2", 0x7d68, 0 },
|
|
{ "MaxRxData", 16, 16 },
|
|
{ "RxCoalesceSize", 0, 16 },
|
|
{ "TP_PARA_REG3", 0x7d6c, 0 },
|
|
{ "EnableTnlCngLpbk", 31, 1 },
|
|
{ "EnableTnlCngFifo", 30, 1 },
|
|
{ "EnableTnlCngHdr", 29, 1 },
|
|
{ "EnableTnlCngSge", 28, 1 },
|
|
{ "RxMacCheck", 27, 1 },
|
|
{ "RxSynFilter", 26, 1 },
|
|
{ "CngCtrlECN", 25, 1 },
|
|
{ "RxDdpOffInit", 24, 1 },
|
|
{ "TunnelCngDrop3", 23, 1 },
|
|
{ "TunnelCngDrop2", 22, 1 },
|
|
{ "TunnelCngDrop1", 21, 1 },
|
|
{ "TunnelCngDrop0", 20, 1 },
|
|
{ "TxDataAckIdx", 16, 4 },
|
|
{ "RxFragEnable", 12, 3 },
|
|
{ "TxPaceFixedStrict", 11, 1 },
|
|
{ "TxPaceAutoStrict", 10, 1 },
|
|
{ "TxPaceFixed", 9, 1 },
|
|
{ "TxPaceAuto", 8, 1 },
|
|
{ "RxChnTunnel", 7, 1 },
|
|
{ "RxUrgTunnel", 6, 1 },
|
|
{ "RxUrgMode", 5, 1 },
|
|
{ "TxUrgMode", 4, 1 },
|
|
{ "CngCtrlMode", 2, 2 },
|
|
{ "RxCoalesceEnable", 1, 1 },
|
|
{ "RxCoalescePshEn", 0, 1 },
|
|
{ "TP_PARA_REG4", 0x7d70, 0 },
|
|
{ "IdleCwndHighSpeed", 28, 1 },
|
|
{ "RxmtCwndHighSpeed", 27, 1 },
|
|
{ "OverdriveHighSpeed", 25, 2 },
|
|
{ "ByteCountHighSpeed", 24, 1 },
|
|
{ "IdleCwndNewReno", 20, 1 },
|
|
{ "RxmtCwndNewReno", 19, 1 },
|
|
{ "OverdriveNewReno", 17, 2 },
|
|
{ "ByteCountNewReno", 16, 1 },
|
|
{ "IdleCwndTahoe", 12, 1 },
|
|
{ "RxmtCwndTahoe", 11, 1 },
|
|
{ "OverdriveTahoe", 9, 2 },
|
|
{ "ByteCountTahoe", 8, 1 },
|
|
{ "IdleCwndReno", 4, 1 },
|
|
{ "RxmtCwndReno", 3, 1 },
|
|
{ "OverdriveReno", 1, 2 },
|
|
{ "ByteCountReno", 0, 1 },
|
|
{ "TP_PARA_REG5", 0x7d74, 0 },
|
|
{ "IndicateSize", 16, 16 },
|
|
{ "MaxProxySize", 12, 4 },
|
|
{ "EnableReadPdu", 11, 1 },
|
|
{ "EnableReadAhead", 10, 1 },
|
|
{ "EmptyRqEnable", 9, 1 },
|
|
{ "SchdEnable", 8, 1 },
|
|
{ "EnableXoffPdu", 7, 1 },
|
|
{ "EnableFcoeCheck", 6, 1 },
|
|
{ "EnableFragCheck", 5, 1 },
|
|
{ "RearmDdpOffset", 4, 1 },
|
|
{ "ResetDdpOffset", 3, 1 },
|
|
{ "OnFlyDDPEnable", 2, 1 },
|
|
{ "EnableRdmaFix", 1, 1 },
|
|
{ "PushTimerEnable", 0, 1 },
|
|
{ "TP_PARA_REG6", 0x7d78, 0 },
|
|
{ "TxPDUSizeAdj", 24, 8 },
|
|
{ "TxTcamKey", 22, 1 },
|
|
{ "EnableCByp", 21, 1 },
|
|
{ "DisablePDUAck", 20, 1 },
|
|
{ "EnableCSav", 19, 1 },
|
|
{ "EnableDeferPDU", 18, 1 },
|
|
{ "EnableFlush", 17, 1 },
|
|
{ "EnableBytePersist", 16, 1 },
|
|
{ "DisableTmoCng", 15, 1 },
|
|
{ "EnableReadAhead", 14, 1 },
|
|
{ "AllowExeption", 13, 1 },
|
|
{ "EnableDeferACK", 12, 1 },
|
|
{ "EnableESnd", 11, 1 },
|
|
{ "EnableCSnd", 10, 1 },
|
|
{ "EnablePDUE", 9, 1 },
|
|
{ "EnablePDUC", 8, 1 },
|
|
{ "EnableBUFI", 7, 1 },
|
|
{ "EnableBUFE", 6, 1 },
|
|
{ "EnableDefer", 5, 1 },
|
|
{ "EnableClearRxmtOos", 4, 1 },
|
|
{ "DisablePDUCng", 3, 1 },
|
|
{ "DisablePDUTimeout", 2, 1 },
|
|
{ "DisablePDURxmt", 1, 1 },
|
|
{ "DisablePDUxmt", 0, 1 },
|
|
{ "TP_PARA_REG7", 0x7d7c, 0 },
|
|
{ "PMMaxXferLen1", 16, 16 },
|
|
{ "PMMaxXferLen0", 0, 16 },
|
|
{ "TP_ENG_CONFIG", 0x7d80, 0 },
|
|
{ "TableLatencyDone", 28, 4 },
|
|
{ "TableLatencyStart", 24, 4 },
|
|
{ "EngineLatencyDelta", 16, 4 },
|
|
{ "EngineLatencyMmgr", 12, 4 },
|
|
{ "EngineLatencyWireIp6", 8, 4 },
|
|
{ "EngineLatencyWire", 4, 4 },
|
|
{ "EngineLatencyBase", 0, 4 },
|
|
{ "TP_PARA_REG8", 0x7d84, 0 },
|
|
{ "EcnAckEct", 2, 1 },
|
|
{ "EcnFinEct", 1, 1 },
|
|
{ "EcnSynEct", 0, 1 },
|
|
{ "TP_ERR_CONFIG", 0x7d8c, 0 },
|
|
{ "TnlErrorFPMA", 31, 1 },
|
|
{ "TnlErrorPing", 30, 1 },
|
|
{ "TnlErrorCsum", 29, 1 },
|
|
{ "TnlErrorCsumIP", 28, 1 },
|
|
{ "TnlErrorOpaque", 27, 1 },
|
|
{ "TnlErrorIp6Opt", 26, 1 },
|
|
{ "TnlErrorTcpOpt", 25, 1 },
|
|
{ "TnlErrorPktLen", 24, 1 },
|
|
{ "TnlErrorTcpHdrLen", 23, 1 },
|
|
{ "TnlErrorIpHdrLen", 22, 1 },
|
|
{ "TnlErrorEthHdrLen", 21, 1 },
|
|
{ "TnlErrorAttack", 20, 1 },
|
|
{ "TnlErrorFrag", 19, 1 },
|
|
{ "TnlErrorIpVer", 18, 1 },
|
|
{ "TnlErrorMac", 17, 1 },
|
|
{ "TnlErrorAny", 16, 1 },
|
|
{ "DropErrorFPMA", 15, 1 },
|
|
{ "DropErrorPing", 14, 1 },
|
|
{ "DropErrorCsum", 13, 1 },
|
|
{ "DropErrorCsumIP", 12, 1 },
|
|
{ "DropErrorOpaque", 11, 1 },
|
|
{ "DropErrorIp6Opt", 10, 1 },
|
|
{ "DropErrorTcpOpt", 9, 1 },
|
|
{ "DropErrorPktLen", 8, 1 },
|
|
{ "DropErrorTcpHdrLen", 7, 1 },
|
|
{ "DropErrorIpHdrLen", 6, 1 },
|
|
{ "DropErrorEthHdrLen", 5, 1 },
|
|
{ "DropErrorAttack", 4, 1 },
|
|
{ "DropErrorFrag", 3, 1 },
|
|
{ "DropErrorIpVer", 2, 1 },
|
|
{ "DropErrorMac", 1, 1 },
|
|
{ "DropErrorAny", 0, 1 },
|
|
{ "TP_TIMER_RESOLUTION", 0x7d90, 0 },
|
|
{ "TimerResolution", 16, 8 },
|
|
{ "TimestampResolution", 8, 8 },
|
|
{ "DelayedACKResolution", 0, 8 },
|
|
{ "TP_MSL", 0x7d94, 0 },
|
|
{ "TP_RXT_MIN", 0x7d98, 0 },
|
|
{ "TP_RXT_MAX", 0x7d9c, 0 },
|
|
{ "TP_PERS_MIN", 0x7da0, 0 },
|
|
{ "TP_PERS_MAX", 0x7da4, 0 },
|
|
{ "TP_KEEP_IDLE", 0x7da8, 0 },
|
|
{ "TP_KEEP_INTVL", 0x7dac, 0 },
|
|
{ "TP_INIT_SRTT", 0x7db0, 0 },
|
|
{ "MaxRtt", 16, 16 },
|
|
{ "InitSrtt", 0, 16 },
|
|
{ "TP_DACK_TIMER", 0x7db4, 0 },
|
|
{ "TP_FINWAIT2_TIMER", 0x7db8, 0 },
|
|
{ "TP_FAST_FINWAIT2_TIMER", 0x7dbc, 0 },
|
|
{ "TP_SHIFT_CNT", 0x7dc0, 0 },
|
|
{ "SynShiftMax", 24, 4 },
|
|
{ "RxtShiftMaxR1", 20, 4 },
|
|
{ "RxtShiftMaxR2", 16, 4 },
|
|
{ "PerShiftBackoffMax", 12, 4 },
|
|
{ "PerShiftMax", 8, 4 },
|
|
{ "KeepaliveMaxR1", 4, 4 },
|
|
{ "KeepaliveMaxR2", 0, 4 },
|
|
{ "TP_TM_CONFIG", 0x7dc4, 0 },
|
|
{ "TP_TIME_LO", 0x7dc8, 0 },
|
|
{ "TP_TIME_HI", 0x7dcc, 0 },
|
|
{ "TP_PORT_MTU_0", 0x7dd0, 0 },
|
|
{ "Port1MTUValue", 16, 16 },
|
|
{ "Port0MTUValue", 0, 16 },
|
|
{ "TP_PORT_MTU_1", 0x7dd4, 0 },
|
|
{ "Port3MTUValue", 16, 16 },
|
|
{ "Port2MTUValue", 0, 16 },
|
|
{ "TP_PACE_TABLE", 0x7dd8, 0 },
|
|
{ "TP_CCTRL_TABLE", 0x7ddc, 0 },
|
|
{ "RowIndex", 16, 16 },
|
|
{ "RowValue", 0, 16 },
|
|
{ "TP_MTU_TABLE", 0x7de4, 0 },
|
|
{ "MTUIndex", 24, 8 },
|
|
{ "MTUWidth", 16, 4 },
|
|
{ "MTUValue", 0, 14 },
|
|
{ "TP_ULP_TABLE", 0x7de8, 0 },
|
|
{ "ULPType7Length", 31, 1 },
|
|
{ "ULPType7Offset", 28, 3 },
|
|
{ "ULPType6Length", 27, 1 },
|
|
{ "ULPType6Offset", 24, 3 },
|
|
{ "ULPType5Length", 23, 1 },
|
|
{ "ULPType5Offset", 20, 3 },
|
|
{ "ULPType4Length", 19, 1 },
|
|
{ "ULPType4Offset", 16, 3 },
|
|
{ "ULPType3Length", 15, 1 },
|
|
{ "ULPType3Offset", 12, 3 },
|
|
{ "ULPType2Length", 11, 1 },
|
|
{ "ULPType2Offset", 8, 3 },
|
|
{ "ULPType1Length", 7, 1 },
|
|
{ "ULPType1Offset", 4, 3 },
|
|
{ "ULPType0Length", 3, 1 },
|
|
{ "ULPType0Offset", 0, 3 },
|
|
{ "TP_RSS_LKP_TABLE", 0x7dec, 0 },
|
|
{ "LkpTblRowVld", 31, 1 },
|
|
{ "LkpTblRowIdx", 20, 11 },
|
|
{ "LkpTblQueue1", 10, 10 },
|
|
{ "LkpTblQueue0", 0, 10 },
|
|
{ "TP_RSS_CONFIG", 0x7df0, 0 },
|
|
{ "TNL4tupEnIpv6", 31, 1 },
|
|
{ "TNL2tupEnIpv6", 30, 1 },
|
|
{ "TNL4tupEnIpv4", 29, 1 },
|
|
{ "TNL2tupEnIpv4", 28, 1 },
|
|
{ "TNLTcpSel", 27, 1 },
|
|
{ "TNLIp6Sel", 26, 1 },
|
|
{ "TNLVrtSel", 25, 1 },
|
|
{ "TNLMapEn", 24, 1 },
|
|
{ "TNLFcoeMode", 23, 1 },
|
|
{ "TNLFcoeSid", 22, 1 },
|
|
{ "TNLFcoeEn", 21, 1 },
|
|
{ "HashXor", 20, 1 },
|
|
{ "OFDHashSave", 19, 1 },
|
|
{ "OFDVrtSel", 18, 1 },
|
|
{ "OFDMapEn", 17, 1 },
|
|
{ "OFDLkpEn", 16, 1 },
|
|
{ "SYN4tupEnIpv6", 15, 1 },
|
|
{ "SYN2tupEnIpv6", 14, 1 },
|
|
{ "SYN4tupEnIpv4", 13, 1 },
|
|
{ "SYN2tupEnIpv4", 12, 1 },
|
|
{ "SYNIp6Sel", 11, 1 },
|
|
{ "SYNVrtSel", 10, 1 },
|
|
{ "SYNMapEn", 9, 1 },
|
|
{ "SYNLkpEn", 8, 1 },
|
|
{ "ChannelEnable", 7, 1 },
|
|
{ "PortEnable", 6, 1 },
|
|
{ "TNLAllLookup", 5, 1 },
|
|
{ "VirtEnable", 4, 1 },
|
|
{ "CongestionEnable", 3, 1 },
|
|
{ "HashToeplitz", 2, 1 },
|
|
{ "UdpEnable", 1, 1 },
|
|
{ "Disable", 0, 1 },
|
|
{ "TP_RSS_CONFIG_TNL", 0x7df4, 0 },
|
|
{ "MaskSize", 28, 4 },
|
|
{ "MaskFilter", 16, 11 },
|
|
{ "HashAll", 2, 1 },
|
|
{ "HashEth", 1, 1 },
|
|
{ "UseWireCh", 0, 1 },
|
|
{ "TP_RSS_CONFIG_OFD", 0x7df8, 0 },
|
|
{ "MaskSize", 28, 4 },
|
|
{ "RRCPLMapEn", 20, 1 },
|
|
{ "RRCPLQueWidth", 16, 4 },
|
|
{ "FrmwrQueMask", 12, 4 },
|
|
{ "TP_RSS_CONFIG_SYN", 0x7dfc, 0 },
|
|
{ "MaskSize", 28, 4 },
|
|
{ "UseWireCh", 0, 1 },
|
|
{ "TP_RSS_CONFIG_VRT", 0x7e00, 0 },
|
|
{ "KeyWrAddrX", 30, 2 },
|
|
{ "KeyExtend", 26, 1 },
|
|
{ "VfRdRg", 25, 1 },
|
|
{ "VfRdEn", 24, 1 },
|
|
{ "VfPerrEn", 23, 1 },
|
|
{ "KeyPerrEn", 22, 1 },
|
|
{ "VfVlanEn", 21, 1 },
|
|
{ "VfFwEn", 20, 1 },
|
|
{ "HashDelay", 16, 4 },
|
|
{ "VfWrAddr", 8, 8 },
|
|
{ "KeyMode", 6, 2 },
|
|
{ "VfWrEn", 5, 1 },
|
|
{ "KeyWrEn", 4, 1 },
|
|
{ "KeyWrAddr", 0, 4 },
|
|
{ "TP_RSS_CONFIG_CNG", 0x7e04, 0 },
|
|
{ "ChnCount3", 31, 1 },
|
|
{ "ChnCount2", 30, 1 },
|
|
{ "ChnCount1", 29, 1 },
|
|
{ "ChnCount0", 28, 1 },
|
|
{ "ChnUndFlow3", 27, 1 },
|
|
{ "ChnUndFlow2", 26, 1 },
|
|
{ "ChnUndFlow1", 25, 1 },
|
|
{ "ChnUndFlow0", 24, 1 },
|
|
{ "ChnOvrFlow3", 23, 1 },
|
|
{ "ChnOvrFlow2", 22, 1 },
|
|
{ "ChnOvrFlow1", 21, 1 },
|
|
{ "ChnOvrFlow0", 20, 1 },
|
|
{ "RstChn3", 19, 1 },
|
|
{ "RstChn2", 18, 1 },
|
|
{ "RstChn1", 17, 1 },
|
|
{ "RstChn0", 16, 1 },
|
|
{ "UpdVld", 15, 1 },
|
|
{ "Xoff", 14, 1 },
|
|
{ "UpdChn3", 13, 1 },
|
|
{ "UpdChn2", 12, 1 },
|
|
{ "UpdChn1", 11, 1 },
|
|
{ "UpdChn0", 10, 1 },
|
|
{ "Queue", 0, 10 },
|
|
{ "TP_LA_TABLE_0", 0x7e10, 0 },
|
|
{ "VirtPort1Table", 16, 16 },
|
|
{ "VirtPort0Table", 0, 16 },
|
|
{ "TP_LA_TABLE_1", 0x7e14, 0 },
|
|
{ "VirtPort3Table", 16, 16 },
|
|
{ "VirtPort2Table", 0, 16 },
|
|
{ "TP_TM_PIO_ADDR", 0x7e18, 0 },
|
|
{ "TP_TM_PIO_DATA", 0x7e1c, 0 },
|
|
{ "TP_MOD_CONFIG", 0x7e24, 0 },
|
|
{ "RxChannelWeight1", 24, 8 },
|
|
{ "RXChannelWeight0", 16, 8 },
|
|
{ "TimerMode", 8, 8 },
|
|
{ "TxChannelXoffEn", 0, 4 },
|
|
{ "TP_TX_MOD_QUEUE_REQ_MAP", 0x7e28, 0 },
|
|
{ "RX_MOD_WEIGHT", 24, 8 },
|
|
{ "TX_MOD_WEIGHT", 16, 8 },
|
|
{ "TX_MOD_QUEUE_REQ_MAP", 0, 16 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT1", 0x7e2c, 0 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT7", 24, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT6", 16, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT5", 8, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT4", 0, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT0", 0x7e30, 0 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT3", 24, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT2", 16, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT1", 8, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT0", 0, 8 },
|
|
{ "TP_TX_MOD_CHANNEL_WEIGHT", 0x7e34, 0 },
|
|
{ "CH3", 24, 8 },
|
|
{ "CH2", 16, 8 },
|
|
{ "CH1", 8, 8 },
|
|
{ "CH0", 0, 8 },
|
|
{ "TP_MOD_RATE_LIMIT", 0x7e38, 0 },
|
|
{ "RX_MOD_RATE_LIMIT_INC", 24, 8 },
|
|
{ "RX_MOD_RATE_LIMIT_TICK", 16, 8 },
|
|
{ "TX_MOD_RATE_LIMIT_INC", 8, 8 },
|
|
{ "TX_MOD_RATE_LIMIT_TICK", 0, 8 },
|
|
{ "TP_PIO_ADDR", 0x7e40, 0 },
|
|
{ "TP_PIO_DATA", 0x7e44, 0 },
|
|
{ "TP_RESET", 0x7e4c, 0 },
|
|
{ "FlstInitEnable", 1, 1 },
|
|
{ "TPReset", 0, 1 },
|
|
{ "TP_MIB_INDEX", 0x7e50, 0 },
|
|
{ "TP_MIB_DATA", 0x7e54, 0 },
|
|
{ "TP_SYNC_TIME_HI", 0x7e58, 0 },
|
|
{ "TP_SYNC_TIME_LO", 0x7e5c, 0 },
|
|
{ "TP_CMM_MM_RX_FLST_BASE", 0x7e60, 0 },
|
|
{ "TP_CMM_MM_TX_FLST_BASE", 0x7e64, 0 },
|
|
{ "TP_CMM_MM_PS_FLST_BASE", 0x7e68, 0 },
|
|
{ "TP_CMM_MM_MAX_PSTRUCT", 0x7e6c, 0 },
|
|
{ "TP_INT_ENABLE", 0x7e70, 0 },
|
|
{ "FlmTxFlstEmpty", 30, 1 },
|
|
{ "RssLkpPerr", 29, 1 },
|
|
{ "FlmPerrSet", 28, 1 },
|
|
{ "ProtocolSramPerr", 27, 1 },
|
|
{ "ArpLutPerr", 26, 1 },
|
|
{ "CmRcfOpPerr", 25, 1 },
|
|
{ "CmCachePerr", 24, 1 },
|
|
{ "CmRcfDataPerr", 23, 1 },
|
|
{ "DbL2tLutPerr", 22, 1 },
|
|
{ "DbTxTidPerr", 21, 1 },
|
|
{ "DbExtPerr", 20, 1 },
|
|
{ "DbOpPerr", 19, 1 },
|
|
{ "TmCachePerr", 18, 1 },
|
|
{ "ETpOutCplFifoPerr", 17, 1 },
|
|
{ "ETpOutTcpFifoPerr", 16, 1 },
|
|
{ "ETpOutIpFifoPerr", 15, 1 },
|
|
{ "ETpOutEthFifoPerr", 14, 1 },
|
|
{ "ETpInCplFifoPerr", 13, 1 },
|
|
{ "ETpInTcpOptFifoPerr", 12, 1 },
|
|
{ "ETpInTcpFifoPerr", 11, 1 },
|
|
{ "ETpInIpFifoPerr", 10, 1 },
|
|
{ "ETpInEthFifoPerr", 9, 1 },
|
|
{ "CTpOutCplFifoPerr", 8, 1 },
|
|
{ "CTpOutPldFifoPerr", 7, 1 },
|
|
{ "CTpOutIpFifoPerr", 6, 1 },
|
|
{ "CTpOutEthFifoPerr", 5, 1 },
|
|
{ "CTpInCplFifoPerr", 4, 1 },
|
|
{ "CTpInTcpOpFifoPerr", 3, 1 },
|
|
{ "PduFbkFifoPerr", 2, 1 },
|
|
{ "SrqTablePerr", 1, 1 },
|
|
{ "DelInvFifoPerr", 0, 1 },
|
|
{ "TP_INT_CAUSE", 0x7e74, 0 },
|
|
{ "FlmTxFlstEmpty", 30, 1 },
|
|
{ "RssLkpPerr", 29, 1 },
|
|
{ "FlmPerrSet", 28, 1 },
|
|
{ "ProtocolSramPerr", 27, 1 },
|
|
{ "ArpLutPerr", 26, 1 },
|
|
{ "CmRcfOpPerr", 25, 1 },
|
|
{ "CmCachePerr", 24, 1 },
|
|
{ "CmRcfDataPerr", 23, 1 },
|
|
{ "DbL2tLutPerr", 22, 1 },
|
|
{ "DbTxTidPerr", 21, 1 },
|
|
{ "DbExtPerr", 20, 1 },
|
|
{ "DbOpPerr", 19, 1 },
|
|
{ "TmCachePerr", 18, 1 },
|
|
{ "ETpOutCplFifoPerr", 17, 1 },
|
|
{ "ETpOutTcpFifoPerr", 16, 1 },
|
|
{ "ETpOutIpFifoPerr", 15, 1 },
|
|
{ "ETpOutEthFifoPerr", 14, 1 },
|
|
{ "ETpInCplFifoPerr", 13, 1 },
|
|
{ "ETpInTcpOptFifoPerr", 12, 1 },
|
|
{ "ETpInTcpFifoPerr", 11, 1 },
|
|
{ "ETpInIpFifoPerr", 10, 1 },
|
|
{ "ETpInEthFifoPerr", 9, 1 },
|
|
{ "CTpOutCplFifoPerr", 8, 1 },
|
|
{ "CTpOutPldFifoPerr", 7, 1 },
|
|
{ "CTpOutIpFifoPerr", 6, 1 },
|
|
{ "CTpOutEthFifoPerr", 5, 1 },
|
|
{ "CTpInCplFifoPerr", 4, 1 },
|
|
{ "CTpInTcpOpFifoPerr", 3, 1 },
|
|
{ "PduFbkFifoPerr", 2, 1 },
|
|
{ "SrqTablePerr", 1, 1 },
|
|
{ "DelInvFifoPerr", 0, 1 },
|
|
{ "TP_PER_ENABLE", 0x7e78, 0 },
|
|
{ "FlmTxFlstEmpty", 30, 1 },
|
|
{ "RssLkpPerr", 29, 1 },
|
|
{ "FlmPerrSet", 28, 1 },
|
|
{ "ProtocolSramPerr", 27, 1 },
|
|
{ "ArpLutPerr", 26, 1 },
|
|
{ "CmRcfOpPerr", 25, 1 },
|
|
{ "CmCachePerr", 24, 1 },
|
|
{ "CmRcfDataPerr", 23, 1 },
|
|
{ "DbL2tLutPerr", 22, 1 },
|
|
{ "DbTxTidPerr", 21, 1 },
|
|
{ "DbExtPerr", 20, 1 },
|
|
{ "DbOpPerr", 19, 1 },
|
|
{ "TmCachePerr", 18, 1 },
|
|
{ "ETpOutCplFifoPerr", 17, 1 },
|
|
{ "ETpOutTcpFifoPerr", 16, 1 },
|
|
{ "ETpOutIpFifoPerr", 15, 1 },
|
|
{ "ETpOutEthFifoPerr", 14, 1 },
|
|
{ "ETpInCplFifoPerr", 13, 1 },
|
|
{ "ETpInTcpOptFifoPerr", 12, 1 },
|
|
{ "ETpInTcpFifoPerr", 11, 1 },
|
|
{ "ETpInIpFifoPerr", 10, 1 },
|
|
{ "ETpInEthFifoPerr", 9, 1 },
|
|
{ "CTpOutCplFifoPerr", 8, 1 },
|
|
{ "CTpOutPldFifoPerr", 7, 1 },
|
|
{ "CTpOutIpFifoPerr", 6, 1 },
|
|
{ "CTpOutEthFifoPerr", 5, 1 },
|
|
{ "CTpInCplFifoPerr", 4, 1 },
|
|
{ "CTpInTcpOpFifoPerr", 3, 1 },
|
|
{ "PduFbkFifoPerr", 2, 1 },
|
|
{ "SrqTablePerr", 1, 1 },
|
|
{ "DelInvFifoPerr", 0, 1 },
|
|
{ "TP_FLM_FREE_PS_CNT", 0x7e80, 0 },
|
|
{ "TP_FLM_FREE_RX_CNT", 0x7e84, 0 },
|
|
{ "FreeRxPageChn", 28, 1 },
|
|
{ "FreeRxPageCount", 0, 21 },
|
|
{ "TP_FLM_FREE_TX_CNT", 0x7e88, 0 },
|
|
{ "FreeTxPageChn", 28, 2 },
|
|
{ "FreeTxPageCount", 0, 21 },
|
|
{ "TP_TM_HEAP_PUSH_CNT", 0x7e8c, 0 },
|
|
{ "TP_TM_HEAP_POP_CNT", 0x7e90, 0 },
|
|
{ "TP_TM_DACK_PUSH_CNT", 0x7e94, 0 },
|
|
{ "TP_TM_DACK_POP_CNT", 0x7e98, 0 },
|
|
{ "TP_TM_MOD_PUSH_CNT", 0x7e9c, 0 },
|
|
{ "TP_MOD_POP_CNT", 0x7ea0, 0 },
|
|
{ "TP_TIMER_SEPARATOR", 0x7ea4, 0 },
|
|
{ "TimerSeparator", 16, 16 },
|
|
{ "DisableTimeFreeze", 0, 1 },
|
|
{ "TP_STAMP_TIME", 0x7ea8, 0 },
|
|
{ "TP_DEBUG_FLAGS", 0x7eac, 0 },
|
|
{ "RxTimerCompBuffer", 27, 1 },
|
|
{ "RxTimerDackFirst", 26, 1 },
|
|
{ "RxTimerDack", 25, 1 },
|
|
{ "RxTimerHeartbeat", 24, 1 },
|
|
{ "RxPawsDrop", 23, 1 },
|
|
{ "RxUrgDataDrop", 22, 1 },
|
|
{ "RxFutureData", 21, 1 },
|
|
{ "RxRcvRxmData", 20, 1 },
|
|
{ "RxRcvOooDataFin", 19, 1 },
|
|
{ "RxRcvOooData", 18, 1 },
|
|
{ "RxRcvWndZero", 17, 1 },
|
|
{ "RxRcvWndLtMss", 16, 1 },
|
|
{ "TxDfrFast", 13, 1 },
|
|
{ "TxRxmMisc", 12, 1 },
|
|
{ "TxDupAckInc", 11, 1 },
|
|
{ "TxRxmUrg", 10, 1 },
|
|
{ "TxRxmFin", 9, 1 },
|
|
{ "TxRxmSyn", 8, 1 },
|
|
{ "TxRxmNewReno", 7, 1 },
|
|
{ "TxRxmFast", 6, 1 },
|
|
{ "TxRxmTimer", 5, 1 },
|
|
{ "TxRxmTimerKeepalive", 4, 1 },
|
|
{ "TxRxmTimerPersist", 3, 1 },
|
|
{ "TxRcvAdvShrunk", 2, 1 },
|
|
{ "TxRcvAdvZero", 1, 1 },
|
|
{ "TxRcvAdvLtMss", 0, 1 },
|
|
{ "TP_RX_SCHED", 0x7eb0, 0 },
|
|
{ "CommitReset1", 31, 1 },
|
|
{ "CommitReset0", 30, 1 },
|
|
{ "ForceCong1", 29, 1 },
|
|
{ "ForceCong0", 28, 1 },
|
|
{ "EnableLpbkFull1", 26, 2 },
|
|
{ "EnableLpbkFull0", 24, 2 },
|
|
{ "EnableFifoFull1", 22, 2 },
|
|
{ "EnablePcmdFull1", 20, 2 },
|
|
{ "EnableHdrFull1", 18, 2 },
|
|
{ "EnableFifoFull0", 16, 2 },
|
|
{ "EnablePcmdFull0", 14, 2 },
|
|
{ "EnableHdrFull0", 12, 2 },
|
|
{ "TP_TX_SCHED", 0x7eb4, 0 },
|
|
{ "CommitReset3", 31, 1 },
|
|
{ "CommitReset2", 30, 1 },
|
|
{ "CommitReset1", 29, 1 },
|
|
{ "CommitReset0", 28, 1 },
|
|
{ "ForceCong3", 27, 1 },
|
|
{ "ForceCong2", 26, 1 },
|
|
{ "ForceCong1", 25, 1 },
|
|
{ "ForceCong0", 24, 1 },
|
|
{ "CommitLimit3", 18, 6 },
|
|
{ "CommitLimit2", 12, 6 },
|
|
{ "CommitLimit1", 6, 6 },
|
|
{ "CommitLimit0", 0, 6 },
|
|
{ "TP_FX_SCHED", 0x7eb8, 0 },
|
|
{ "TxChnXoff3", 19, 1 },
|
|
{ "TxChnXoff2", 18, 1 },
|
|
{ "TxChnXoff1", 17, 1 },
|
|
{ "TxChnXoff0", 16, 1 },
|
|
{ "TxModXoff7", 15, 1 },
|
|
{ "TxModXoff6", 14, 1 },
|
|
{ "TxModXoff5", 13, 1 },
|
|
{ "TxModXoff4", 12, 1 },
|
|
{ "TxModXoff3", 11, 1 },
|
|
{ "TxModXoff2", 10, 1 },
|
|
{ "TxModXoff1", 9, 1 },
|
|
{ "TxModXoff0", 8, 1 },
|
|
{ "RxChnXoff3", 7, 1 },
|
|
{ "RxChnXoff2", 6, 1 },
|
|
{ "RxChnXoff1", 5, 1 },
|
|
{ "RxChnXoff0", 4, 1 },
|
|
{ "RxModXoff1", 1, 1 },
|
|
{ "RxModXoff0", 0, 1 },
|
|
{ "TP_TX_ORATE", 0x7ebc, 0 },
|
|
{ "OfdRate3", 24, 8 },
|
|
{ "OfdRate2", 16, 8 },
|
|
{ "OfdRate1", 8, 8 },
|
|
{ "OfdRate0", 0, 8 },
|
|
{ "TP_IX_SCHED0", 0x7ec0, 0 },
|
|
{ "TP_IX_SCHED1", 0x7ec4, 0 },
|
|
{ "TP_IX_SCHED2", 0x7ec8, 0 },
|
|
{ "TP_IX_SCHED3", 0x7ecc, 0 },
|
|
{ "TP_TX_TRATE", 0x7ed0, 0 },
|
|
{ "TnlRate3", 24, 8 },
|
|
{ "TnlRate2", 16, 8 },
|
|
{ "TnlRate1", 8, 8 },
|
|
{ "TnlRate0", 0, 8 },
|
|
{ "TP_DBG_LA_CONFIG", 0x7ed4, 0 },
|
|
{ "DbgLaOpcEnable", 24, 8 },
|
|
{ "DbgLaWhlf", 23, 1 },
|
|
{ "DbgLaWptr", 16, 7 },
|
|
{ "DbgLaMode", 14, 2 },
|
|
{ "DbgLaFatalFreeze", 13, 1 },
|
|
{ "DbgLaEnable", 12, 1 },
|
|
{ "DbgLaRptr", 0, 7 },
|
|
{ "TP_DBG_LA_DATAL", 0x7ed8, 0 },
|
|
{ "TP_DBG_LA_DATAH", 0x7edc, 0 },
|
|
{ "TP_PROTOCOL_CNTRL", 0x7ee8, 0 },
|
|
{ "WriteEnable", 31, 1 },
|
|
{ "TcamEnable", 10, 1 },
|
|
{ "BlockSelect", 8, 2 },
|
|
{ "LineAddress", 1, 7 },
|
|
{ "RequestDone", 0, 1 },
|
|
{ "TP_PROTOCOL_DATA0", 0x7eec, 0 },
|
|
{ "TP_PROTOCOL_DATA1", 0x7ef0, 0 },
|
|
{ "TP_PROTOCOL_DATA2", 0x7ef4, 0 },
|
|
{ "TP_PROTOCOL_DATA3", 0x7ef8, 0 },
|
|
{ "TP_PROTOCOL_DATA4", 0x7efc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_ulp_tx_regs[] = {
|
|
{ "ULP_TX_CONFIG", 0x8dc0, 0 },
|
|
{ "ULIMIT_EXCLUSIVE_FIX", 16, 1 },
|
|
{ "ISO_A_FLAG_EN", 15, 1 },
|
|
{ "IWARP_SEQ_FLIT_DIS", 14, 1 },
|
|
{ "MR_SIZE_FIX_EN", 13, 1 },
|
|
{ "T10_ISO_FIX_EN", 12, 1 },
|
|
{ "CPL_FLAGS_UPDATE_EN", 11, 1 },
|
|
{ "IWARP_SEQ_UPDATE_EN", 10, 1 },
|
|
{ "SEQ_UPDATE_EN", 9, 1 },
|
|
{ "ERR_ITT_EN", 8, 1 },
|
|
{ "atomic_fix_dis", 7, 1 },
|
|
{ "PHYS_ADDR_RESP_EN", 6, 1 },
|
|
{ "ENDIANESS_CHANGE", 5, 1 },
|
|
{ "ERR_RTAG_EN", 4, 1 },
|
|
{ "TSO_ETHLEN_EN", 3, 1 },
|
|
{ "emsg_more_info", 2, 1 },
|
|
{ "LOSDR", 1, 1 },
|
|
{ "extra_tag_insertion_enable", 0, 1 },
|
|
{ "ULP_TX_PERR_INJECT", 0x8dc4, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "ULP_TX_INT_ENABLE", 0x8dc8, 0 },
|
|
{ "Pbl_bound_err_ch3", 31, 1 },
|
|
{ "Pbl_bound_err_ch2", 30, 1 },
|
|
{ "Pbl_bound_err_ch1", 29, 1 },
|
|
{ "Pbl_bound_err_ch0", 28, 1 },
|
|
{ "sge2ulp_fifo_perr_set3", 27, 1 },
|
|
{ "sge2ulp_fifo_perr_set2", 26, 1 },
|
|
{ "sge2ulp_fifo_perr_set1", 25, 1 },
|
|
{ "sge2ulp_fifo_perr_set0", 24, 1 },
|
|
{ "cim2ulp_fifo_perr_set3", 23, 1 },
|
|
{ "cim2ulp_fifo_perr_set2", 22, 1 },
|
|
{ "cim2ulp_fifo_perr_set1", 21, 1 },
|
|
{ "cim2ulp_fifo_perr_set0", 20, 1 },
|
|
{ "CQE_fifo_perr_set3", 19, 1 },
|
|
{ "CQE_fifo_perr_set2", 18, 1 },
|
|
{ "CQE_fifo_perr_set1", 17, 1 },
|
|
{ "CQE_fifo_perr_set0", 16, 1 },
|
|
{ "pbl_fifo_perr_set3", 15, 1 },
|
|
{ "pbl_fifo_perr_set2", 14, 1 },
|
|
{ "pbl_fifo_perr_set1", 13, 1 },
|
|
{ "pbl_fifo_perr_set0", 12, 1 },
|
|
{ "cmd_fifo_perr_set3", 11, 1 },
|
|
{ "cmd_fifo_perr_set2", 10, 1 },
|
|
{ "cmd_fifo_perr_set1", 9, 1 },
|
|
{ "cmd_fifo_perr_set0", 8, 1 },
|
|
{ "lso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "lso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "lso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "lso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "ULP_TX_INT_CAUSE", 0x8dcc, 0 },
|
|
{ "Pbl_bound_err_ch3", 31, 1 },
|
|
{ "Pbl_bound_err_ch2", 30, 1 },
|
|
{ "Pbl_bound_err_ch1", 29, 1 },
|
|
{ "Pbl_bound_err_ch0", 28, 1 },
|
|
{ "sge2ulp_fifo_perr_set3", 27, 1 },
|
|
{ "sge2ulp_fifo_perr_set2", 26, 1 },
|
|
{ "sge2ulp_fifo_perr_set1", 25, 1 },
|
|
{ "sge2ulp_fifo_perr_set0", 24, 1 },
|
|
{ "cim2ulp_fifo_perr_set3", 23, 1 },
|
|
{ "cim2ulp_fifo_perr_set2", 22, 1 },
|
|
{ "cim2ulp_fifo_perr_set1", 21, 1 },
|
|
{ "cim2ulp_fifo_perr_set0", 20, 1 },
|
|
{ "CQE_fifo_perr_set3", 19, 1 },
|
|
{ "CQE_fifo_perr_set2", 18, 1 },
|
|
{ "CQE_fifo_perr_set1", 17, 1 },
|
|
{ "CQE_fifo_perr_set0", 16, 1 },
|
|
{ "pbl_fifo_perr_set3", 15, 1 },
|
|
{ "pbl_fifo_perr_set2", 14, 1 },
|
|
{ "pbl_fifo_perr_set1", 13, 1 },
|
|
{ "pbl_fifo_perr_set0", 12, 1 },
|
|
{ "cmd_fifo_perr_set3", 11, 1 },
|
|
{ "cmd_fifo_perr_set2", 10, 1 },
|
|
{ "cmd_fifo_perr_set1", 9, 1 },
|
|
{ "cmd_fifo_perr_set0", 8, 1 },
|
|
{ "lso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "lso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "lso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "lso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "ULP_TX_PERR_ENABLE", 0x8dd0, 0 },
|
|
{ "sge2ulp_fifo_perr_set3", 27, 1 },
|
|
{ "sge2ulp_fifo_perr_set2", 26, 1 },
|
|
{ "sge2ulp_fifo_perr_set1", 25, 1 },
|
|
{ "sge2ulp_fifo_perr_set0", 24, 1 },
|
|
{ "cim2ulp_fifo_perr_set3", 23, 1 },
|
|
{ "cim2ulp_fifo_perr_set2", 22, 1 },
|
|
{ "cim2ulp_fifo_perr_set1", 21, 1 },
|
|
{ "cim2ulp_fifo_perr_set0", 20, 1 },
|
|
{ "CQE_fifo_perr_set3", 19, 1 },
|
|
{ "CQE_fifo_perr_set2", 18, 1 },
|
|
{ "CQE_fifo_perr_set1", 17, 1 },
|
|
{ "CQE_fifo_perr_set0", 16, 1 },
|
|
{ "pbl_fifo_perr_set3", 15, 1 },
|
|
{ "pbl_fifo_perr_set2", 14, 1 },
|
|
{ "pbl_fifo_perr_set1", 13, 1 },
|
|
{ "pbl_fifo_perr_set0", 12, 1 },
|
|
{ "cmd_fifo_perr_set3", 11, 1 },
|
|
{ "cmd_fifo_perr_set2", 10, 1 },
|
|
{ "cmd_fifo_perr_set1", 9, 1 },
|
|
{ "cmd_fifo_perr_set0", 8, 1 },
|
|
{ "lso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "lso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "lso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "lso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "ULP_TX_TPT_LLIMIT", 0x8dd4, 0 },
|
|
{ "ULP_TX_TPT_ULIMIT", 0x8dd8, 0 },
|
|
{ "ULP_TX_PBL_LLIMIT", 0x8ddc, 0 },
|
|
{ "ULP_TX_PBL_ULIMIT", 0x8de0, 0 },
|
|
{ "ULP_TX_TLS_CTL", 0x8de4, 0 },
|
|
{ "TlsPerrEn", 4, 1 },
|
|
{ "TlsPathCtl", 3, 1 },
|
|
{ "TlsDisableIFuse", 2, 1 },
|
|
{ "TlsDisableCFuse", 1, 1 },
|
|
{ "TlsDisable", 0, 1 },
|
|
{ "ULP_TX_CPL_PACK_SIZE1", 0x8df8, 0 },
|
|
{ "Ch3Size1", 24, 8 },
|
|
{ "Ch2Size1", 16, 8 },
|
|
{ "Ch1Size1", 8, 8 },
|
|
{ "Ch0Size1", 0, 8 },
|
|
{ "ULP_TX_CPL_PACK_SIZE2", 0x8dfc, 0 },
|
|
{ "Ch3Size2", 24, 8 },
|
|
{ "Ch2Size2", 16, 8 },
|
|
{ "Ch1Size2", 8, 8 },
|
|
{ "Ch0Size2", 0, 8 },
|
|
{ "ULP_TX_ERR_MSG2CIM", 0x8e00, 0 },
|
|
{ "ULP_TX_ERR_TABLE_BASE", 0x8e04, 0 },
|
|
{ "ULP_TX_ERR_CNT_CH0", 0x8e10, 0 },
|
|
{ "ULP_TX_ERR_CNT_CH1", 0x8e14, 0 },
|
|
{ "ULP_TX_ERR_CNT_CH2", 0x8e18, 0 },
|
|
{ "ULP_TX_ERR_CNT_CH3", 0x8e1c, 0 },
|
|
{ "ULP_TX_FC_SOF", 0x8e20, 0 },
|
|
{ "SOF_FS3", 24, 8 },
|
|
{ "SOF_FS2", 16, 8 },
|
|
{ "SOF_3", 8, 8 },
|
|
{ "SOF_2", 0, 8 },
|
|
{ "ULP_TX_FC_EOF", 0x8e24, 0 },
|
|
{ "EOF_LS3", 24, 8 },
|
|
{ "EOF_LS2", 16, 8 },
|
|
{ "EOF_3", 8, 8 },
|
|
{ "EOF_2", 0, 8 },
|
|
{ "ULP_TX_CGEN_GLOBAL", 0x8e28, 0 },
|
|
{ "ULP_TX_CGEN", 0x8e2c, 0 },
|
|
{ "ULP_TX_CGEN_Storage", 8, 4 },
|
|
{ "ULP_TX_CGEN_RDMA", 4, 4 },
|
|
{ "ULP_TX_CGEN_Channel", 0, 4 },
|
|
{ "ULP_TX_MEM_CFG", 0x8e30, 0 },
|
|
{ "ULP_TX_PERR_INJECT_2", 0x8e34, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "ULP_TX_FPGA_CMD_CTRL", 0x8e38, 0 },
|
|
{ "ULP_TX_FPGA_CMD_0", 0x8e3c, 0 },
|
|
{ "ULP_TX_FPGA_CMD_1", 0x8e40, 0 },
|
|
{ "ULP_TX_FPGA_CMD_2", 0x8e44, 0 },
|
|
{ "ULP_TX_FPGA_CMD_3", 0x8e48, 0 },
|
|
{ "ULP_TX_FPGA_CMD_4", 0x8e4c, 0 },
|
|
{ "ULP_TX_FPGA_CMD_5", 0x8e50, 0 },
|
|
{ "ULP_TX_FPGA_CMD_6", 0x8e54, 0 },
|
|
{ "ULP_TX_FPGA_CMD_7", 0x8e58, 0 },
|
|
{ "ULP_TX_FPGA_CMD_8", 0x8e5c, 0 },
|
|
{ "ULP_TX_FPGA_CMD_9", 0x8e60, 0 },
|
|
{ "ULP_TX_FPGA_CMD_10", 0x8e64, 0 },
|
|
{ "ULP_TX_FPGA_CMD_11", 0x8e68, 0 },
|
|
{ "ULP_TX_FPGA_CMD_12", 0x8e6c, 0 },
|
|
{ "ULP_TX_FPGA_CMD_13", 0x8e70, 0 },
|
|
{ "ULP_TX_FPGA_CMD_14", 0x8e74, 0 },
|
|
{ "ULP_TX_FPGA_CMD_15", 0x8e78, 0 },
|
|
{ "ULP_TX_INT_ENABLE_2", 0x8e7c, 0 },
|
|
{ "edma_in_fifo_perr_set3", 31, 1 },
|
|
{ "edma_in_fifo_perr_set2", 30, 1 },
|
|
{ "edma_in_fifo_perr_set1", 29, 1 },
|
|
{ "edma_in_fifo_perr_set0", 28, 1 },
|
|
{ "align_ctl_fifo_perr_set3", 27, 1 },
|
|
{ "align_ctl_fifo_perr_set2", 26, 1 },
|
|
{ "align_ctl_fifo_perr_set1", 25, 1 },
|
|
{ "align_ctl_fifo_perr_set0", 24, 1 },
|
|
{ "sge_fifo_perr_set3", 23, 1 },
|
|
{ "sge_fifo_perr_set2", 22, 1 },
|
|
{ "sge_fifo_perr_set1", 21, 1 },
|
|
{ "sge_fifo_perr_set0", 20, 1 },
|
|
{ "stag_fifo_perr_set3", 19, 1 },
|
|
{ "stag_fifo_perr_set2", 18, 1 },
|
|
{ "stag_fifo_perr_set1", 17, 1 },
|
|
{ "stag_fifo_perr_set0", 16, 1 },
|
|
{ "map_fifo_perr_set3", 15, 1 },
|
|
{ "map_fifo_perr_set2", 14, 1 },
|
|
{ "map_fifo_perr_set1", 13, 1 },
|
|
{ "map_fifo_perr_set0", 12, 1 },
|
|
{ "dma_fifo_perr_set3", 11, 1 },
|
|
{ "dma_fifo_perr_set2", 10, 1 },
|
|
{ "dma_fifo_perr_set1", 9, 1 },
|
|
{ "dma_fifo_perr_set0", 8, 1 },
|
|
{ "fso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "fso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "fso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "fso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "t10_pi_sram_perr_set3", 3, 1 },
|
|
{ "t10_pi_sram_perr_set2", 2, 1 },
|
|
{ "t10_pi_sram_perr_set1", 1, 1 },
|
|
{ "t10_pi_sram_perr_set0", 0, 1 },
|
|
{ "ULP_TX_INT_CAUSE_2", 0x8e80, 0 },
|
|
{ "edma_in_fifo_perr_set3", 31, 1 },
|
|
{ "edma_in_fifo_perr_set2", 30, 1 },
|
|
{ "edma_in_fifo_perr_set1", 29, 1 },
|
|
{ "edma_in_fifo_perr_set0", 28, 1 },
|
|
{ "align_ctl_fifo_perr_set3", 27, 1 },
|
|
{ "align_ctl_fifo_perr_set2", 26, 1 },
|
|
{ "align_ctl_fifo_perr_set1", 25, 1 },
|
|
{ "align_ctl_fifo_perr_set0", 24, 1 },
|
|
{ "sge_fifo_perr_set3", 23, 1 },
|
|
{ "sge_fifo_perr_set2", 22, 1 },
|
|
{ "sge_fifo_perr_set1", 21, 1 },
|
|
{ "sge_fifo_perr_set0", 20, 1 },
|
|
{ "stag_fifo_perr_set3", 19, 1 },
|
|
{ "stag_fifo_perr_set2", 18, 1 },
|
|
{ "stag_fifo_perr_set1", 17, 1 },
|
|
{ "stag_fifo_perr_set0", 16, 1 },
|
|
{ "map_fifo_perr_set3", 15, 1 },
|
|
{ "map_fifo_perr_set2", 14, 1 },
|
|
{ "map_fifo_perr_set1", 13, 1 },
|
|
{ "map_fifo_perr_set0", 12, 1 },
|
|
{ "dma_fifo_perr_set3", 11, 1 },
|
|
{ "dma_fifo_perr_set2", 10, 1 },
|
|
{ "dma_fifo_perr_set1", 9, 1 },
|
|
{ "dma_fifo_perr_set0", 8, 1 },
|
|
{ "fso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "fso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "fso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "fso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "t10_pi_sram_perr_set3", 3, 1 },
|
|
{ "t10_pi_sram_perr_set2", 2, 1 },
|
|
{ "t10_pi_sram_perr_set1", 1, 1 },
|
|
{ "t10_pi_sram_perr_set0", 0, 1 },
|
|
{ "ULP_TX_PERR_ENABLE_2", 0x8e84, 0 },
|
|
{ "edma_in_fifo_perr_set3", 31, 1 },
|
|
{ "edma_in_fifo_perr_set2", 30, 1 },
|
|
{ "edma_in_fifo_perr_set1", 29, 1 },
|
|
{ "edma_in_fifo_perr_set0", 28, 1 },
|
|
{ "align_ctl_fifo_perr_set3", 27, 1 },
|
|
{ "align_ctl_fifo_perr_set2", 26, 1 },
|
|
{ "align_ctl_fifo_perr_set1", 25, 1 },
|
|
{ "align_ctl_fifo_perr_set0", 24, 1 },
|
|
{ "sge_fifo_perr_set3", 23, 1 },
|
|
{ "sge_fifo_perr_set2", 22, 1 },
|
|
{ "sge_fifo_perr_set1", 21, 1 },
|
|
{ "sge_fifo_perr_set0", 20, 1 },
|
|
{ "stag_fifo_perr_set3", 19, 1 },
|
|
{ "stag_fifo_perr_set2", 18, 1 },
|
|
{ "stag_fifo_perr_set1", 17, 1 },
|
|
{ "stag_fifo_perr_set0", 16, 1 },
|
|
{ "map_fifo_perr_set3", 15, 1 },
|
|
{ "map_fifo_perr_set2", 14, 1 },
|
|
{ "map_fifo_perr_set1", 13, 1 },
|
|
{ "map_fifo_perr_set0", 12, 1 },
|
|
{ "dma_fifo_perr_set3", 11, 1 },
|
|
{ "dma_fifo_perr_set2", 10, 1 },
|
|
{ "dma_fifo_perr_set1", 9, 1 },
|
|
{ "dma_fifo_perr_set0", 8, 1 },
|
|
{ "fso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "fso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "fso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "fso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "t10_pi_sram_perr_set3", 3, 1 },
|
|
{ "t10_pi_sram_perr_set2", 2, 1 },
|
|
{ "t10_pi_sram_perr_set1", 1, 1 },
|
|
{ "t10_pi_sram_perr_set0", 0, 1 },
|
|
{ "ULP_TX_SE_CNT_ERR", 0x8ea0, 0 },
|
|
{ "ERR_CH3", 12, 4 },
|
|
{ "ERR_CH2", 8, 4 },
|
|
{ "ERR_CH1", 4, 4 },
|
|
{ "ERR_CH0", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CLR", 0x8ea4, 0 },
|
|
{ "CLR_DROP", 16, 4 },
|
|
{ "CLR_CH3", 12, 4 },
|
|
{ "CLR_CH2", 8, 4 },
|
|
{ "CLR_CH1", 4, 4 },
|
|
{ "CLR_CH0", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CH0", 0x8ea8, 0 },
|
|
{ "SOP_CNT_ULP2TP", 28, 4 },
|
|
{ "EOP_CNT_ULP2TP", 24, 4 },
|
|
{ "SOP_CNT_LSO_IN", 20, 4 },
|
|
{ "EOP_CNT_LSO_IN", 16, 4 },
|
|
{ "SOP_CNT_ALG_IN", 12, 4 },
|
|
{ "EOP_CNT_ALG_IN", 8, 4 },
|
|
{ "SOP_CNT_CIM2ULP", 4, 4 },
|
|
{ "EOP_CNT_CIM2ULP", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CH1", 0x8eac, 0 },
|
|
{ "SOP_CNT_ULP2TP", 28, 4 },
|
|
{ "EOP_CNT_ULP2TP", 24, 4 },
|
|
{ "SOP_CNT_LSO_IN", 20, 4 },
|
|
{ "EOP_CNT_LSO_IN", 16, 4 },
|
|
{ "SOP_CNT_ALG_IN", 12, 4 },
|
|
{ "EOP_CNT_ALG_IN", 8, 4 },
|
|
{ "SOP_CNT_CIM2ULP", 4, 4 },
|
|
{ "EOP_CNT_CIM2ULP", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CH2", 0x8eb0, 0 },
|
|
{ "SOP_CNT_ULP2TP", 28, 4 },
|
|
{ "EOP_CNT_ULP2TP", 24, 4 },
|
|
{ "SOP_CNT_LSO_IN", 20, 4 },
|
|
{ "EOP_CNT_LSO_IN", 16, 4 },
|
|
{ "SOP_CNT_ALG_IN", 12, 4 },
|
|
{ "EOP_CNT_ALG_IN", 8, 4 },
|
|
{ "SOP_CNT_CIM2ULP", 4, 4 },
|
|
{ "EOP_CNT_CIM2ULP", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CH3", 0x8eb4, 0 },
|
|
{ "SOP_CNT_ULP2TP", 28, 4 },
|
|
{ "EOP_CNT_ULP2TP", 24, 4 },
|
|
{ "SOP_CNT_LSO_IN", 20, 4 },
|
|
{ "EOP_CNT_LSO_IN", 16, 4 },
|
|
{ "SOP_CNT_ALG_IN", 12, 4 },
|
|
{ "EOP_CNT_ALG_IN", 8, 4 },
|
|
{ "SOP_CNT_CIM2ULP", 4, 4 },
|
|
{ "EOP_CNT_CIM2ULP", 0, 4 },
|
|
{ "ULP_TX_DROP_CNT", 0x8eb8, 0 },
|
|
{ "DROP_INVLD_MC_CH3", 28, 4 },
|
|
{ "DROP_INVLD_MC_CH2", 24, 4 },
|
|
{ "DROP_INVLD_MC_CH1", 20, 4 },
|
|
{ "DROP_INVLD_MC_CH0", 16, 4 },
|
|
{ "DROP_CH3", 12, 4 },
|
|
{ "DROP_CH2", 8, 4 },
|
|
{ "DROP_CH1", 4, 4 },
|
|
{ "DROP_CH0", 0, 4 },
|
|
{ "ULP_TX_CSU_REVISION", 0x8ebc, 0 },
|
|
{ "ULP_TX_LA_RDPTR_0", 0x8ec0, 0 },
|
|
{ "ULP_TX_LA_RDDATA_0", 0x8ec4, 0 },
|
|
{ "ULP_TX_LA_WRPTR_0", 0x8ec8, 0 },
|
|
{ "ULP_TX_LA_RESERVED_0", 0x8ecc, 0 },
|
|
{ "ULP_TX_LA_RDPTR_1", 0x8ed0, 0 },
|
|
{ "ULP_TX_LA_RDDATA_1", 0x8ed4, 0 },
|
|
{ "ULP_TX_LA_WRPTR_1", 0x8ed8, 0 },
|
|
{ "ULP_TX_LA_RESERVED_1", 0x8edc, 0 },
|
|
{ "ULP_TX_LA_RDPTR_2", 0x8ee0, 0 },
|
|
{ "ULP_TX_LA_RDDATA_2", 0x8ee4, 0 },
|
|
{ "ULP_TX_LA_WRPTR_2", 0x8ee8, 0 },
|
|
{ "ULP_TX_LA_RESERVED_2", 0x8eec, 0 },
|
|
{ "ULP_TX_LA_RDPTR_3", 0x8ef0, 0 },
|
|
{ "ULP_TX_LA_RDDATA_3", 0x8ef4, 0 },
|
|
{ "ULP_TX_LA_WRPTR_3", 0x8ef8, 0 },
|
|
{ "ULP_TX_LA_RESERVED_3", 0x8efc, 0 },
|
|
{ "ULP_TX_LA_RDPTR_4", 0x8f00, 0 },
|
|
{ "ULP_TX_LA_RDDATA_4", 0x8f04, 0 },
|
|
{ "ULP_TX_LA_WRPTR_4", 0x8f08, 0 },
|
|
{ "ULP_TX_LA_RESERVED_4", 0x8f0c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_5", 0x8f10, 0 },
|
|
{ "ULP_TX_LA_RDDATA_5", 0x8f14, 0 },
|
|
{ "ULP_TX_LA_WRPTR_5", 0x8f18, 0 },
|
|
{ "ULP_TX_LA_RESERVED_5", 0x8f1c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_6", 0x8f20, 0 },
|
|
{ "ULP_TX_LA_RDDATA_6", 0x8f24, 0 },
|
|
{ "ULP_TX_LA_WRPTR_6", 0x8f28, 0 },
|
|
{ "ULP_TX_LA_RESERVED_6", 0x8f2c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_7", 0x8f30, 0 },
|
|
{ "ULP_TX_LA_RDDATA_7", 0x8f34, 0 },
|
|
{ "ULP_TX_LA_WRPTR_7", 0x8f38, 0 },
|
|
{ "ULP_TX_LA_RESERVED_7", 0x8f3c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_8", 0x8f40, 0 },
|
|
{ "ULP_TX_LA_RDDATA_8", 0x8f44, 0 },
|
|
{ "ULP_TX_LA_WRPTR_8", 0x8f48, 0 },
|
|
{ "ULP_TX_LA_RESERVED_8", 0x8f4c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_9", 0x8f50, 0 },
|
|
{ "ULP_TX_LA_RDDATA_9", 0x8f54, 0 },
|
|
{ "ULP_TX_LA_WRPTR_9", 0x8f58, 0 },
|
|
{ "ULP_TX_LA_RESERVED_9", 0x8f5c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_10", 0x8f60, 0 },
|
|
{ "ULP_TX_LA_RDDATA_10", 0x8f64, 0 },
|
|
{ "ULP_TX_LA_WRPTR_10", 0x8f68, 0 },
|
|
{ "ULP_TX_LA_RESERVED_10", 0x8f6c, 0 },
|
|
{ "ULP_TX_ASIC_DEBUG_CTRL", 0x8f70, 0 },
|
|
{ "ULP_TX_CPL_TX_DATA_FLAGS_MASK", 0x8f88, 0 },
|
|
{ "bypass_first", 26, 1 },
|
|
{ "bypass_middle", 25, 1 },
|
|
{ "bypass_last", 24, 1 },
|
|
{ "push_first", 22, 1 },
|
|
{ "push_middle", 21, 1 },
|
|
{ "push_last", 20, 1 },
|
|
{ "save_first", 18, 1 },
|
|
{ "save_middle", 17, 1 },
|
|
{ "save_last", 16, 1 },
|
|
{ "flush_first", 14, 1 },
|
|
{ "flush_middle", 13, 1 },
|
|
{ "flush_last", 12, 1 },
|
|
{ "urgent_first", 10, 1 },
|
|
{ "urgent_middle", 9, 1 },
|
|
{ "urgent_last", 8, 1 },
|
|
{ "more_first", 6, 1 },
|
|
{ "more_middle", 5, 1 },
|
|
{ "more_last", 4, 1 },
|
|
{ "shove_first", 2, 1 },
|
|
{ "shove_middle", 1, 1 },
|
|
{ "shove_last", 0, 1 },
|
|
{ "ULP_TX_TLS_IND_CMD", 0x8fb8, 0 },
|
|
{ "ULP_TX_TLS_IND_DATA", 0x8fbc, 0 },
|
|
{ "ULP_TX_ASIC_DEBUG_0", 0x8f74, 0 },
|
|
{ "ULP_TX_ASIC_DEBUG_1", 0x8f78, 0 },
|
|
{ "ULP_TX_ASIC_DEBUG_2", 0x8f7c, 0 },
|
|
{ "ULP_TX_ASIC_DEBUG_3", 0x8f80, 0 },
|
|
{ "ULP_TX_ASIC_DEBUG_4", 0x8f84, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_pm_rx_regs[] = {
|
|
{ "PM_RX_CFG", 0x8fc0, 0 },
|
|
{ "ch1_output", 27, 5 },
|
|
{ "strobe1", 16, 1 },
|
|
{ "ch1_input", 11, 5 },
|
|
{ "ch2_input", 6, 5 },
|
|
{ "ch3_input", 1, 5 },
|
|
{ "strobe0", 0, 1 },
|
|
{ "PM_RX_MODE", 0x8fc4, 0 },
|
|
{ "use_bundle_len", 4, 1 },
|
|
{ "stat_to_ch", 3, 1 },
|
|
{ "stat_from_ch", 1, 2 },
|
|
{ "prefetch_enable", 0, 1 },
|
|
{ "PM_RX_STAT_CONFIG", 0x8fc8, 0 },
|
|
{ "PM_RX_STAT_COUNT", 0x8fcc, 0 },
|
|
{ "PM_RX_DBG_CTRL", 0x8fd0, 0 },
|
|
{ "OspiWrBusy", 21, 2 },
|
|
{ "IspiWrBusy", 17, 4 },
|
|
{ "PMDbgAddr", 0, 17 },
|
|
{ "PM_RX_DBG_DATA", 0x8fd4, 0 },
|
|
{ "PM_RX_INT_ENABLE", 0x8fd8, 0 },
|
|
{ "ospi_overflow1", 28, 1 },
|
|
{ "ospi_overflow0", 27, 1 },
|
|
{ "ma_intf_sdc_err", 26, 1 },
|
|
{ "bundle_len_ParErr", 25, 1 },
|
|
{ "bundle_len_ovfl", 24, 1 },
|
|
{ "sdc_err", 23, 1 },
|
|
{ "zero_e_cmd_error", 22, 1 },
|
|
{ "iespi0_fifo2x_Rx_framing_error", 21, 1 },
|
|
{ "iespi1_fifo2x_Rx_framing_error", 20, 1 },
|
|
{ "iespi2_fifo2x_Rx_framing_error", 19, 1 },
|
|
{ "iespi3_fifo2x_Rx_framing_error", 18, 1 },
|
|
{ "iespi0_Rx_framing_error", 17, 1 },
|
|
{ "iespi1_Rx_framing_error", 16, 1 },
|
|
{ "iespi2_Rx_framing_error", 15, 1 },
|
|
{ "iespi3_Rx_framing_error", 14, 1 },
|
|
{ "iespi0_Tx_framing_error", 13, 1 },
|
|
{ "iespi1_Tx_framing_error", 12, 1 },
|
|
{ "iespi2_Tx_framing_error", 11, 1 },
|
|
{ "iespi3_Tx_framing_error", 10, 1 },
|
|
{ "ocspi0_Rx_framing_error", 9, 1 },
|
|
{ "ocspi1_Rx_framing_error", 8, 1 },
|
|
{ "ocspi0_Tx_framing_error", 7, 1 },
|
|
{ "ocspi1_Tx_framing_error", 6, 1 },
|
|
{ "ocspi0_ofifo2x_Tx_framing_error", 5, 1 },
|
|
{ "ocspi1_ofifo2x_Tx_framing_error", 4, 1 },
|
|
{ "ocspi_par_error", 3, 1 },
|
|
{ "db_options_par_error", 2, 1 },
|
|
{ "iespi_par_error", 1, 1 },
|
|
{ "e_pcmd_par_error", 0, 1 },
|
|
{ "PM_RX_INT_CAUSE", 0x8fdc, 0 },
|
|
{ "ospi_overflow1", 28, 1 },
|
|
{ "ospi_overflow0", 27, 1 },
|
|
{ "ma_intf_sdc_err", 26, 1 },
|
|
{ "bundle_len_ParErr", 25, 1 },
|
|
{ "bundle_len_ovfl", 24, 1 },
|
|
{ "sdc_err", 23, 1 },
|
|
{ "zero_e_cmd_error", 22, 1 },
|
|
{ "iespi0_fifo2x_Rx_framing_error", 21, 1 },
|
|
{ "iespi1_fifo2x_Rx_framing_error", 20, 1 },
|
|
{ "iespi2_fifo2x_Rx_framing_error", 19, 1 },
|
|
{ "iespi3_fifo2x_Rx_framing_error", 18, 1 },
|
|
{ "iespi0_Rx_framing_error", 17, 1 },
|
|
{ "iespi1_Rx_framing_error", 16, 1 },
|
|
{ "iespi2_Rx_framing_error", 15, 1 },
|
|
{ "iespi3_Rx_framing_error", 14, 1 },
|
|
{ "iespi0_Tx_framing_error", 13, 1 },
|
|
{ "iespi1_Tx_framing_error", 12, 1 },
|
|
{ "iespi2_Tx_framing_error", 11, 1 },
|
|
{ "iespi3_Tx_framing_error", 10, 1 },
|
|
{ "ocspi0_Rx_framing_error", 9, 1 },
|
|
{ "ocspi1_Rx_framing_error", 8, 1 },
|
|
{ "ocspi0_Tx_framing_error", 7, 1 },
|
|
{ "ocspi1_Tx_framing_error", 6, 1 },
|
|
{ "ocspi0_ofifo2x_Tx_framing_error", 5, 1 },
|
|
{ "ocspi1_ofifo2x_Tx_framing_error", 4, 1 },
|
|
{ "ocspi_par_error", 3, 1 },
|
|
{ "db_options_par_error", 2, 1 },
|
|
{ "iespi_par_error", 1, 1 },
|
|
{ "e_pcmd_par_error", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_pm_tx_regs[] = {
|
|
{ "PM_TX_CFG", 0x8fe0, 0 },
|
|
{ "ch1_output", 27, 5 },
|
|
{ "ch2_output", 22, 5 },
|
|
{ "ch3_output", 17, 5 },
|
|
{ "strobe1", 16, 1 },
|
|
{ "ch1_input", 11, 5 },
|
|
{ "ch2_input", 6, 5 },
|
|
{ "ch3_input", 1, 5 },
|
|
{ "strobe0", 0, 1 },
|
|
{ "PM_TX_MODE", 0x8fe4, 0 },
|
|
{ "cong_thresh3", 25, 7 },
|
|
{ "cong_thresh2", 18, 7 },
|
|
{ "cong_thresh1", 11, 7 },
|
|
{ "cong_thresh0", 4, 7 },
|
|
{ "use_bundle_len", 3, 1 },
|
|
{ "stat_channel", 1, 2 },
|
|
{ "prefetch_enable", 0, 1 },
|
|
{ "PM_TX_STAT_CONFIG", 0x8fe8, 0 },
|
|
{ "PM_TX_STAT_COUNT", 0x8fec, 0 },
|
|
{ "PM_TX_DBG_CTRL", 0x8ff0, 0 },
|
|
{ "OspiWrBusy", 21, 4 },
|
|
{ "IspiWrBusy", 17, 4 },
|
|
{ "PMDbgAddr", 0, 17 },
|
|
{ "PM_TX_DBG_DATA", 0x8ff4, 0 },
|
|
{ "PM_TX_INT_ENABLE", 0x8ff8, 0 },
|
|
{ "pcmd_len_ovfl0", 31, 1 },
|
|
{ "pcmd_len_ovfl1", 30, 1 },
|
|
{ "pcmd_len_ovfl2", 29, 1 },
|
|
{ "zero_c_cmd_error", 28, 1 },
|
|
{ "icspi0_fifo2x_Rx_framing_error", 27, 1 },
|
|
{ "icspi1_fifo2x_Rx_framing_error", 26, 1 },
|
|
{ "icspi2_fifo2x_Rx_framing_error", 25, 1 },
|
|
{ "icspi3_fifo2x_Rx_framing_error", 24, 1 },
|
|
{ "icspi0_Rx_framing_error", 23, 1 },
|
|
{ "icspi1_Rx_framing_error", 22, 1 },
|
|
{ "icspi2_Rx_framing_error", 21, 1 },
|
|
{ "icspi3_Rx_framing_error", 20, 1 },
|
|
{ "icspi0_Tx_framing_error", 19, 1 },
|
|
{ "icspi1_Tx_framing_error", 18, 1 },
|
|
{ "icspi2_Tx_framing_error", 17, 1 },
|
|
{ "icspi3_Tx_framing_error", 16, 1 },
|
|
{ "oespi0_Rx_framing_error", 15, 1 },
|
|
{ "oespi1_Rx_framing_error", 14, 1 },
|
|
{ "oespi2_Rx_framing_error", 13, 1 },
|
|
{ "oespi3_Rx_framing_error", 12, 1 },
|
|
{ "oespi0_Tx_framing_error", 11, 1 },
|
|
{ "oespi1_Tx_framing_error", 10, 1 },
|
|
{ "oespi2_Tx_framing_error", 9, 1 },
|
|
{ "oespi3_Tx_framing_error", 8, 1 },
|
|
{ "oespi0_ofifo2x_Tx_framing_error", 7, 1 },
|
|
{ "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
|
|
{ "oespi2_ofifo2x_Tx_framing_error", 5, 1 },
|
|
{ "oespi3_ofifo2x_Tx_framing_error", 4, 1 },
|
|
{ "oespi_par_error", 3, 1 },
|
|
{ "db_options_par_error", 2, 1 },
|
|
{ "icspi_par_error", 1, 1 },
|
|
{ "c_pcmd_par_error", 0, 1 },
|
|
{ "PM_TX_INT_CAUSE", 0x8ffc, 0 },
|
|
{ "pcmd_len_ovfl0", 31, 1 },
|
|
{ "pcmd_len_ovfl1", 30, 1 },
|
|
{ "pcmd_len_ovfl2", 29, 1 },
|
|
{ "zero_c_cmd_error", 28, 1 },
|
|
{ "icspi0_fifo2x_Rx_framing_error", 27, 1 },
|
|
{ "icspi1_fifo2x_Rx_framing_error", 26, 1 },
|
|
{ "icspi2_fifo2x_Rx_framing_error", 25, 1 },
|
|
{ "icspi3_fifo2x_Rx_framing_error", 24, 1 },
|
|
{ "icspi0_Rx_framing_error", 23, 1 },
|
|
{ "icspi1_Rx_framing_error", 22, 1 },
|
|
{ "icspi2_Rx_framing_error", 21, 1 },
|
|
{ "icspi3_Rx_framing_error", 20, 1 },
|
|
{ "icspi0_Tx_framing_error", 19, 1 },
|
|
{ "icspi1_Tx_framing_error", 18, 1 },
|
|
{ "icspi2_Tx_framing_error", 17, 1 },
|
|
{ "icspi3_Tx_framing_error", 16, 1 },
|
|
{ "oespi0_Rx_framing_error", 15, 1 },
|
|
{ "oespi1_Rx_framing_error", 14, 1 },
|
|
{ "oespi2_Rx_framing_error", 13, 1 },
|
|
{ "oespi3_Rx_framing_error", 12, 1 },
|
|
{ "oespi0_Tx_framing_error", 11, 1 },
|
|
{ "oespi1_Tx_framing_error", 10, 1 },
|
|
{ "oespi2_Tx_framing_error", 9, 1 },
|
|
{ "oespi3_Tx_framing_error", 8, 1 },
|
|
{ "oespi0_ofifo2x_Tx_framing_error", 7, 1 },
|
|
{ "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
|
|
{ "oespi2_ofifo2x_Tx_framing_error", 5, 1 },
|
|
{ "oespi3_ofifo2x_Tx_framing_error", 4, 1 },
|
|
{ "ospi_or_bundle_len_par_err", 3, 1 },
|
|
{ "db_options_par_error", 2, 1 },
|
|
{ "icspi_par_error", 1, 1 },
|
|
{ "c_pcmd_par_error", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_mps_regs[] = {
|
|
{ "MPS_CMN_CTL", 0x9000, 0 },
|
|
{ "TX_PORT_STATS_MODE", 8, 1 },
|
|
{ "T5Mode", 7, 1 },
|
|
{ "SpeedMode", 5, 2 },
|
|
{ "LpbkCrdtCtrl", 4, 1 },
|
|
{ "Detect8023", 3, 1 },
|
|
{ "VFDirectAccess", 2, 1 },
|
|
{ "NumPorts", 0, 2 },
|
|
{ "MPS_INT_ENABLE", 0x9004, 0 },
|
|
{ "StatIntEnb", 5, 1 },
|
|
{ "TxIntEnb", 4, 1 },
|
|
{ "RxIntEnb", 3, 1 },
|
|
{ "TrcIntEnb", 2, 1 },
|
|
{ "ClsIntEnb", 1, 1 },
|
|
{ "PLIntEnb", 0, 1 },
|
|
{ "MPS_INT_CAUSE", 0x9008, 0 },
|
|
{ "StatInt", 5, 1 },
|
|
{ "TxInt", 4, 1 },
|
|
{ "RxInt", 3, 1 },
|
|
{ "TrcInt", 2, 1 },
|
|
{ "ClsInt", 1, 1 },
|
|
{ "PLInt", 0, 1 },
|
|
{ "MPS_CGEN_GLOBAL", 0x900c, 0 },
|
|
{ "MPS_VF_TX_CTL_31_0", 0x9010, 0 },
|
|
{ "MPS_VF_TX_CTL_63_32", 0x9014, 0 },
|
|
{ "MPS_VF_TX_CTL_95_64", 0x9018, 0 },
|
|
{ "MPS_VF_TX_CTL_127_96", 0x901c, 0 },
|
|
{ "MPS_VF_TX_CTL_159_128", 0x9100, 0 },
|
|
{ "MPS_VF_TX_CTL_191_160", 0x9104, 0 },
|
|
{ "MPS_VF_TX_CTL_223_192", 0x9108, 0 },
|
|
{ "MPS_VF_TX_CTL_255_224", 0x910c, 0 },
|
|
{ "MPS_VF_RX_CTL_31_0", 0x9020, 0 },
|
|
{ "MPS_VF_RX_CTL_63_32", 0x9024, 0 },
|
|
{ "MPS_VF_RX_CTL_95_64", 0x9028, 0 },
|
|
{ "MPS_VF_RX_CTL_127_96", 0x902c, 0 },
|
|
{ "MPS_VF_RX_CTL_159_128", 0x9110, 0 },
|
|
{ "MPS_VF_RX_CTL_191_160", 0x9114, 0 },
|
|
{ "MPS_VF_RX_CTL_223_192", 0x9118, 0 },
|
|
{ "MPS_VF_RX_CTL_255_224", 0x911c, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP0", 0x9030, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP1", 0x9034, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP2", 0x9038, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP3", 0x903c, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP0", 0x9040, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP1", 0x9044, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP2", 0x9048, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP3", 0x904c, 0 },
|
|
{ "MPS_TP_CSIDE_MUX_CTL_P0", 0x9050, 0 },
|
|
{ "MPS_TP_CSIDE_MUX_CTL_P1", 0x9054, 0 },
|
|
{ "MPS_WOL_CTL_MODE", 0x9058, 0 },
|
|
{ "MPS_FPGA_DEBUG", 0x9060, 0 },
|
|
{ "FPGA_PTP_PORT", 9, 2 },
|
|
{ "LPBK_EN", 8, 1 },
|
|
{ "CH_MAP1", 2, 2 },
|
|
{ "CH_MAP0", 0, 2 },
|
|
{ "MPS_DEBUG_CTL", 0x9068, 0 },
|
|
{ "DbgModeCtl_H", 11, 1 },
|
|
{ "DbgSel_H", 6, 5 },
|
|
{ "DbgModeCtl_L", 5, 1 },
|
|
{ "DbgSel_L", 0, 5 },
|
|
{ "MPS_DEBUG_DATA_REG_L", 0x906c, 0 },
|
|
{ "MPS_DEBUG_DATA_REG_H", 0x9070, 0 },
|
|
{ "MPS_TOP_SPARE", 0x9074, 0 },
|
|
{ "TopSpare", 8, 24 },
|
|
{ "oVlanSelLpbk3", 7, 1 },
|
|
{ "oVlanSelLpbk2", 6, 1 },
|
|
{ "oVlanSelLpbk1", 5, 1 },
|
|
{ "oVlanSelLpbk0", 4, 1 },
|
|
{ "oVlanSelMac3", 3, 1 },
|
|
{ "oVlanSelMac2", 2, 1 },
|
|
{ "oVlanSelMac1", 1, 1 },
|
|
{ "oVlanSelMac0", 0, 1 },
|
|
{ "MPS_BUILD_REVISION", 0x9078, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH0", 0x907c, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH1", 0x9080, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH2", 0x9084, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH3", 0x9088, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH4", 0x908c, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH5", 0x9090, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH6", 0x9094, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH7", 0x9098, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH8", 0x909c, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH9", 0x90a0, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH10", 0x90a4, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH11", 0x90a8, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH12", 0x90ac, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH13", 0x90b0, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH14", 0x90b4, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH15", 0x90b8, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0", 0x90bc, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1", 0x90c0, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2", 0x90c4, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3", 0x90c8, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4", 0x90cc, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5", 0x90d0, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6", 0x90d4, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7", 0x90d8, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8", 0x90dc, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9", 0x90e0, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10", 0x90e4, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11", 0x90e8, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12", 0x90ec, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13", 0x90f0, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14", 0x90f4, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15", 0x90f8, 0 },
|
|
{ "MPS_FPGA_BIST_CFG_P0", 0x9120, 0 },
|
|
{ "AddrMask", 16, 16 },
|
|
{ "BaseAddr", 0, 16 },
|
|
{ "MPS_FPGA_BIST_CFG_P1", 0x9124, 0 },
|
|
{ "AddrMask", 16, 16 },
|
|
{ "BaseAddr", 0, 16 },
|
|
{ "MPS_PORT_CTL", 0x30000, 0 },
|
|
{ "LpbkEn", 31, 1 },
|
|
{ "TxEn", 30, 1 },
|
|
{ "RxEn", 29, 1 },
|
|
{ "PPPEn", 28, 1 },
|
|
{ "FCSStripEn", 27, 1 },
|
|
{ "PPPAndPause", 26, 1 },
|
|
{ "PrioPPPEnMap", 16, 8 },
|
|
{ "MPS_PORT_PAUSE_CTL", 0x30004, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL", 0x30008, 0 },
|
|
{ "RegSendOff", 24, 8 },
|
|
{ "RegSendOn", 16, 8 },
|
|
{ "SgeSendEn", 8, 8 },
|
|
{ "RxSendEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL2", 0x3000c, 0 },
|
|
{ "MPS_PORT_RX_PAUSE_CTL", 0x30010, 0 },
|
|
{ "RegHaltOn", 8, 8 },
|
|
{ "RxHaltEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_STATUS", 0x30014, 0 },
|
|
{ "RegSending", 16, 8 },
|
|
{ "SgeSending", 8, 8 },
|
|
{ "RxSending", 0, 8 },
|
|
{ "MPS_PORT_RX_PAUSE_STATUS", 0x30018, 0 },
|
|
{ "RegHalted", 8, 8 },
|
|
{ "RxHalted", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_L", 0x3001c, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_H", 0x30020, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x30024, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x30028, 0 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3002c, 0 },
|
|
{ "Prty7", 14, 2 },
|
|
{ "Prty6", 12, 2 },
|
|
{ "Prty5", 10, 2 },
|
|
{ "Prty4", 8, 2 },
|
|
{ "Prty3", 6, 2 },
|
|
{ "Prty2", 4, 2 },
|
|
{ "Prty1", 2, 2 },
|
|
{ "Prty0", 0, 2 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x30030, 0 },
|
|
{ "Prty7", 28, 4 },
|
|
{ "Prty6", 24, 4 },
|
|
{ "Prty5", 20, 4 },
|
|
{ "Prty4", 16, 4 },
|
|
{ "Prty3", 12, 4 },
|
|
{ "Prty2", 8, 4 },
|
|
{ "Prty1", 4, 4 },
|
|
{ "Prty0", 0, 4 },
|
|
{ "MPS_PORT_CTL", 0x34000, 0 },
|
|
{ "LpbkEn", 31, 1 },
|
|
{ "TxEn", 30, 1 },
|
|
{ "RxEn", 29, 1 },
|
|
{ "PPPEn", 28, 1 },
|
|
{ "FCSStripEn", 27, 1 },
|
|
{ "PPPAndPause", 26, 1 },
|
|
{ "PrioPPPEnMap", 16, 8 },
|
|
{ "MPS_PORT_PAUSE_CTL", 0x34004, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL", 0x34008, 0 },
|
|
{ "RegSendOff", 24, 8 },
|
|
{ "RegSendOn", 16, 8 },
|
|
{ "SgeSendEn", 8, 8 },
|
|
{ "RxSendEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL2", 0x3400c, 0 },
|
|
{ "MPS_PORT_RX_PAUSE_CTL", 0x34010, 0 },
|
|
{ "RegHaltOn", 8, 8 },
|
|
{ "RxHaltEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_STATUS", 0x34014, 0 },
|
|
{ "RegSending", 16, 8 },
|
|
{ "SgeSending", 8, 8 },
|
|
{ "RxSending", 0, 8 },
|
|
{ "MPS_PORT_RX_PAUSE_STATUS", 0x34018, 0 },
|
|
{ "RegHalted", 8, 8 },
|
|
{ "RxHalted", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_L", 0x3401c, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_H", 0x34020, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x34024, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x34028, 0 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3402c, 0 },
|
|
{ "Prty7", 14, 2 },
|
|
{ "Prty6", 12, 2 },
|
|
{ "Prty5", 10, 2 },
|
|
{ "Prty4", 8, 2 },
|
|
{ "Prty3", 6, 2 },
|
|
{ "Prty2", 4, 2 },
|
|
{ "Prty1", 2, 2 },
|
|
{ "Prty0", 0, 2 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x34030, 0 },
|
|
{ "Prty7", 28, 4 },
|
|
{ "Prty6", 24, 4 },
|
|
{ "Prty5", 20, 4 },
|
|
{ "Prty4", 16, 4 },
|
|
{ "Prty3", 12, 4 },
|
|
{ "Prty2", 8, 4 },
|
|
{ "Prty1", 4, 4 },
|
|
{ "Prty0", 0, 4 },
|
|
{ "MPS_PF_CTL", 0x1e2c0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1e6c0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1eac0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1eec0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1f2c0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1f6c0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1fac0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1fec0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_RX_CTL", 0x11000, 0 },
|
|
{ "FILT_VLAN_SEL", 17, 1 },
|
|
{ "CBA_EN", 16, 1 },
|
|
{ "BLK_SNDR", 12, 4 },
|
|
{ "CMPRS", 8, 4 },
|
|
{ "SNF", 0, 8 },
|
|
{ "MPS_RX_PORT_MUX_CTL", 0x11004, 0 },
|
|
{ "CTL_P1", 4, 4 },
|
|
{ "CTL_P0", 0, 4 },
|
|
{ "MPS_RX_FIFO_0_CTL", 0x11008, 0 },
|
|
{ "MPS_RX_FIFO_1_CTL", 0x1100c, 0 },
|
|
{ "MPS_RX_FIFO_2_CTL", 0x11010, 0 },
|
|
{ "MPS_RX_FIFO_3_CTL", 0x11014, 0 },
|
|
{ "MPS_RX_PG_HYST_BG0", 0x11048, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "TH", 0, 11 },
|
|
{ "MPS_RX_PG_HYST_BG1", 0x1104c, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "TH", 0, 11 },
|
|
{ "MPS_RX_PG_HYST_BG2", 0x11050, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "TH", 0, 11 },
|
|
{ "MPS_RX_PG_HYST_BG3", 0x11054, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "TH", 0, 11 },
|
|
{ "MPS_RX_OCH_CTL", 0x11058, 0 },
|
|
{ "DROP_WT", 27, 5 },
|
|
{ "TRUNC_WT", 22, 5 },
|
|
{ "DRAIN", 13, 5 },
|
|
{ "DROP", 8, 5 },
|
|
{ "STOP", 0, 5 },
|
|
{ "MPS_RX_LPBK_BP0", 0x1105c, 0 },
|
|
{ "MPS_RX_LPBK_BP1", 0x11060, 0 },
|
|
{ "MPS_RX_LPBK_BP2", 0x11064, 0 },
|
|
{ "MPS_RX_LPBK_BP3", 0x11068, 0 },
|
|
{ "MPS_RX_PORT_GAP", 0x1106c, 0 },
|
|
{ "MPS_RX_PERR_INT_CAUSE", 0x11074, 0 },
|
|
{ "INT_ERR_INT", 24, 1 },
|
|
{ "FF", 23, 1 },
|
|
{ "RPLC", 19, 1 },
|
|
{ "ATRB", 18, 1 },
|
|
{ "PPM1", 10, 1 },
|
|
{ "PPM0", 9, 1 },
|
|
{ "MPS_RX_PERR_INT_ENABLE", 0x11078, 0 },
|
|
{ "INT_ERR_INT", 24, 1 },
|
|
{ "FF", 23, 1 },
|
|
{ "RPLC", 19, 1 },
|
|
{ "ATRB", 18, 1 },
|
|
{ "PPM1", 10, 1 },
|
|
{ "PPM0", 9, 1 },
|
|
{ "MPS_RX_PERR_ENABLE", 0x1107c, 0 },
|
|
{ "INT_ERR_INT", 24, 1 },
|
|
{ "FF", 23, 1 },
|
|
{ "RPLC", 19, 1 },
|
|
{ "ATRB", 18, 1 },
|
|
{ "PPM1", 10, 1 },
|
|
{ "PPM0", 9, 1 },
|
|
{ "MPS_RX_PERR_INJECT", 0x11080, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_RX_FUNC_INT_CAUSE", 0x11084, 0 },
|
|
{ "MTU_ERR_INT3", 19, 1 },
|
|
{ "MTU_ERR_INT2", 18, 1 },
|
|
{ "MTU_ERR_INT1", 17, 1 },
|
|
{ "MTU_ERR_INT0", 16, 1 },
|
|
{ "SE_CNT_ERR_INT", 15, 1 },
|
|
{ "FRM_ERR_INT", 14, 1 },
|
|
{ "LEN_ERR_INT", 13, 1 },
|
|
{ "INT_ERR_INT", 8, 5 },
|
|
{ "PG_TH_INT7", 7, 1 },
|
|
{ "PG_TH_INT6", 6, 1 },
|
|
{ "PG_TH_INT5", 5, 1 },
|
|
{ "PG_TH_INT4", 4, 1 },
|
|
{ "PG_TH_INT3", 3, 1 },
|
|
{ "PG_TH_INT2", 2, 1 },
|
|
{ "PG_TH_INT1", 1, 1 },
|
|
{ "PG_TH_INT0", 0, 1 },
|
|
{ "MPS_RX_FUNC_INT_ENABLE", 0x11088, 0 },
|
|
{ "MTU_ERR_INT3", 19, 1 },
|
|
{ "MTU_ERR_INT2", 18, 1 },
|
|
{ "MTU_ERR_INT1", 17, 1 },
|
|
{ "MTU_ERR_INT0", 16, 1 },
|
|
{ "SE_CNT_ERR_INT", 15, 1 },
|
|
{ "FRM_ERR_INT", 14, 1 },
|
|
{ "LEN_ERR_INT", 13, 1 },
|
|
{ "INT_ERR_INT", 8, 5 },
|
|
{ "PG_TH_INT7", 7, 1 },
|
|
{ "PG_TH_INT6", 6, 1 },
|
|
{ "PG_TH_INT5", 5, 1 },
|
|
{ "PG_TH_INT4", 4, 1 },
|
|
{ "PG_TH_INT3", 3, 1 },
|
|
{ "PG_TH_INT2", 2, 1 },
|
|
{ "PG_TH_INT1", 1, 1 },
|
|
{ "PG_TH_INT0", 0, 1 },
|
|
{ "MPS_RX_REPL_CTL", 0x11098, 0 },
|
|
{ "MPS_RX_PPP_ATRB", 0x1109c, 0 },
|
|
{ "ETYPE", 16, 16 },
|
|
{ "OPCODE", 0, 16 },
|
|
{ "MPS_RX_QFC0_ATRB", 0x110a0, 0 },
|
|
{ "ETYPE", 16, 16 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_RX_QFC1_ATRB", 0x110a4, 0 },
|
|
{ "MPS_RX_PT_ARB0", 0x110a8, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_RX_PT_ARB1", 0x110ac, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_RX_PT_ARB2", 0x110b0, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_PF_OUT_EN", 0x110b4, 0 },
|
|
{ "MPS_BMC_MTU", 0x110b8, 0 },
|
|
{ "MPS_BMC_PKT_CNT", 0x110bc, 0 },
|
|
{ "MPS_BMC_BYTE_CNT", 0x110c0, 0 },
|
|
{ "MPS_PFVF_ATRB_CTL", 0x110c4, 0 },
|
|
{ "RD_WRN", 31, 1 },
|
|
{ "PFVF", 0, 9 },
|
|
{ "MPS_PFVF_ATRB", 0x110c8, 0 },
|
|
{ "PF", 28, 3 },
|
|
{ "OFF", 18, 1 },
|
|
{ "NV_DROP", 17, 1 },
|
|
{ "MODE", 16, 1 },
|
|
{ "FULL_FRAME_MODE", 14, 1 },
|
|
{ "MTU", 0, 14 },
|
|
{ "MPS_PFVF_ATRB_FLTR0", 0x110cc, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR1", 0x110d0, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR2", 0x110d4, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR3", 0x110d8, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR4", 0x110dc, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR5", 0x110e0, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR6", 0x110e4, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR7", 0x110e8, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR8", 0x110ec, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR9", 0x110f0, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR10", 0x110f4, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR11", 0x110f8, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR12", 0x110fc, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR13", 0x11100, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR14", 0x11104, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR15", 0x11108, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_RPLC_MAP_CTL", 0x1110c, 0 },
|
|
{ "RD_WRN", 31, 1 },
|
|
{ "ADDR", 0, 10 },
|
|
{ "MPS_PF_RPLCT_MAP", 0x11110, 0 },
|
|
{ "MPS_VF_RPLCT_MAP0", 0x11114, 0 },
|
|
{ "MPS_VF_RPLCT_MAP1", 0x11118, 0 },
|
|
{ "MPS_VF_RPLCT_MAP2", 0x1111c, 0 },
|
|
{ "MPS_VF_RPLCT_MAP3", 0x11120, 0 },
|
|
{ "MPS_VF_RPLCT_MAP4", 0x11300, 0 },
|
|
{ "MPS_VF_RPLCT_MAP5", 0x11304, 0 },
|
|
{ "MPS_VF_RPLCT_MAP6", 0x11308, 0 },
|
|
{ "MPS_VF_RPLCT_MAP7", 0x1130c, 0 },
|
|
{ "MPS_MEM_DBG_CTL", 0x1112c, 0 },
|
|
{ "PKD", 17, 1 },
|
|
{ "PGD", 16, 1 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MPS_PKD_MEM_DATA0", 0x11130, 0 },
|
|
{ "MPS_PKD_MEM_DATA1", 0x11134, 0 },
|
|
{ "MPS_PKD_MEM_DATA2", 0x11138, 0 },
|
|
{ "MPS_PGD_MEM_DATA", 0x1113c, 0 },
|
|
{ "MPS_RX_SE_CNT_ERR", 0x11140, 0 },
|
|
{ "MPS_RX_SE_CNT_CLR", 0x11144, 0 },
|
|
{ "MPS_RX_SE_CNT_IN0", 0x11148, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN1", 0x1114c, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN2", 0x11150, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN3", 0x11154, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN4", 0x11158, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN5", 0x1115c, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN6", 0x11160, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN7", 0x11164, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_OUT01", 0x11168, 0 },
|
|
{ "SOP_CNT_1", 24, 8 },
|
|
{ "EOP_CNT_1", 16, 8 },
|
|
{ "SOP_CNT_0", 8, 8 },
|
|
{ "EOP_CNT_0", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_OUT23", 0x1116c, 0 },
|
|
{ "SOP_CNT_3", 24, 8 },
|
|
{ "EOP_CNT_3", 16, 8 },
|
|
{ "SOP_CNT_2", 8, 8 },
|
|
{ "EOP_CNT_2", 0, 8 },
|
|
{ "MPS_RX_SPI_ERR", 0x11170, 0 },
|
|
{ "LEN_ERR", 21, 4 },
|
|
{ "ERR", 0, 21 },
|
|
{ "MPS_RX_IN_BUS_STATE", 0x11174, 0 },
|
|
{ "ST3", 24, 8 },
|
|
{ "ST2", 16, 8 },
|
|
{ "ST1", 8, 8 },
|
|
{ "ST0", 0, 8 },
|
|
{ "MPS_RX_OUT_BUS_STATE", 0x11178, 0 },
|
|
{ "ST_NCSI", 23, 9 },
|
|
{ "ST_TP", 0, 23 },
|
|
{ "MPS_RX_DBG_CTL", 0x1117c, 0 },
|
|
{ "OUT_DBG_CHNL", 8, 3 },
|
|
{ "DBG_PKD_QSEL", 7, 1 },
|
|
{ "DBG_CDS_INV", 6, 1 },
|
|
{ "IN_DBG_PORT", 3, 3 },
|
|
{ "IN_DBG_CHNL", 0, 3 },
|
|
{ "MPS_RX_SPARE", 0x11190, 0 },
|
|
{ "MPS_RX_PTP_ETYPE", 0x11194, 0 },
|
|
{ "PETYPE2", 16, 16 },
|
|
{ "PETYPE1", 0, 16 },
|
|
{ "MPS_RX_PTP_TCP", 0x11198, 0 },
|
|
{ "PTCPORT2", 16, 16 },
|
|
{ "PTCPORT1", 0, 16 },
|
|
{ "MPS_RX_PTP_UDP", 0x1119c, 0 },
|
|
{ "PUDPORT2", 16, 16 },
|
|
{ "PUDPORT1", 0, 16 },
|
|
{ "MPS_RX_PTP_CTL", 0x111a0, 0 },
|
|
{ "MIN_PTP_SPACE", 24, 7 },
|
|
{ "PUDP2EN", 20, 4 },
|
|
{ "PUDP1EN", 16, 4 },
|
|
{ "PTCP2EN", 12, 4 },
|
|
{ "PTCP1EN", 8, 4 },
|
|
{ "PETYPE2EN", 4, 4 },
|
|
{ "PETYPE1EN", 0, 4 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_0_0", 0x111a4, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_0_1", 0x111a8, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_0_2", 0x111ac, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_0_3", 0x111b0, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_1_0", 0x111b4, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_1_1", 0x111b8, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_1_2", 0x111bc, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_1_3", 0x111c0, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_2_0", 0x111c4, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_2_1", 0x111c8, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_2_2", 0x111cc, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_2_3", 0x111d0, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_3_0", 0x111d4, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_3_1", 0x111d8, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_3_2", 0x111dc, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_3_3", 0x111e0, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_MAC_CLS_DROP_CNT0", 0x111e4, 0 },
|
|
{ "MPS_RX_MAC_CLS_DROP_CNT1", 0x111e8, 0 },
|
|
{ "MPS_RX_MAC_CLS_DROP_CNT2", 0x111ec, 0 },
|
|
{ "MPS_RX_MAC_CLS_DROP_CNT3", 0x111f0, 0 },
|
|
{ "MPS_RX_LPBK_CLS_DROP_CNT0", 0x111f4, 0 },
|
|
{ "MPS_RX_LPBK_CLS_DROP_CNT1", 0x111f8, 0 },
|
|
{ "MPS_RX_LPBK_CLS_DROP_CNT2", 0x111fc, 0 },
|
|
{ "MPS_RX_LPBK_CLS_DROP_CNT3", 0x11200, 0 },
|
|
{ "MPS_RX_CGEN", 0x11204, 0 },
|
|
{ "MPS_RX_CGEN_NCSI", 12, 1 },
|
|
{ "MPS_RX_CGEN_OUT", 8, 4 },
|
|
{ "MPS_RX_CGEN_LPBK_IN", 4, 4 },
|
|
{ "MPS_RX_CGEN_MAC_IN", 0, 4 },
|
|
{ "MPS_RX_MAC_BG_PG_CNT0", 0x11208, 0 },
|
|
{ "MAC_USED", 16, 11 },
|
|
{ "MAC_ALLOC", 0, 11 },
|
|
{ "MPS_RX_MAC_BG_PG_CNT1", 0x1120c, 0 },
|
|
{ "MAC_USED", 16, 11 },
|
|
{ "MAC_ALLOC", 0, 11 },
|
|
{ "MPS_RX_MAC_BG_PG_CNT2", 0x11210, 0 },
|
|
{ "MAC_USED", 16, 11 },
|
|
{ "MAC_ALLOC", 0, 11 },
|
|
{ "MPS_RX_MAC_BG_PG_CNT3", 0x11214, 0 },
|
|
{ "MAC_USED", 16, 11 },
|
|
{ "MAC_ALLOC", 0, 11 },
|
|
{ "MPS_RX_LPBK_BG_PG_CNT0", 0x11218, 0 },
|
|
{ "LPBK_USED", 16, 11 },
|
|
{ "LPBK_ALLOC", 0, 11 },
|
|
{ "MPS_RX_LPBK_BG_PG_CNT1", 0x1121c, 0 },
|
|
{ "LPBK_USED", 16, 11 },
|
|
{ "LPBK_ALLOC", 0, 11 },
|
|
{ "MPS_RX_CONGESTION_THRESHOLD_BG0", 0x11220, 0 },
|
|
{ "CONG_EN", 31, 1 },
|
|
{ "CONG_TH", 0, 20 },
|
|
{ "MPS_RX_CONGESTION_THRESHOLD_BG1", 0x11224, 0 },
|
|
{ "CONG_EN", 31, 1 },
|
|
{ "CONG_TH", 0, 20 },
|
|
{ "MPS_RX_CONGESTION_THRESHOLD_BG2", 0x11228, 0 },
|
|
{ "CONG_EN", 31, 1 },
|
|
{ "CONG_TH", 0, 20 },
|
|
{ "MPS_RX_CONGESTION_THRESHOLD_BG3", 0x1122c, 0 },
|
|
{ "CONG_EN", 31, 1 },
|
|
{ "CONG_TH", 0, 20 },
|
|
{ "MPS_RX_GRE_PROT_TYPE", 0x11230, 0 },
|
|
{ "NVGRE_EN", 9, 1 },
|
|
{ "GRE_EN", 8, 1 },
|
|
{ "GRE", 0, 8 },
|
|
{ "MPS_RX_VXLAN_TYPE", 0x11234, 0 },
|
|
{ "VXLAN_EN", 16, 1 },
|
|
{ "VXLAN", 0, 16 },
|
|
{ "MPS_RX_GENEVE_TYPE", 0x11238, 0 },
|
|
{ "GENEVE_EN", 16, 1 },
|
|
{ "GENEVE", 0, 16 },
|
|
{ "MPS_RX_INNER_HDR_IVLAN", 0x1123c, 0 },
|
|
{ "IVLAN_EN", 16, 1 },
|
|
{ "IVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_RX_ENCAP_NVGRE", 0x11240, 0 },
|
|
{ "ETYPE_EN", 16, 1 },
|
|
{ "ETYPE", 0, 16 },
|
|
{ "MPS_RX_ENCAP_GENEVE", 0x11244, 0 },
|
|
{ "ETYPE_EN", 16, 1 },
|
|
{ "ETYPE", 0, 16 },
|
|
{ "MPS_RX_TCP", 0x11248, 0 },
|
|
{ "PROT_TYPE_EN", 8, 1 },
|
|
{ "PROT_TYPE", 0, 8 },
|
|
{ "MPS_RX_UDP", 0x1124c, 0 },
|
|
{ "PROT_TYPE_EN", 8, 1 },
|
|
{ "PROT_TYPE", 0, 8 },
|
|
{ "MPS_RX_PAUSE", 0x11250, 0 },
|
|
{ "MPS_RX_LENGTH", 0x11254, 0 },
|
|
{ "SAP_VALUE", 16, 16 },
|
|
{ "LENGTH_ETYPE", 0, 16 },
|
|
{ "MPS_RX_CTL_ORG", 0x11258, 0 },
|
|
{ "CTL_VALUE", 24, 8 },
|
|
{ "ORG_VALUE", 0, 24 },
|
|
{ "MPS_RX_IPV4", 0x1125c, 0 },
|
|
{ "MPS_RX_IPV6", 0x11260, 0 },
|
|
{ "MPS_RX_TTL", 0x11264, 0 },
|
|
{ "TTL_IPV4", 10, 8 },
|
|
{ "TTL_IPV6", 2, 8 },
|
|
{ "TTL_CHK_EN_IPV4", 1, 1 },
|
|
{ "TTL_CHK_EN_IPV6", 0, 1 },
|
|
{ "MPS_RX_DEFAULT_VNI", 0x11268, 0 },
|
|
{ "MPS_RX_PRS_CTL", 0x1126c, 0 },
|
|
{ "CTL_CHK_EN", 28, 1 },
|
|
{ "ORG_CHK_EN", 27, 1 },
|
|
{ "SAP_CHK_EN", 26, 1 },
|
|
{ "VXLAN_FLAG_CHK_EN", 25, 1 },
|
|
{ "VXLAN_FLAG_MASK", 17, 8 },
|
|
{ "VXLAN_FLAG", 9, 8 },
|
|
{ "GRE_VER_CHK_EN", 8, 1 },
|
|
{ "GRE_VER", 5, 3 },
|
|
{ "GENEVE_VER_CHK_EN", 4, 1 },
|
|
{ "GENEVE_VER", 2, 2 },
|
|
{ "DIP_EN", 1, 1 },
|
|
{ "MPS_RX_PRS_CTL_2", 0x11270, 0 },
|
|
{ "EN_UDP_CSUM_CHK", 4, 1 },
|
|
{ "EN_UDP_LEN_CHK", 3, 1 },
|
|
{ "EN_IP_CSUM_CHK", 2, 1 },
|
|
{ "EN_IP_PAYLOAD_LEN_CHK", 1, 1 },
|
|
{ "IPV6_UDP_CSUM_COMPAT", 0, 1 },
|
|
{ "MPS_RX_MPS2NCSI_CNT", 0x11274, 0 },
|
|
{ "MPS_RX_MAX_TNL_HDR_LEN", 0x11278, 0 },
|
|
{ "MPS_RX_PAUSE_DA_H", 0x1127c, 0 },
|
|
{ "MPS_RX_PAUSE_DA_L", 0x11280, 0 },
|
|
{ "MPS_RX_CNT_NVGRE_PKT_MAC0", 0x11284, 0 },
|
|
{ "MPS_RX_CNT_VXLAN_PKT_MAC0", 0x11288, 0 },
|
|
{ "MPS_RX_CNT_GENEVE_PKT_MAC0", 0x1128c, 0 },
|
|
{ "MPS_RX_CNT_TNL_ERR_PKT_MAC0", 0x11290, 0 },
|
|
{ "MPS_RX_CNT_NVGRE_PKT_MAC1", 0x11294, 0 },
|
|
{ "MPS_RX_CNT_VXLAN_PKT_MAC1", 0x11298, 0 },
|
|
{ "MPS_RX_CNT_GENEVE_PKT_MAC1", 0x1129c, 0 },
|
|
{ "MPS_RX_CNT_TNL_ERR_PKT_MAC1", 0x112a0, 0 },
|
|
{ "MPS_RX_CNT_NVGRE_PKT_LPBK0", 0x112a4, 0 },
|
|
{ "MPS_RX_CNT_VXLAN_PKT_LPBK0", 0x112a8, 0 },
|
|
{ "MPS_RX_CNT_GENEVE_PKT_LPBK0", 0x112ac, 0 },
|
|
{ "MPS_RX_CNT_TNL_ERR_PKT_LPBK0", 0x112b0, 0 },
|
|
{ "MPS_RX_CNT_NVGRE_PKT_LPBK1", 0x112b4, 0 },
|
|
{ "MPS_RX_CNT_VXLAN_PKT_LPBK1", 0x112b8, 0 },
|
|
{ "MPS_RX_CNT_GENEVE_PKT_LPBK1", 0x112bc, 0 },
|
|
{ "MPS_RX_CNT_TNL_ERR_PKT_LPBK1", 0x112c0, 0 },
|
|
{ "MPS_RX_CNT_NVGRE_PKT_TO_TP0", 0x112c4, 0 },
|
|
{ "MPS_RX_CNT_VXLAN_PKT_TO_TP0", 0x112c8, 0 },
|
|
{ "MPS_RX_CNT_GENEVE_PKT_TO_TP0", 0x112cc, 0 },
|
|
{ "MPS_RX_CNT_TNL_ERR_PKT_TO_TP0", 0x112d0, 0 },
|
|
{ "MPS_RX_CNT_NVGRE_PKT_TO_TP1", 0x112d4, 0 },
|
|
{ "MPS_RX_CNT_VXLAN_PKT_TO_TP1", 0x112d8, 0 },
|
|
{ "MPS_RX_CNT_GENEVE_PKT_TO_TP1", 0x112dc, 0 },
|
|
{ "MPS_RX_CNT_TNL_ERR_PKT_TO_TP1", 0x112e0, 0 },
|
|
{ "MPS_PORT_RX_CTL", 0x30100, 0 },
|
|
{ "HASH_PRIO_SEL_LPBK", 25, 1 },
|
|
{ "HASH_PRIO_SEL_MAC", 24, 1 },
|
|
{ "HASH_EN_LPBK", 23, 1 },
|
|
{ "HASH_EN_MAC", 22, 1 },
|
|
{ "PTP_FWD_UP", 21, 1 },
|
|
{ "NO_RPLCT_M", 20, 1 },
|
|
{ "RPLCT_SEL_L", 18, 2 },
|
|
{ "FLTR_VLAN_SEL", 17, 1 },
|
|
{ "PRIO_VLAN_SEL", 16, 1 },
|
|
{ "CHK_8023_LEN_M", 15, 1 },
|
|
{ "CHK_8023_LEN_L", 14, 1 },
|
|
{ "NIV_DROP", 13, 1 },
|
|
{ "NOV_DROP", 12, 1 },
|
|
{ "CLS_PRT", 11, 1 },
|
|
{ "RX_QFC_EN", 10, 1 },
|
|
{ "QFC_FWD_UP", 9, 1 },
|
|
{ "PPP_FWD_UP", 8, 1 },
|
|
{ "PAUSE_FWD_UP", 7, 1 },
|
|
{ "LPBK_BP", 6, 1 },
|
|
{ "PASS_NO_MATCH", 5, 1 },
|
|
{ "IVLAN_EN", 4, 1 },
|
|
{ "OVLAN_EN3", 3, 1 },
|
|
{ "OVLAN_EN2", 2, 1 },
|
|
{ "OVLAN_EN1", 1, 1 },
|
|
{ "OVLAN_EN0", 0, 1 },
|
|
{ "MPS_PORT_RX_MTU", 0x30104, 0 },
|
|
{ "MPS_PORT_RX_PF_MAP", 0x30108, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP0", 0x3010c, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP1", 0x30110, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP2", 0x30114, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP3", 0x30118, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP4", 0x30150, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP5", 0x30154, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP6", 0x30158, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP7", 0x3015c, 0 },
|
|
{ "MPS_PORT_RX_IVLAN", 0x3011c, 0 },
|
|
{ "MPS_PORT_RX_OVLAN0", 0x30120, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN1", 0x30124, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN2", 0x30128, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN3", 0x3012c, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_RSS_HASH", 0x30130, 0 },
|
|
{ "MPS_PORT_RX_RSS_CONTROL", 0x30134, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL1", 0x30138, 0 },
|
|
{ "FIXED_PFVF_MAC", 14, 1 },
|
|
{ "FIXED_PFVF_LPBK", 13, 1 },
|
|
{ "FIXED_PFVF_LPBK_OV", 12, 1 },
|
|
{ "FIXED_PF", 9, 3 },
|
|
{ "FIXED_VF_VLD", 8, 1 },
|
|
{ "FIXED_VF", 0, 8 },
|
|
{ "MPS_PORT_RX_SPARE", 0x3013c, 0 },
|
|
{ "MPS_PORT_RX_PTP_RSS_HASH", 0x30140, 0 },
|
|
{ "MPS_PORT_RX_PTP_RSS_CONTROL", 0x30144, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_TS_VLD", 0x30148, 0 },
|
|
{ "MPS_PORT_RX_TNL_LKP_INNER_SEL", 0x3014c, 0 },
|
|
{ "MPS_PORT_RX_PRS_DEBUG_FLAG_MAC", 0x30160, 0 },
|
|
{ "Outer_IPv4_n_Inner_IPv4", 31, 1 },
|
|
{ "Outer_IPv4_n_Inner_IPv6", 30, 1 },
|
|
{ "Outer_IPv6_n_Inner_IPv4", 29, 1 },
|
|
{ "Outer_IPv6_n_Inner_IPv6", 28, 1 },
|
|
{ "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
|
|
{ "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
|
|
{ "Outer_IPv4_n_VLAN_GRE", 23, 1 },
|
|
{ "Outer_IPv6_n_VLAN_GRE", 22, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
|
|
{ "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
|
|
{ "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
|
|
{ "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
|
|
{ "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
|
|
{ "Err_Tnl_Hdr_Len", 11, 1 },
|
|
{ "non_runt_frame", 10, 1 },
|
|
{ "Inner_VLAN_VLD", 9, 1 },
|
|
{ "Err_IP_Payload_Len", 8, 1 },
|
|
{ "Err_UDP_Payload_Len", 7, 1 },
|
|
{ "MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK", 0x30164, 0 },
|
|
{ "Outer_IPv4_n_Inner_IPv4", 31, 1 },
|
|
{ "Outer_IPv4_n_Inner_IPv6", 30, 1 },
|
|
{ "Outer_IPv6_n_Inner_IPv4", 29, 1 },
|
|
{ "Outer_IPv6_n_Inner_IPv6", 28, 1 },
|
|
{ "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
|
|
{ "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
|
|
{ "Outer_IPv4_n_VLAN_GRE", 23, 1 },
|
|
{ "Outer_IPv6_n_VLAN_GRE", 22, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
|
|
{ "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
|
|
{ "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
|
|
{ "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
|
|
{ "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
|
|
{ "Err_Tnl_Hdr_Len", 11, 1 },
|
|
{ "Inner_VLAN_VLD", 10, 1 },
|
|
{ "Err_IP_Payload_Len", 9, 1 },
|
|
{ "Err_UDP_Payload_Len", 8, 1 },
|
|
{ "MPS_PORT_RX_REPL_VECT_SEL", 0x30168, 0 },
|
|
{ "DIS_REPL_VECT_SEL", 4, 1 },
|
|
{ "REPL_VECT_SEL", 0, 4 },
|
|
{ "MPS_PORT_RX_CTL", 0x34100, 0 },
|
|
{ "HASH_PRIO_SEL_LPBK", 25, 1 },
|
|
{ "HASH_PRIO_SEL_MAC", 24, 1 },
|
|
{ "HASH_EN_LPBK", 23, 1 },
|
|
{ "HASH_EN_MAC", 22, 1 },
|
|
{ "PTP_FWD_UP", 21, 1 },
|
|
{ "NO_RPLCT_M", 20, 1 },
|
|
{ "RPLCT_SEL_L", 18, 2 },
|
|
{ "FLTR_VLAN_SEL", 17, 1 },
|
|
{ "PRIO_VLAN_SEL", 16, 1 },
|
|
{ "CHK_8023_LEN_M", 15, 1 },
|
|
{ "CHK_8023_LEN_L", 14, 1 },
|
|
{ "NIV_DROP", 13, 1 },
|
|
{ "NOV_DROP", 12, 1 },
|
|
{ "CLS_PRT", 11, 1 },
|
|
{ "RX_QFC_EN", 10, 1 },
|
|
{ "QFC_FWD_UP", 9, 1 },
|
|
{ "PPP_FWD_UP", 8, 1 },
|
|
{ "PAUSE_FWD_UP", 7, 1 },
|
|
{ "LPBK_BP", 6, 1 },
|
|
{ "PASS_NO_MATCH", 5, 1 },
|
|
{ "IVLAN_EN", 4, 1 },
|
|
{ "OVLAN_EN3", 3, 1 },
|
|
{ "OVLAN_EN2", 2, 1 },
|
|
{ "OVLAN_EN1", 1, 1 },
|
|
{ "OVLAN_EN0", 0, 1 },
|
|
{ "MPS_PORT_RX_MTU", 0x34104, 0 },
|
|
{ "MPS_PORT_RX_PF_MAP", 0x34108, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP0", 0x3410c, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP1", 0x34110, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP2", 0x34114, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP3", 0x34118, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP4", 0x34150, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP5", 0x34154, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP6", 0x34158, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP7", 0x3415c, 0 },
|
|
{ "MPS_PORT_RX_IVLAN", 0x3411c, 0 },
|
|
{ "MPS_PORT_RX_OVLAN0", 0x34120, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN1", 0x34124, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN2", 0x34128, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN3", 0x3412c, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_RSS_HASH", 0x34130, 0 },
|
|
{ "MPS_PORT_RX_RSS_CONTROL", 0x34134, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL1", 0x34138, 0 },
|
|
{ "FIXED_PFVF_MAC", 14, 1 },
|
|
{ "FIXED_PFVF_LPBK", 13, 1 },
|
|
{ "FIXED_PFVF_LPBK_OV", 12, 1 },
|
|
{ "FIXED_PF", 9, 3 },
|
|
{ "FIXED_VF_VLD", 8, 1 },
|
|
{ "FIXED_VF", 0, 8 },
|
|
{ "MPS_PORT_RX_SPARE", 0x3413c, 0 },
|
|
{ "MPS_PORT_RX_PTP_RSS_HASH", 0x34140, 0 },
|
|
{ "MPS_PORT_RX_PTP_RSS_CONTROL", 0x34144, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_TS_VLD", 0x34148, 0 },
|
|
{ "MPS_PORT_RX_TNL_LKP_INNER_SEL", 0x3414c, 0 },
|
|
{ "MPS_PORT_RX_PRS_DEBUG_FLAG_MAC", 0x34160, 0 },
|
|
{ "Outer_IPv4_n_Inner_IPv4", 31, 1 },
|
|
{ "Outer_IPv4_n_Inner_IPv6", 30, 1 },
|
|
{ "Outer_IPv6_n_Inner_IPv4", 29, 1 },
|
|
{ "Outer_IPv6_n_Inner_IPv6", 28, 1 },
|
|
{ "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
|
|
{ "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
|
|
{ "Outer_IPv4_n_VLAN_GRE", 23, 1 },
|
|
{ "Outer_IPv6_n_VLAN_GRE", 22, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
|
|
{ "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
|
|
{ "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
|
|
{ "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
|
|
{ "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
|
|
{ "Err_Tnl_Hdr_Len", 11, 1 },
|
|
{ "non_runt_frame", 10, 1 },
|
|
{ "Inner_VLAN_VLD", 9, 1 },
|
|
{ "Err_IP_Payload_Len", 8, 1 },
|
|
{ "Err_UDP_Payload_Len", 7, 1 },
|
|
{ "MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK", 0x34164, 0 },
|
|
{ "Outer_IPv4_n_Inner_IPv4", 31, 1 },
|
|
{ "Outer_IPv4_n_Inner_IPv6", 30, 1 },
|
|
{ "Outer_IPv6_n_Inner_IPv4", 29, 1 },
|
|
{ "Outer_IPv6_n_Inner_IPv6", 28, 1 },
|
|
{ "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
|
|
{ "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
|
|
{ "Outer_IPv4_n_VLAN_GRE", 23, 1 },
|
|
{ "Outer_IPv6_n_VLAN_GRE", 22, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
|
|
{ "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
|
|
{ "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
|
|
{ "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
|
|
{ "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
|
|
{ "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
|
|
{ "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
|
|
{ "Err_Tnl_Hdr_Len", 11, 1 },
|
|
{ "Inner_VLAN_VLD", 10, 1 },
|
|
{ "Err_IP_Payload_Len", 9, 1 },
|
|
{ "Err_UDP_Payload_Len", 8, 1 },
|
|
{ "MPS_PORT_RX_REPL_VECT_SEL", 0x34168, 0 },
|
|
{ "DIS_REPL_VECT_SEL", 4, 1 },
|
|
{ "REPL_VECT_SEL", 0, 4 },
|
|
{ "MPS_TX_PRTY_SEL", 0x9400, 0 },
|
|
{ "Ch2_Prty", 12, 3 },
|
|
{ "Ch1_Prty", 8, 3 },
|
|
{ "Ch0_Prty", 4, 3 },
|
|
{ "TP_Source", 2, 2 },
|
|
{ "NCSI_Source", 0, 2 },
|
|
{ "MPS_TX_INT_ENABLE", 0x9404, 0 },
|
|
{ "PortErr", 16, 1 },
|
|
{ "FRMERR", 15, 1 },
|
|
{ "SECNTERR", 14, 1 },
|
|
{ "BUBBLE", 13, 1 },
|
|
{ "TxDescFifo", 9, 4 },
|
|
{ "TxDataFifo", 5, 4 },
|
|
{ "Ncsi", 4, 1 },
|
|
{ "TP", 0, 4 },
|
|
{ "MPS_TX_INT_CAUSE", 0x9408, 0 },
|
|
{ "PortErr", 16, 1 },
|
|
{ "FRMERR", 15, 1 },
|
|
{ "SECNTERR", 14, 1 },
|
|
{ "BUBBLE", 13, 1 },
|
|
{ "TxDescFifo", 9, 4 },
|
|
{ "TxDataFifo", 5, 4 },
|
|
{ "Ncsi", 4, 1 },
|
|
{ "TP", 0, 4 },
|
|
{ "MPS_TX_NCSI2MPS_CNT", 0x940c, 0 },
|
|
{ "MPS_TX_PERR_ENABLE", 0x9410, 0 },
|
|
{ "TxDescFifo", 9, 4 },
|
|
{ "TxDataFifo", 5, 4 },
|
|
{ "Ncsi", 4, 1 },
|
|
{ "TP", 0, 4 },
|
|
{ "MPS_TX_PERR_INJECT", 0x9414, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_TX_SE_CNT_TP01", 0x9418, 0 },
|
|
{ "SOP_CNT_1", 24, 8 },
|
|
{ "EOP_CNT_1", 16, 8 },
|
|
{ "SOP_CNT_0", 8, 8 },
|
|
{ "EOP_CNT_0", 0, 8 },
|
|
{ "MPS_TX_SE_CNT_TP23", 0x941c, 0 },
|
|
{ "SOP_CNT_3", 24, 8 },
|
|
{ "EOP_CNT_3", 16, 8 },
|
|
{ "SOP_CNT_2", 8, 8 },
|
|
{ "EOP_CNT_2", 0, 8 },
|
|
{ "MPS_TX_SE_CNT_MAC01", 0x9420, 0 },
|
|
{ "SOP_CNT_1", 24, 8 },
|
|
{ "EOP_CNT_1", 16, 8 },
|
|
{ "SOP_CNT_0", 8, 8 },
|
|
{ "EOP_CNT_0", 0, 8 },
|
|
{ "MPS_TX_SE_CNT_MAC23", 0x9424, 0 },
|
|
{ "SOP_CNT_3", 24, 8 },
|
|
{ "EOP_CNT_3", 16, 8 },
|
|
{ "SOP_CNT_2", 8, 8 },
|
|
{ "EOP_CNT_2", 0, 8 },
|
|
{ "MPS_TX_SECNT_SPI_BUBBLE_ERR", 0x9428, 0 },
|
|
{ "Bubble", 16, 8 },
|
|
{ "Spi", 8, 8 },
|
|
{ "SeCnt", 0, 8 },
|
|
{ "MPS_TX_SECNT_BUBBLE_CLR", 0x942c, 0 },
|
|
{ "NcsiSeCnt", 20, 1 },
|
|
{ "LpbkSeCnt", 16, 4 },
|
|
{ "Bubble", 8, 8 },
|
|
{ "SeCnt", 0, 8 },
|
|
{ "MPS_TX_PORT_ERR", 0x9430, 0 },
|
|
{ "Lpbkpt3", 7, 1 },
|
|
{ "Lpbkpt2", 6, 1 },
|
|
{ "Lpbkpt1", 5, 1 },
|
|
{ "Lpbkpt0", 4, 1 },
|
|
{ "pt3", 3, 1 },
|
|
{ "pt2", 2, 1 },
|
|
{ "pt1", 1, 1 },
|
|
{ "pt0", 0, 1 },
|
|
{ "MPS_TX_LPBK_DROP_BP_CTL_CH0", 0x9434, 0 },
|
|
{ "BpEn", 1, 1 },
|
|
{ "DropEn", 0, 1 },
|
|
{ "MPS_TX_LPBK_DROP_BP_CTL_CH1", 0x9438, 0 },
|
|
{ "BpEn", 1, 1 },
|
|
{ "DropEn", 0, 1 },
|
|
{ "MPS_TX_LPBK_DROP_BP_CTL_CH2", 0x943c, 0 },
|
|
{ "BpEn", 1, 1 },
|
|
{ "DropEn", 0, 1 },
|
|
{ "MPS_TX_LPBK_DROP_BP_CTL_CH3", 0x9440, 0 },
|
|
{ "BpEn", 1, 1 },
|
|
{ "DropEn", 0, 1 },
|
|
{ "MPS_TX_DEBUG_REG_TP2TX_10", 0x9444, 0 },
|
|
{ "SOPCh1", 31, 1 },
|
|
{ "EOPCh1", 30, 1 },
|
|
{ "SizeCh1", 27, 3 },
|
|
{ "ErrCh1", 26, 1 },
|
|
{ "FullCh1", 25, 1 },
|
|
{ "ValidCh1", 24, 1 },
|
|
{ "DataCh1", 16, 8 },
|
|
{ "SOPCh0", 15, 1 },
|
|
{ "EOPCh0", 14, 1 },
|
|
{ "SizeCh0", 11, 3 },
|
|
{ "ErrCh0", 10, 1 },
|
|
{ "FullCh0", 9, 1 },
|
|
{ "ValidCh0", 8, 1 },
|
|
{ "DataCh0", 0, 8 },
|
|
{ "MPS_TX_DEBUG_REG_TP2TX_32", 0x9448, 0 },
|
|
{ "SOPCh3", 31, 1 },
|
|
{ "EOPCh3", 30, 1 },
|
|
{ "SizeCh3", 27, 3 },
|
|
{ "ErrCh3", 26, 1 },
|
|
{ "FullCh3", 25, 1 },
|
|
{ "ValidCh3", 24, 1 },
|
|
{ "DataCh3", 16, 8 },
|
|
{ "SOPCh2", 15, 1 },
|
|
{ "EOPCh2", 14, 1 },
|
|
{ "SizeCh2", 11, 3 },
|
|
{ "ErrCh2", 10, 1 },
|
|
{ "FullCh2", 9, 1 },
|
|
{ "ValidCh2", 8, 1 },
|
|
{ "DataCh2", 0, 8 },
|
|
{ "MPS_TX_DEBUG_REG_TX2MAC_10", 0x944c, 0 },
|
|
{ "SOPPt1", 31, 1 },
|
|
{ "EOPPt1", 30, 1 },
|
|
{ "SizePt1", 27, 3 },
|
|
{ "ErrPt1", 26, 1 },
|
|
{ "FullPt1", 25, 1 },
|
|
{ "ValidPt1", 24, 1 },
|
|
{ "DataPt1", 16, 8 },
|
|
{ "SOPPt0", 15, 1 },
|
|
{ "EOPPt0", 14, 1 },
|
|
{ "SizePt0", 11, 3 },
|
|
{ "ErrPt0", 10, 1 },
|
|
{ "FullPt0", 9, 1 },
|
|
{ "ValidPt0", 8, 1 },
|
|
{ "DataPt0", 0, 8 },
|
|
{ "MPS_TX_DEBUG_REG_TX2MAC_32", 0x9450, 0 },
|
|
{ "SOPPt3", 31, 1 },
|
|
{ "EOPPt3", 30, 1 },
|
|
{ "SizePt3", 27, 3 },
|
|
{ "ErrPt3", 26, 1 },
|
|
{ "FullPt3", 25, 1 },
|
|
{ "ValidPt3", 24, 1 },
|
|
{ "DataPt3", 16, 8 },
|
|
{ "SOPPt2", 15, 1 },
|
|
{ "EOPPt2", 14, 1 },
|
|
{ "SizePt2", 11, 3 },
|
|
{ "ErrPt2", 10, 1 },
|
|
{ "FullPt2", 9, 1 },
|
|
{ "ValidPt2", 8, 1 },
|
|
{ "DataPt2", 0, 8 },
|
|
{ "MPS_TX_SGE_CH_PAUSE_IGNR", 0x9454, 0 },
|
|
{ "MPS_TX_DEBUG_SUBPART_SEL", 0x9458, 0 },
|
|
{ "SubPrtH", 11, 5 },
|
|
{ "PortH", 8, 3 },
|
|
{ "SubPrtL", 3, 5 },
|
|
{ "PortL", 0, 3 },
|
|
{ "MPS_TX_PAD_CTL", 0x945c, 0 },
|
|
{ "LpbkPadEnPt3", 7, 1 },
|
|
{ "LpbkPadEnPt2", 6, 1 },
|
|
{ "LpbkPadEnPt1", 5, 1 },
|
|
{ "LpbkPadEnPt0", 4, 1 },
|
|
{ "MacPadEnPt3", 3, 1 },
|
|
{ "MacPadEnPt2", 2, 1 },
|
|
{ "MacPadEnPt1", 1, 1 },
|
|
{ "MacPadEnPt0", 0, 1 },
|
|
{ "MPS_TX_PFVF_PORT_DROP_TP", 0x9460, 0 },
|
|
{ "TP2MPS_Ch1", 8, 8 },
|
|
{ "TP2MPS_Ch0", 0, 8 },
|
|
{ "MPS_TX_PFVF_PORT_DROP_NCSI", 0x9464, 0 },
|
|
{ "MPS_TX_PFVF_PORT_DROP_CTL", 0x9468, 0 },
|
|
{ "PFNOVFDROP", 5, 1 },
|
|
{ "NCSI_Ch4_CLR", 4, 1 },
|
|
{ "TP2MPS_Ch1_CLR", 1, 1 },
|
|
{ "TP2MPS_Ch0_CLR", 0, 1 },
|
|
{ "MPS_TX_CGEN", 0x946c, 0 },
|
|
{ "TxOutLpbk3_CGEN", 31, 1 },
|
|
{ "TxOutLpbk2_CGEN", 30, 1 },
|
|
{ "TxOutLpbk1_CGEN", 29, 1 },
|
|
{ "TxOutLpbk0_CGEN", 28, 1 },
|
|
{ "TxOutMAC3_CGEN", 27, 1 },
|
|
{ "TxOutMAC2_CGEN", 26, 1 },
|
|
{ "TxOutMAC1_CGEN", 25, 1 },
|
|
{ "TxOutMAC0_CGEN", 24, 1 },
|
|
{ "TxSchLpbk3_CGEN", 23, 1 },
|
|
{ "TxSchLpbk2_CGEN", 22, 1 },
|
|
{ "TxSchLpbk1_CGEN", 21, 1 },
|
|
{ "TxSchLpbk0_CGEN", 20, 1 },
|
|
{ "TxSchMAC3_CGEN", 19, 1 },
|
|
{ "TxSchMAC2_CGEN", 18, 1 },
|
|
{ "TxSchMAC1_CGEN", 17, 1 },
|
|
{ "TxSchMAC0_CGEN", 16, 1 },
|
|
{ "TxInCh4_CGEN", 15, 1 },
|
|
{ "TxInCh3_CGEN", 14, 1 },
|
|
{ "TxInCh2_CGEN", 13, 1 },
|
|
{ "TxInCh1_CGEN", 12, 1 },
|
|
{ "TxInCh0_CGEN", 11, 1 },
|
|
{ "MPS_TX_CGEN_DYNAMIC", 0x9470, 0 },
|
|
{ "TxOutLpbk3_CGEN", 31, 1 },
|
|
{ "TxOutLpbk2_CGEN", 30, 1 },
|
|
{ "TxOutLpbk1_CGEN", 29, 1 },
|
|
{ "TxOutLpbk0_CGEN", 28, 1 },
|
|
{ "TxOutMAC3_CGEN", 27, 1 },
|
|
{ "TxOutMAC2_CGEN", 26, 1 },
|
|
{ "TxOutMAC1_CGEN", 25, 1 },
|
|
{ "TxOutMAC0_CGEN", 24, 1 },
|
|
{ "TxSchLpbk3_CGEN", 23, 1 },
|
|
{ "TxSchLpbk2_CGEN", 22, 1 },
|
|
{ "TxSchLpbk1_CGEN", 21, 1 },
|
|
{ "TxSchLpbk0_CGEN", 20, 1 },
|
|
{ "TxSchMAC3_CGEN", 19, 1 },
|
|
{ "TxSchMAC2_CGEN", 18, 1 },
|
|
{ "TxSchMAC1_CGEN", 17, 1 },
|
|
{ "TxSchMAC0_CGEN", 16, 1 },
|
|
{ "TxInCh4_CGEN", 15, 1 },
|
|
{ "TxInCh3_CGEN", 14, 1 },
|
|
{ "TxInCh2_CGEN", 13, 1 },
|
|
{ "TxInCh1_CGEN", 12, 1 },
|
|
{ "TxInCh0_CGEN", 11, 1 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1e2e0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1e6e0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1eae0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1eee0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1f2e0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1f6e0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1fae0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1fee0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x30190, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x30194, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x30198, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3019c, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x301a0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x301a8, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x301ac, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x301b0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x301b4, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x301b8, 0 },
|
|
{ "MPS_PORT_TX_FIFO_CTL", 0x301c4, 0 },
|
|
{ "OUT_TH", 22, 8 },
|
|
{ "IN_TH", 14, 8 },
|
|
{ "FifoTh", 5, 9 },
|
|
{ "FifoEn", 4, 1 },
|
|
{ "MaxPktCnt", 0, 4 },
|
|
{ "MPS_PORT_FPGA_PAUSE_CTL", 0x301c8, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x301d0, 0 },
|
|
{ "off_pending", 8, 8 },
|
|
{ "on_pending", 0, 8 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x34190, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x34194, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x34198, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3419c, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x341a0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x341a8, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x341ac, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x341b0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x341b4, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x341b8, 0 },
|
|
{ "MPS_PORT_TX_FIFO_CTL", 0x341c4, 0 },
|
|
{ "OUT_TH", 22, 8 },
|
|
{ "IN_TH", 14, 8 },
|
|
{ "FifoTh", 5, 9 },
|
|
{ "FifoEn", 4, 1 },
|
|
{ "MaxPktCnt", 0, 4 },
|
|
{ "MPS_PORT_FPGA_PAUSE_CTL", 0x341c8, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x341d0, 0 },
|
|
{ "off_pending", 8, 8 },
|
|
{ "on_pending", 0, 8 },
|
|
{ "MPS_TRC_CFG", 0x9800, 0 },
|
|
{ "TrcMultiRSSFilter", 5, 1 },
|
|
{ "TrcFifoEmpty", 4, 1 },
|
|
{ "TrcIgnoreDropInput", 3, 1 },
|
|
{ "TrcKeepDuplicates", 2, 1 },
|
|
{ "TrcEn", 1, 1 },
|
|
{ "TrcMultiFilter", 0, 1 },
|
|
{ "MPS_TRC_FILTER0_RSS_HASH", 0x9804, 0 },
|
|
{ "MPS_TRC_FILTER0_RSS_CONTROL", 0x9808, 0 },
|
|
{ "RssControl", 16, 8 },
|
|
{ "QueueNumber", 0, 16 },
|
|
{ "MPS_TRC_FILTER1_RSS_HASH", 0x9ff0, 0 },
|
|
{ "MPS_TRC_FILTER1_RSS_CONTROL", 0x9ff4, 0 },
|
|
{ "RssControl", 16, 8 },
|
|
{ "QueueNumber", 0, 16 },
|
|
{ "MPS_TRC_FILTER2_RSS_HASH", 0x9ff8, 0 },
|
|
{ "MPS_TRC_FILTER2_RSS_CONTROL", 0x9ffc, 0 },
|
|
{ "RssControl", 16, 8 },
|
|
{ "QueueNumber", 0, 16 },
|
|
{ "MPS_TRC_FILTER3_RSS_HASH", 0xa000, 0 },
|
|
{ "MPS_TRC_FILTER3_RSS_CONTROL", 0xa004, 0 },
|
|
{ "RssControl", 16, 8 },
|
|
{ "QueueNumber", 0, 16 },
|
|
{ "MPS_TRC_RSS_HASH", 0xa008, 0 },
|
|
{ "MPS_TRC_RSS_CONTROL", 0xa00c, 0 },
|
|
{ "RssControl", 16, 8 },
|
|
{ "QueueNumber", 0, 16 },
|
|
{ "MPS_TRC_VF_OFF_FILTER_0", 0xa010, 0 },
|
|
{ "TrcMPS2TP_MacOnly", 22, 1 },
|
|
{ "TrcAllMPS2TP", 21, 1 },
|
|
{ "TrcAllTP2MPS", 20, 1 },
|
|
{ "TrcAllVf", 19, 1 },
|
|
{ "OffEn", 18, 1 },
|
|
{ "VfFiltEn", 17, 1 },
|
|
{ "VfFiltMask", 9, 8 },
|
|
{ "VfFiltValid", 8, 1 },
|
|
{ "VfFiltData", 0, 8 },
|
|
{ "MPS_TRC_VF_OFF_FILTER_1", 0xa014, 0 },
|
|
{ "TrcMPS2TP_MacOnly", 22, 1 },
|
|
{ "TrcAllMPS2TP", 21, 1 },
|
|
{ "TrcAllTP2MPS", 20, 1 },
|
|
{ "TrcAllVf", 19, 1 },
|
|
{ "OffEn", 18, 1 },
|
|
{ "VfFiltEn", 17, 1 },
|
|
{ "VfFiltMask", 9, 8 },
|
|
{ "VfFiltValid", 8, 1 },
|
|
{ "VfFiltData", 0, 8 },
|
|
{ "MPS_TRC_VF_OFF_FILTER_2", 0xa018, 0 },
|
|
{ "TrcMPS2TP_MacOnly", 22, 1 },
|
|
{ "TrcAllMPS2TP", 21, 1 },
|
|
{ "TrcAllTP2MPS", 20, 1 },
|
|
{ "TrcAllVf", 19, 1 },
|
|
{ "OffEn", 18, 1 },
|
|
{ "VfFiltEn", 17, 1 },
|
|
{ "VfFiltMask", 9, 8 },
|
|
{ "VfFiltValid", 8, 1 },
|
|
{ "VfFiltData", 0, 8 },
|
|
{ "MPS_TRC_VF_OFF_FILTER_3", 0xa01c, 0 },
|
|
{ "TrcMPS2TP_MacOnly", 22, 1 },
|
|
{ "TrcAllMPS2TP", 21, 1 },
|
|
{ "TrcAllTP2MPS", 20, 1 },
|
|
{ "TrcAllVf", 19, 1 },
|
|
{ "OffEn", 18, 1 },
|
|
{ "VfFiltEn", 17, 1 },
|
|
{ "VfFiltMask", 9, 8 },
|
|
{ "VfFiltValid", 8, 1 },
|
|
{ "VfFiltData", 0, 8 },
|
|
{ "MPS_TRC_CGEN", 0xa020, 0 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x9810, 0 },
|
|
{ "TfInsertActLen", 27, 1 },
|
|
{ "TfInsertTimer", 26, 1 },
|
|
{ "TfInvertMatch", 25, 1 },
|
|
{ "TfPktTooLarge", 24, 1 },
|
|
{ "TfEn", 23, 1 },
|
|
{ "TfPort", 18, 5 },
|
|
{ "TfDrop", 17, 1 },
|
|
{ "TfSopEopErr", 16, 1 },
|
|
{ "TfLength", 8, 5 },
|
|
{ "TfOffset", 0, 5 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x9814, 0 },
|
|
{ "TfInsertActLen", 27, 1 },
|
|
{ "TfInsertTimer", 26, 1 },
|
|
{ "TfInvertMatch", 25, 1 },
|
|
{ "TfPktTooLarge", 24, 1 },
|
|
{ "TfEn", 23, 1 },
|
|
{ "TfPort", 18, 5 },
|
|
{ "TfDrop", 17, 1 },
|
|
{ "TfSopEopErr", 16, 1 },
|
|
{ "TfLength", 8, 5 },
|
|
{ "TfOffset", 0, 5 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x9818, 0 },
|
|
{ "TfInsertActLen", 27, 1 },
|
|
{ "TfInsertTimer", 26, 1 },
|
|
{ "TfInvertMatch", 25, 1 },
|
|
{ "TfPktTooLarge", 24, 1 },
|
|
{ "TfEn", 23, 1 },
|
|
{ "TfPort", 18, 5 },
|
|
{ "TfDrop", 17, 1 },
|
|
{ "TfSopEopErr", 16, 1 },
|
|
{ "TfLength", 8, 5 },
|
|
{ "TfOffset", 0, 5 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x981c, 0 },
|
|
{ "TfInsertActLen", 27, 1 },
|
|
{ "TfInsertTimer", 26, 1 },
|
|
{ "TfInvertMatch", 25, 1 },
|
|
{ "TfPktTooLarge", 24, 1 },
|
|
{ "TfEn", 23, 1 },
|
|
{ "TfPort", 18, 5 },
|
|
{ "TfDrop", 17, 1 },
|
|
{ "TfSopEopErr", 16, 1 },
|
|
{ "TfLength", 8, 5 },
|
|
{ "TfOffset", 0, 5 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x9820, 0 },
|
|
{ "TfMinPktSize", 16, 9 },
|
|
{ "TfCaptureMax", 0, 14 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x9824, 0 },
|
|
{ "TfMinPktSize", 16, 9 },
|
|
{ "TfCaptureMax", 0, 14 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x9828, 0 },
|
|
{ "TfMinPktSize", 16, 9 },
|
|
{ "TfCaptureMax", 0, 14 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x982c, 0 },
|
|
{ "TfMinPktSize", 16, 9 },
|
|
{ "TfCaptureMax", 0, 14 },
|
|
{ "MPS_TRC_FILTER_RUNT_CTL", 0x9830, 0 },
|
|
{ "MPS_TRC_FILTER_RUNT_CTL", 0x9834, 0 },
|
|
{ "MPS_TRC_FILTER_RUNT_CTL", 0x9838, 0 },
|
|
{ "MPS_TRC_FILTER_RUNT_CTL", 0x983c, 0 },
|
|
{ "MPS_TRC_FILTER_DROP", 0x9840, 0 },
|
|
{ "TfDropInpCount", 16, 16 },
|
|
{ "TfDropBufferCount", 0, 16 },
|
|
{ "MPS_TRC_FILTER_DROP", 0x9844, 0 },
|
|
{ "TfDropInpCount", 16, 16 },
|
|
{ "TfDropBufferCount", 0, 16 },
|
|
{ "MPS_TRC_FILTER_DROP", 0x9848, 0 },
|
|
{ "TfDropInpCount", 16, 16 },
|
|
{ "TfDropBufferCount", 0, 16 },
|
|
{ "MPS_TRC_FILTER_DROP", 0x984c, 0 },
|
|
{ "TfDropInpCount", 16, 16 },
|
|
{ "TfDropBufferCount", 0, 16 },
|
|
{ "MPS_TRC_PERR_INJECT", 0x9850, 0 },
|
|
{ "MemSel", 1, 4 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_TRC_PERR_ENABLE", 0x9854, 0 },
|
|
{ "MiscPerr", 8, 1 },
|
|
{ "PktFifo", 4, 4 },
|
|
{ "FiltMem", 0, 4 },
|
|
{ "MPS_TRC_INT_ENABLE", 0x9858, 0 },
|
|
{ "PLErrEnb", 9, 1 },
|
|
{ "MiscPerr", 8, 1 },
|
|
{ "PktFifo", 4, 4 },
|
|
{ "FiltMem", 0, 4 },
|
|
{ "MPS_TRC_INT_CAUSE", 0x985c, 0 },
|
|
{ "PLErrEnb", 9, 1 },
|
|
{ "MiscPerr", 8, 1 },
|
|
{ "PktFifo", 4, 4 },
|
|
{ "FiltMem", 0, 4 },
|
|
{ "MPS_TRC_TIMESTAMP_L", 0x9860, 0 },
|
|
{ "MPS_TRC_TIMESTAMP_H", 0x9864, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c00, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c04, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c08, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c0c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c10, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c14, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c18, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c1c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c20, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c24, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c28, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c2c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c30, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c34, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c38, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c3c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c40, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c44, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c48, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c4c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c50, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c54, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c58, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c5c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c60, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c64, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c68, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c6c, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c80, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c84, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c88, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c8c, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c90, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c94, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c98, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c9c, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cac, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cbc, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ccc, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cdc, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cec, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d00, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d04, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d08, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d0c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d10, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d14, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d18, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d1c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d20, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d24, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d28, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d2c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d30, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d34, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d38, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d3c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d40, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d44, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d48, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d4c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d50, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d54, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d58, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d5c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d60, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d64, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d68, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d6c, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d80, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d84, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d88, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d8c, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d90, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d94, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d98, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d9c, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dac, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dbc, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dcc, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9ddc, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dec, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e00, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e04, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e08, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e0c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e10, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e14, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e18, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e1c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e20, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e24, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e28, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e2c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e30, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e34, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e38, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e3c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e40, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e44, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e48, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e4c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e50, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e54, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e58, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e5c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e60, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e64, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e68, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e6c, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e80, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e84, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e88, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e8c, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e90, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e94, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e98, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e9c, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eac, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ebc, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ecc, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9edc, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eec, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f00, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f04, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f08, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f0c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f10, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f14, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f18, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f1c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f20, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f24, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f28, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f2c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f30, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f34, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f38, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f3c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f40, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f44, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f48, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f4c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f50, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f54, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f58, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f5c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f60, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f64, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f68, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f6c, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f80, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f84, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f88, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f8c, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f90, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f94, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f98, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f9c, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fac, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fbc, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fcc, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fdc, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fec, 0 },
|
|
{ "MPS_STAT_CTL", 0x9600, 0 },
|
|
{ "StatStopCtrl", 10, 1 },
|
|
{ "StopStat", 9, 1 },
|
|
{ "StatWriteCtrl", 8, 1 },
|
|
{ "CountLbPF", 7, 1 },
|
|
{ "CountLbVF", 6, 1 },
|
|
{ "CountPauseMCRx", 5, 1 },
|
|
{ "CountPauseStatRx", 4, 1 },
|
|
{ "CountPauseMCTx", 3, 1 },
|
|
{ "CountPauseStatTx", 2, 1 },
|
|
{ "CountVFinPF", 1, 1 },
|
|
{ "LpbkErrStat", 0, 1 },
|
|
{ "MPS_STAT_INT_ENABLE", 0x9608, 0 },
|
|
{ "MPS_STAT_INT_CAUSE", 0x960c, 0 },
|
|
{ "MPS_STAT_PERR_INT_ENABLE_SRAM", 0x9610, 0 },
|
|
{ "Rxbg", 27, 2 },
|
|
{ "Rxpf", 22, 5 },
|
|
{ "Txpf", 18, 4 },
|
|
{ "Rxport", 11, 7 },
|
|
{ "Lbport", 6, 5 },
|
|
{ "Txport", 0, 6 },
|
|
{ "MPS_STAT_PERR_INT_CAUSE_SRAM", 0x9614, 0 },
|
|
{ "Rxbg", 27, 2 },
|
|
{ "Rxpf", 22, 5 },
|
|
{ "Txpf", 18, 4 },
|
|
{ "Rxport", 11, 7 },
|
|
{ "Lbport", 6, 5 },
|
|
{ "Txport", 0, 6 },
|
|
{ "MPS_STAT_PERR_ENABLE_SRAM", 0x9618, 0 },
|
|
{ "Rxbg", 27, 2 },
|
|
{ "Rxpf", 22, 5 },
|
|
{ "Txpf", 18, 4 },
|
|
{ "Rxport", 11, 7 },
|
|
{ "Lbport", 6, 5 },
|
|
{ "Txport", 0, 6 },
|
|
{ "MPS_STAT_PERR_INT_ENABLE_TX_FIFO", 0x961c, 0 },
|
|
{ "TxCh", 20, 4 },
|
|
{ "Tx", 12, 8 },
|
|
{ "Pause", 8, 4 },
|
|
{ "Drop", 0, 8 },
|
|
{ "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 0x9620, 0 },
|
|
{ "TxCh", 20, 4 },
|
|
{ "Tx", 12, 8 },
|
|
{ "Pause", 8, 4 },
|
|
{ "Drop", 0, 8 },
|
|
{ "MPS_STAT_PERR_ENABLE_TX_FIFO", 0x9624, 0 },
|
|
{ "TxCh", 20, 4 },
|
|
{ "Tx", 12, 8 },
|
|
{ "Pause", 8, 4 },
|
|
{ "Drop", 0, 8 },
|
|
{ "MPS_STAT_PERR_INT_ENABLE_RX_FIFO", 0x9628, 0 },
|
|
{ "Pause", 20, 4 },
|
|
{ "Lpbk", 16, 4 },
|
|
{ "Nq", 8, 8 },
|
|
{ "PV", 4, 4 },
|
|
{ "Mac", 0, 4 },
|
|
{ "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 0x962c, 0 },
|
|
{ "Pause", 20, 4 },
|
|
{ "Lpbk", 16, 4 },
|
|
{ "Nq", 8, 8 },
|
|
{ "PV", 4, 4 },
|
|
{ "Mac", 0, 4 },
|
|
{ "MPS_STAT_PERR_ENABLE_RX_FIFO", 0x9630, 0 },
|
|
{ "Pause", 20, 4 },
|
|
{ "Lpbk", 16, 4 },
|
|
{ "Nq", 8, 8 },
|
|
{ "PV", 4, 4 },
|
|
{ "Mac", 0, 4 },
|
|
{ "MPS_STAT_PERR_INJECT", 0x9634, 0 },
|
|
{ "MemSel", 1, 7 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_STAT_DEBUG_SUB_SEL", 0x9638, 0 },
|
|
{ "SubPrtH", 5, 5 },
|
|
{ "SubPrtL", 0, 5 },
|
|
{ "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L", 0x9640, 0 },
|
|
{ "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H", 0x9644, 0 },
|
|
{ "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L", 0x9648, 0 },
|
|
{ "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H", 0x964c, 0 },
|
|
{ "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L", 0x9650, 0 },
|
|
{ "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H", 0x9654, 0 },
|
|
{ "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L", 0x9658, 0 },
|
|
{ "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H", 0x965c, 0 },
|
|
{ "MPS_STAT_RX_BG_0_LB_DROP_FRAME_L", 0x9660, 0 },
|
|
{ "MPS_STAT_RX_BG_0_LB_DROP_FRAME_H", 0x9664, 0 },
|
|
{ "MPS_STAT_RX_BG_1_LB_DROP_FRAME_L", 0x9668, 0 },
|
|
{ "MPS_STAT_RX_BG_1_LB_DROP_FRAME_H", 0x966c, 0 },
|
|
{ "MPS_STAT_RX_BG_2_LB_DROP_FRAME_L", 0x9670, 0 },
|
|
{ "MPS_STAT_RX_BG_2_LB_DROP_FRAME_H", 0x9674, 0 },
|
|
{ "MPS_STAT_RX_BG_3_LB_DROP_FRAME_L", 0x9678, 0 },
|
|
{ "MPS_STAT_RX_BG_3_LB_DROP_FRAME_H", 0x967c, 0 },
|
|
{ "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L", 0x9680, 0 },
|
|
{ "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H", 0x9684, 0 },
|
|
{ "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L", 0x9688, 0 },
|
|
{ "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H", 0x968c, 0 },
|
|
{ "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L", 0x9690, 0 },
|
|
{ "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H", 0x9694, 0 },
|
|
{ "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L", 0x9698, 0 },
|
|
{ "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H", 0x969c, 0 },
|
|
{ "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L", 0x96a0, 0 },
|
|
{ "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H", 0x96a4, 0 },
|
|
{ "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L", 0x96a8, 0 },
|
|
{ "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H", 0x96ac, 0 },
|
|
{ "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L", 0x96b0, 0 },
|
|
{ "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H", 0x96b4, 0 },
|
|
{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L", 0x96b8, 0 },
|
|
{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H", 0x96bc, 0 },
|
|
{ "MPS_STAT_PERR_INT_ENABLE_SRAM1", 0x96c0, 0 },
|
|
{ "Rxvf", 5, 3 },
|
|
{ "Txvf", 0, 5 },
|
|
{ "MPS_STAT_PERR_INT_CAUSE_SRAM1", 0x96c4, 0 },
|
|
{ "Rxvf", 5, 3 },
|
|
{ "Txvf", 0, 5 },
|
|
{ "MPS_STAT_PERR_ENABLE_SRAM1", 0x96c8, 0 },
|
|
{ "Rxvf", 5, 3 },
|
|
{ "Txvf", 0, 5 },
|
|
{ "MPS_STAT_STOP_UPD_BG", 0x96cc, 0 },
|
|
{ "MPS_STAT_STOP_UPD_PORT", 0x96d0, 0 },
|
|
{ "PtLpbk", 8, 4 },
|
|
{ "PtTx", 4, 4 },
|
|
{ "PtRx", 0, 4 },
|
|
{ "MPS_STAT_STOP_UPD_PF", 0x96d4, 0 },
|
|
{ "PFTx", 8, 8 },
|
|
{ "PFRx", 0, 8 },
|
|
{ "MPS_STAT_STOP_UPD_TX_VF_0_31", 0x96d8, 0 },
|
|
{ "MPS_STAT_STOP_UPD_TX_VF_32_63", 0x96dc, 0 },
|
|
{ "MPS_STAT_STOP_UPD_TX_VF_64_95", 0x96e0, 0 },
|
|
{ "MPS_STAT_STOP_UPD_TX_VF_96_127", 0x96e4, 0 },
|
|
{ "MPS_STAT_STOP_UPD_TX_VF_128_159", 0x9710, 0 },
|
|
{ "MPS_STAT_STOP_UPD_TX_VF_160_191", 0x9714, 0 },
|
|
{ "MPS_STAT_STOP_UPD_TX_VF_192_223", 0x9718, 0 },
|
|
{ "MPS_STAT_STOP_UPD_TX_VF_224_255", 0x971c, 0 },
|
|
{ "MPS_STAT_STOP_UPD_RX_VF_0_31", 0x96e8, 0 },
|
|
{ "MPS_STAT_STOP_UPD_RX_VF_32_63", 0x96ec, 0 },
|
|
{ "MPS_STAT_STOP_UPD_RX_VF_64_95", 0x96f0, 0 },
|
|
{ "MPS_STAT_STOP_UPD_RX_VF_96_127", 0x96f4, 0 },
|
|
{ "MPS_STAT_STOP_UPD_RX_VF_128_159", 0x96f8, 0 },
|
|
{ "MPS_STAT_STOP_UPD_RX_VF_160_191", 0x96fc, 0 },
|
|
{ "MPS_STAT_STOP_UPD_RX_VF_192_223", 0x9700, 0 },
|
|
{ "MPS_STAT_STOP_UPD_RX_VF_224_255", 0x9704, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x30400, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x30404, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x30408, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3040c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x30410, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x30414, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x30418, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3041c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x30420, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x30424, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x30428, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3042c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x30430, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x30434, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x30438, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3043c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x30440, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x30444, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x30448, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3044c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x30450, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x30454, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x30458, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3045c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x30460, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x30464, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x30468, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3046c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x30470, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x30474, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x30478, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3047c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x30480, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x30484, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x30488, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3048c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x30490, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x30494, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x30498, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3049c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x304a0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x304a4, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x304a8, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x304ac, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x304b0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x304b4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x304c0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x304c4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x304c8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x304cc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x304d0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x304d4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x304d8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x304dc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x304e0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x304e4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x304e8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x304ec, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x304f0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x304f4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x304f8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x304fc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x30500, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x30504, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x30508, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3050c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x30510, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x30514, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x30518, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3051c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x30520, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x30524, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x30528, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3052c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x30540, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x30544, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x30548, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3054c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x30550, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x30554, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x30558, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3055c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x30560, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x30564, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x30568, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3056c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x30570, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x30574, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x30578, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3057c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x30580, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x30584, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x30588, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3058c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x30590, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x30594, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x30598, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3059c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x305a0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x305a4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x305a8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x305ac, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x305b0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x305b4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x305b8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x305bc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x305c0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x305c4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x305c8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x305cc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x305d0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x305d4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x305d8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x305dc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x305e0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x305e4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x305e8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x305ec, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x305f0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x305f4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x305f8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x305fc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x30600, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x30604, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x30608, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3060c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x30610, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x30614, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x30618, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3061c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x34400, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x34404, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x34408, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3440c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x34410, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x34414, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x34418, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3441c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x34420, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x34424, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x34428, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3442c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x34430, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x34434, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x34438, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3443c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x34440, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x34444, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x34448, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3444c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x34450, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x34454, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x34458, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3445c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x34460, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x34464, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x34468, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3446c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x34470, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x34474, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x34478, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3447c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x34480, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x34484, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x34488, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3448c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x34490, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x34494, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x34498, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3449c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x344a0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x344a4, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x344a8, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x344ac, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x344b0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x344b4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x344c0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x344c4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x344c8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x344cc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x344d0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x344d4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x344d8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x344dc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x344e0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x344e4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x344e8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x344ec, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x344f0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x344f4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x344f8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x344fc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x34500, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x34504, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x34508, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3450c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x34510, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x34514, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x34518, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3451c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x34520, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x34524, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x34528, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3452c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x34540, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x34544, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x34548, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3454c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x34550, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x34554, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x34558, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3455c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x34560, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x34564, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x34568, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3456c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x34570, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x34574, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x34578, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3457c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x34580, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x34584, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x34588, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3458c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x34590, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x34594, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x34598, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3459c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x345a0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x345a4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x345a8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x345ac, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x345b0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x345b4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x345b8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x345bc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x345c0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x345c4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x345c8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x345cc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x345d0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x345d4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x345d8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x345dc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x345e0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x345e4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x345e8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x345ec, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x345f0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x345f4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x345f8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x345fc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x34600, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x34604, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x34608, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3460c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x34610, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x34614, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x34618, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3461c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e300, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e304, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e308, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e30c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e310, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e314, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e318, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e31c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e320, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e324, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e328, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e32c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e330, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e334, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e338, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e33c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e340, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e344, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e348, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e34c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e350, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e354, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e358, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e35c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e360, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e364, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e368, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e36c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e370, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e374, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e378, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e37c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e380, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e384, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e700, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e704, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e708, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e70c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e710, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e714, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e718, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e71c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e720, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e724, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e728, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e72c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e730, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e734, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e738, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e73c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e740, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e744, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e748, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e74c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e750, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e754, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e758, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e75c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e760, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e764, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e768, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e76c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e770, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e774, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e778, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e77c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e780, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e784, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1eb00, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1eb04, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1eb08, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1eb0c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1eb10, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1eb14, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1eb18, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1eb1c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1eb20, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1eb24, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1eb28, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1eb2c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1eb30, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1eb34, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1eb38, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1eb3c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1eb40, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1eb44, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1eb48, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1eb4c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1eb50, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1eb54, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1eb58, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1eb5c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1eb60, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1eb64, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1eb68, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1eb6c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1eb70, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1eb74, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1eb78, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1eb7c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1eb80, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1eb84, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ef00, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ef04, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ef08, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ef0c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ef10, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ef14, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ef18, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ef1c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ef20, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ef24, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ef28, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ef2c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ef30, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ef34, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ef38, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ef3c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ef40, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ef44, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ef48, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ef4c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ef50, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ef54, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ef58, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ef5c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ef60, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ef64, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ef68, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ef6c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ef70, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ef74, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ef78, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ef7c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ef80, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ef84, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f300, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f304, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f308, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f30c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f310, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f314, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f318, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f31c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f320, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f324, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f328, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f32c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f330, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f334, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f338, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f33c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f340, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f344, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f348, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f34c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f350, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f354, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f358, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f35c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f360, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f364, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f368, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f36c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f370, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f374, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f378, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f37c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f380, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f384, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f700, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f704, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f708, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f70c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f710, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f714, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f718, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f71c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f720, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f724, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f728, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f72c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f730, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f734, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f738, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f73c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f740, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f744, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f748, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f74c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f750, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f754, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f758, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f75c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f760, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f764, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f768, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f76c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f770, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f774, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f778, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f77c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f780, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f784, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1fb00, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1fb04, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1fb08, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1fb0c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1fb10, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1fb14, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1fb18, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1fb1c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1fb20, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1fb24, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1fb28, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1fb2c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1fb30, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1fb34, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1fb38, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1fb3c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1fb40, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1fb44, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1fb48, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1fb4c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1fb50, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1fb54, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1fb58, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1fb5c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1fb60, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1fb64, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1fb68, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1fb6c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1fb70, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1fb74, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1fb78, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1fb7c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1fb80, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1fb84, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ff00, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ff04, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ff08, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ff0c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ff10, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ff14, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ff18, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ff1c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ff20, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ff24, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ff28, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ff2c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ff30, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ff34, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ff38, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ff3c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ff40, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ff44, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ff48, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ff4c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ff50, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ff54, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ff58, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ff5c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ff60, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ff64, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ff68, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ff6c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ff70, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ff74, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ff78, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ff7c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ff80, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ff84, 0 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30200, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30204, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30208, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3020c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30210, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30214, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30218, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3021c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30220, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30224, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30228, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3022c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30230, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30234, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30238, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3023c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30240, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30244, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30248, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3024c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30250, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30254, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30258, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3025c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30260, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30264, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30268, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3026c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30270, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30274, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30278, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3027c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30280, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30284, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30288, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3028c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30290, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30294, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30298, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3029c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302a0, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302a4, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302a8, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302ac, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302b0, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302b4, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302b8, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302bc, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302c0, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302c4, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302c8, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302cc, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302d0, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302d4, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302d8, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302dc, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302e0, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302e4, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302e8, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302ec, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302f0, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302f4, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302f8, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302fc, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30300, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34200, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34204, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34208, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3420c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34210, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34214, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34218, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3421c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34220, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34224, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34228, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3422c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34230, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34234, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34238, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3423c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34240, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34244, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34248, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3424c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34250, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34254, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34258, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3425c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34260, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34264, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34268, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3426c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34270, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34274, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34278, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3427c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34280, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34284, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34288, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3428c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34290, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34294, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34298, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3429c, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342a0, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342a4, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342a8, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342ac, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342b0, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342b4, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342b8, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342bc, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342c0, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342c4, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342c8, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342cc, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342d0, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342d4, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342d8, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342dc, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342e0, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342e4, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342e8, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342ec, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342f0, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342f4, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342f8, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342fc, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34300, 0 },
|
|
{ "DisEncapOuterRplct", 23, 1 },
|
|
{ "DisEncap", 22, 1 },
|
|
{ "Valid", 21, 1 },
|
|
{ "PortMap", 17, 4 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_HASH_CTL", 0x30304, 0 },
|
|
{ "UnicastEnable", 31, 1 },
|
|
{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x30308, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3030c, 0 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x30310, 0 },
|
|
{ "MatchAll", 18, 1 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_PORT_CLS_BMC_VLAN", 0x30314, 0 },
|
|
{ "BMC_VLAN_SEL", 13, 1 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PORT_CLS_CTL", 0x30318, 0 },
|
|
{ "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
|
|
{ "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
|
|
{ "LPBK_TCAM_PRIORITY", 12, 1 },
|
|
{ "LPBK_SMAC_TCAM_SEL", 10, 2 },
|
|
{ "LPBK_DMAC_TCAM_SEL", 8, 2 },
|
|
{ "TCAM1_HIT_PRIORITY", 7, 1 },
|
|
{ "TCAM0_HIT_PRIORITY", 6, 1 },
|
|
{ "TCAM_PRIORITY", 5, 1 },
|
|
{ "SMAC_TCAM_SEL", 3, 2 },
|
|
{ "DMAC_TCAM_SEL", 1, 2 },
|
|
{ "PF_VLAN_SEL", 0, 1 },
|
|
{ "MPS_PORT_CLS_NCSI_ETH_TYPE", 0x3031c, 0 },
|
|
{ "EthType1", 16, 16 },
|
|
{ "EthType2", 0, 16 },
|
|
{ "MPS_PORT_CLS_NCSI_ETH_TYPE_EN", 0x30320, 0 },
|
|
{ "EN1", 1, 1 },
|
|
{ "EN2", 0, 1 },
|
|
{ "MPS_PORT_CLS_HASH_CTL", 0x34304, 0 },
|
|
{ "UnicastEnable", 31, 1 },
|
|
{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x34308, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "MultiListen", 16, 1 },
|
|
{ "Priority", 13, 3 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3430c, 0 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x34310, 0 },
|
|
{ "MatchAll", 18, 1 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_PORT_CLS_BMC_VLAN", 0x34314, 0 },
|
|
{ "BMC_VLAN_SEL", 13, 1 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PORT_CLS_CTL", 0x34318, 0 },
|
|
{ "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
|
|
{ "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
|
|
{ "LPBK_TCAM_PRIORITY", 12, 1 },
|
|
{ "LPBK_SMAC_TCAM_SEL", 10, 2 },
|
|
{ "LPBK_DMAC_TCAM_SEL", 8, 2 },
|
|
{ "TCAM1_HIT_PRIORITY", 7, 1 },
|
|
{ "TCAM0_HIT_PRIORITY", 6, 1 },
|
|
{ "TCAM_PRIORITY", 5, 1 },
|
|
{ "SMAC_TCAM_SEL", 3, 2 },
|
|
{ "DMAC_TCAM_SEL", 1, 2 },
|
|
{ "PF_VLAN_SEL", 0, 1 },
|
|
{ "MPS_PORT_CLS_NCSI_ETH_TYPE", 0x3431c, 0 },
|
|
{ "EthType1", 16, 16 },
|
|
{ "EthType2", 0, 16 },
|
|
{ "MPS_PORT_CLS_NCSI_ETH_TYPE_EN", 0x34320, 0 },
|
|
{ "EN1", 1, 1 },
|
|
{ "EN2", 0, 1 },
|
|
{ "MPS_CLS_CTL", 0xd000, 0 },
|
|
{ "VlanClsEn_in", 7, 1 },
|
|
{ "DisTcamParChk", 6, 1 },
|
|
{ "VlanLkpEn", 5, 1 },
|
|
{ "MemWriteFault", 4, 1 },
|
|
{ "MemWriteWaiting", 3, 1 },
|
|
{ "CimNoPromiscuous", 2, 1 },
|
|
{ "HypervisorOnly", 1, 1 },
|
|
{ "VlanClsEn", 0, 1 },
|
|
{ "MPS_CLS_ARB_WEIGHT", 0xd004, 0 },
|
|
{ "PlWeight", 16, 5 },
|
|
{ "CimWeight", 8, 5 },
|
|
{ "LpbkWeight", 0, 5 },
|
|
{ "MPS_CLS_NCSI_ETH_TYPE", 0xd008, 0 },
|
|
{ "EthType1", 16, 16 },
|
|
{ "EthType2", 0, 16 },
|
|
{ "MPS_CLS_NCSI_ETH_TYPE_EN", 0xd00c, 0 },
|
|
{ "EN1", 1, 1 },
|
|
{ "EN2", 0, 1 },
|
|
{ "MPS_CLS_BMC_MAC_ADDR_L", 0xd010, 0 },
|
|
{ "MPS_CLS_BMC_MAC_ADDR_H", 0xd014, 0 },
|
|
{ "MatchAll", 18, 1 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_CLS_BMC_VLAN", 0xd018, 0 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_PERR_INJECT", 0xd01c, 0 },
|
|
{ "MemSel", 1, 2 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_CLS_PERR_ENABLE", 0xd020, 0 },
|
|
{ "HashSRAM", 2, 1 },
|
|
{ "MatchTCAM", 1, 1 },
|
|
{ "MatchSRAM", 0, 1 },
|
|
{ "MPS_CLS_INT_ENABLE", 0xd024, 0 },
|
|
{ "PLErrEnb", 3, 1 },
|
|
{ "HashSRAM", 2, 1 },
|
|
{ "MatchTCAM", 1, 1 },
|
|
{ "MatchSRAM", 0, 1 },
|
|
{ "MPS_CLS_INT_CAUSE", 0xd028, 0 },
|
|
{ "PLErrEnb", 3, 1 },
|
|
{ "HashSRAM", 2, 1 },
|
|
{ "MatchTCAM", 1, 1 },
|
|
{ "MatchSRAM", 0, 1 },
|
|
{ "MPS_CLS_PL_TEST_DATA_L", 0xd02c, 0 },
|
|
{ "MPS_CLS_PL_TEST_DATA_H", 0xd030, 0 },
|
|
{ "MPS_CLS_PL_TEST_RES_DATA", 0xd034, 0 },
|
|
{ "Cls_Spare", 28, 4 },
|
|
{ "Cls_Priority", 25, 3 },
|
|
{ "Cls_Replicate", 24, 1 },
|
|
{ "Cls_Index", 15, 9 },
|
|
{ "Cls_VF", 7, 8 },
|
|
{ "Cls_VF_Vld", 6, 1 },
|
|
{ "Cls_PF", 3, 3 },
|
|
{ "Cls_Match", 0, 3 },
|
|
{ "MPS_CLS_PL_TEST_CTL", 0xd038, 0 },
|
|
{ "MPS_CLS_PORT_BMC_CTL", 0xd03c, 0 },
|
|
{ "MPS_CLS_MATCH_CNT_TCAM", 0xd100, 0 },
|
|
{ "MPS_CLS_MATCH_CNT_HASH", 0xd104, 0 },
|
|
{ "MPS_CLS_MATCH_CNT_BCAST", 0xd108, 0 },
|
|
{ "MPS_CLS_MATCH_CNT_BMC", 0xd10c, 0 },
|
|
{ "MPS_CLS_MATCH_CNT_PROM", 0xd110, 0 },
|
|
{ "MPS_CLS_MATCH_CNT_HPROM", 0xd114, 0 },
|
|
{ "MPS_CLS_MISS_CNT", 0xd118, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd200, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd220, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd240, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd260, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd280, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd2a0, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd2c0, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd2e0, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd204, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd224, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd244, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd264, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd284, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd2a4, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd2c4, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd2e4, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd208, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd228, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd248, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd268, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd288, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd2a8, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd2c8, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd2e8, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd20c, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd22c, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd24c, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd26c, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd28c, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd2ac, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd2cc, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd2ec, 0 },
|
|
{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd210, 0 },
|
|
{ "ClsTrcVlanVld", 31, 1 },
|
|
{ "ClsTrcVlanId", 16, 12 },
|
|
{ "ClsTrcReqPort", 0, 4 },
|
|
{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd230, 0 },
|
|
{ "ClsTrcVlanVld", 31, 1 },
|
|
{ "ClsTrcVlanId", 16, 12 },
|
|
{ "ClsTrcReqPort", 0, 4 },
|
|
{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd250, 0 },
|
|
{ "ClsTrcVlanVld", 31, 1 },
|
|
{ "ClsTrcVlanId", 16, 12 },
|
|
{ "ClsTrcReqPort", 0, 4 },
|
|
{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd270, 0 },
|
|
{ "ClsTrcVlanVld", 31, 1 },
|
|
{ "ClsTrcVlanId", 16, 12 },
|
|
{ "ClsTrcReqPort", 0, 4 },
|
|
{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd290, 0 },
|
|
{ "ClsTrcVlanVld", 31, 1 },
|
|
{ "ClsTrcVlanId", 16, 12 },
|
|
{ "ClsTrcReqPort", 0, 4 },
|
|
{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd2b0, 0 },
|
|
{ "ClsTrcVlanVld", 31, 1 },
|
|
{ "ClsTrcVlanId", 16, 12 },
|
|
{ "ClsTrcReqPort", 0, 4 },
|
|
{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd2d0, 0 },
|
|
{ "ClsTrcVlanVld", 31, 1 },
|
|
{ "ClsTrcVlanId", 16, 12 },
|
|
{ "ClsTrcReqPort", 0, 4 },
|
|
{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd2f0, 0 },
|
|
{ "ClsTrcVlanVld", 31, 1 },
|
|
{ "ClsTrcVlanId", 16, 12 },
|
|
{ "ClsTrcReqPort", 0, 4 },
|
|
{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd214, 0 },
|
|
{ "ClsTrcLkpType", 31, 1 },
|
|
{ "ClsTrcDIPHit", 30, 1 },
|
|
{ "ClsTrcVNI", 0, 24 },
|
|
{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd234, 0 },
|
|
{ "ClsTrcLkpType", 31, 1 },
|
|
{ "ClsTrcDIPHit", 30, 1 },
|
|
{ "ClsTrcVNI", 0, 24 },
|
|
{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd254, 0 },
|
|
{ "ClsTrcLkpType", 31, 1 },
|
|
{ "ClsTrcDIPHit", 30, 1 },
|
|
{ "ClsTrcVNI", 0, 24 },
|
|
{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd274, 0 },
|
|
{ "ClsTrcLkpType", 31, 1 },
|
|
{ "ClsTrcDIPHit", 30, 1 },
|
|
{ "ClsTrcVNI", 0, 24 },
|
|
{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd294, 0 },
|
|
{ "ClsTrcLkpType", 31, 1 },
|
|
{ "ClsTrcDIPHit", 30, 1 },
|
|
{ "ClsTrcVNI", 0, 24 },
|
|
{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd2b4, 0 },
|
|
{ "ClsTrcLkpType", 31, 1 },
|
|
{ "ClsTrcDIPHit", 30, 1 },
|
|
{ "ClsTrcVNI", 0, 24 },
|
|
{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd2d4, 0 },
|
|
{ "ClsTrcLkpType", 31, 1 },
|
|
{ "ClsTrcDIPHit", 30, 1 },
|
|
{ "ClsTrcVNI", 0, 24 },
|
|
{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd2f4, 0 },
|
|
{ "ClsTrcLkpType", 31, 1 },
|
|
{ "ClsTrcDIPHit", 30, 1 },
|
|
{ "ClsTrcVNI", 0, 24 },
|
|
{ "MPS_CLS_RESULT_TRACE", 0xd300, 0 },
|
|
{ "ClsTrcPortNum", 31, 1 },
|
|
{ "ClsTrcPriority", 28, 3 },
|
|
{ "ClsTrcMultiListen", 27, 1 },
|
|
{ "ClsTrcReplicate", 26, 1 },
|
|
{ "ClsTrcPortMap", 24, 2 },
|
|
{ "ClsTrcMatch", 21, 3 },
|
|
{ "ClsTrcIndex", 12, 9 },
|
|
{ "ClsTrcVF_Vld", 11, 1 },
|
|
{ "ClsTrcPF", 3, 8 },
|
|
{ "ClsTrcVF", 0, 3 },
|
|
{ "MPS_CLS_RESULT_TRACE", 0xd304, 0 },
|
|
{ "ClsTrcPortNum", 31, 1 },
|
|
{ "ClsTrcPriority", 28, 3 },
|
|
{ "ClsTrcMultiListen", 27, 1 },
|
|
{ "ClsTrcReplicate", 26, 1 },
|
|
{ "ClsTrcPortMap", 24, 2 },
|
|
{ "ClsTrcMatch", 21, 3 },
|
|
{ "ClsTrcIndex", 12, 9 },
|
|
{ "ClsTrcVF_Vld", 11, 1 },
|
|
{ "ClsTrcPF", 3, 8 },
|
|
{ "ClsTrcVF", 0, 3 },
|
|
{ "MPS_CLS_RESULT_TRACE", 0xd308, 0 },
|
|
{ "ClsTrcPortNum", 31, 1 },
|
|
{ "ClsTrcPriority", 28, 3 },
|
|
{ "ClsTrcMultiListen", 27, 1 },
|
|
{ "ClsTrcReplicate", 26, 1 },
|
|
{ "ClsTrcPortMap", 24, 2 },
|
|
{ "ClsTrcMatch", 21, 3 },
|
|
{ "ClsTrcIndex", 12, 9 },
|
|
{ "ClsTrcVF_Vld", 11, 1 },
|
|
{ "ClsTrcPF", 3, 8 },
|
|
{ "ClsTrcVF", 0, 3 },
|
|
{ "MPS_CLS_RESULT_TRACE", 0xd30c, 0 },
|
|
{ "ClsTrcPortNum", 31, 1 },
|
|
{ "ClsTrcPriority", 28, 3 },
|
|
{ "ClsTrcMultiListen", 27, 1 },
|
|
{ "ClsTrcReplicate", 26, 1 },
|
|
{ "ClsTrcPortMap", 24, 2 },
|
|
{ "ClsTrcMatch", 21, 3 },
|
|
{ "ClsTrcIndex", 12, 9 },
|
|
{ "ClsTrcVF_Vld", 11, 1 },
|
|
{ "ClsTrcPF", 3, 8 },
|
|
{ "ClsTrcVF", 0, 3 },
|
|
{ "MPS_CLS_RESULT_TRACE", 0xd310, 0 },
|
|
{ "ClsTrcPortNum", 31, 1 },
|
|
{ "ClsTrcPriority", 28, 3 },
|
|
{ "ClsTrcMultiListen", 27, 1 },
|
|
{ "ClsTrcReplicate", 26, 1 },
|
|
{ "ClsTrcPortMap", 24, 2 },
|
|
{ "ClsTrcMatch", 21, 3 },
|
|
{ "ClsTrcIndex", 12, 9 },
|
|
{ "ClsTrcVF_Vld", 11, 1 },
|
|
{ "ClsTrcPF", 3, 8 },
|
|
{ "ClsTrcVF", 0, 3 },
|
|
{ "MPS_CLS_RESULT_TRACE", 0xd314, 0 },
|
|
{ "ClsTrcPortNum", 31, 1 },
|
|
{ "ClsTrcPriority", 28, 3 },
|
|
{ "ClsTrcMultiListen", 27, 1 },
|
|
{ "ClsTrcReplicate", 26, 1 },
|
|
{ "ClsTrcPortMap", 24, 2 },
|
|
{ "ClsTrcMatch", 21, 3 },
|
|
{ "ClsTrcIndex", 12, 9 },
|
|
{ "ClsTrcVF_Vld", 11, 1 },
|
|
{ "ClsTrcPF", 3, 8 },
|
|
{ "ClsTrcVF", 0, 3 },
|
|
{ "MPS_CLS_RESULT_TRACE", 0xd318, 0 },
|
|
{ "ClsTrcPortNum", 31, 1 },
|
|
{ "ClsTrcPriority", 28, 3 },
|
|
{ "ClsTrcMultiListen", 27, 1 },
|
|
{ "ClsTrcReplicate", 26, 1 },
|
|
{ "ClsTrcPortMap", 24, 2 },
|
|
{ "ClsTrcMatch", 21, 3 },
|
|
{ "ClsTrcIndex", 12, 9 },
|
|
{ "ClsTrcVF_Vld", 11, 1 },
|
|
{ "ClsTrcPF", 3, 8 },
|
|
{ "ClsTrcVF", 0, 3 },
|
|
{ "MPS_CLS_RESULT_TRACE", 0xd31c, 0 },
|
|
{ "ClsTrcPortNum", 31, 1 },
|
|
{ "ClsTrcPriority", 28, 3 },
|
|
{ "ClsTrcMultiListen", 27, 1 },
|
|
{ "ClsTrcReplicate", 26, 1 },
|
|
{ "ClsTrcPortMap", 24, 2 },
|
|
{ "ClsTrcMatch", 21, 3 },
|
|
{ "ClsTrcIndex", 12, 9 },
|
|
{ "ClsTrcVF_Vld", 11, 1 },
|
|
{ "ClsTrcPF", 3, 8 },
|
|
{ "ClsTrcVF", 0, 3 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfc0, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfc4, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfc8, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfcc, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfd0, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfd4, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfd8, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfdc, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfe0, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_DIPIPV4_ID_TABLE", 0x12000, 0 },
|
|
{ "MPS_CLS_DIPIPV4_ID_TABLE", 0x12008, 0 },
|
|
{ "MPS_CLS_DIPIPV4_ID_TABLE", 0x12010, 0 },
|
|
{ "MPS_CLS_DIPIPV4_ID_TABLE", 0x12018, 0 },
|
|
{ "MPS_CLS_DIPIPV4_MASK_TABLE", 0x12004, 0 },
|
|
{ "MPS_CLS_DIPIPV4_MASK_TABLE", 0x1200c, 0 },
|
|
{ "MPS_CLS_DIPIPV4_MASK_TABLE", 0x12014, 0 },
|
|
{ "MPS_CLS_DIPIPV4_MASK_TABLE", 0x1201c, 0 },
|
|
{ "MPS_CLS_DIPIPV6ID_0_TABLE", 0x12020, 0 },
|
|
{ "MPS_CLS_DIPIPV6ID_0_TABLE", 0x12040, 0 },
|
|
{ "MPS_CLS_DIPIPV6ID_1_TABLE", 0x12024, 0 },
|
|
{ "MPS_CLS_DIPIPV6ID_1_TABLE", 0x12044, 0 },
|
|
{ "MPS_CLS_DIPIPV6ID_2_TABLE", 0x12028, 0 },
|
|
{ "MPS_CLS_DIPIPV6ID_2_TABLE", 0x12048, 0 },
|
|
{ "MPS_CLS_DIPIPV6ID_3_TABLE", 0x1202c, 0 },
|
|
{ "MPS_CLS_DIPIPV6ID_3_TABLE", 0x1204c, 0 },
|
|
{ "MPS_CLS_DIPIPV6MASK_0_TABLE", 0x12030, 0 },
|
|
{ "MPS_CLS_DIPIPV6MASK_0_TABLE", 0x12050, 0 },
|
|
{ "MPS_CLS_DIPIPV6MASK_1_TABLE", 0x12034, 0 },
|
|
{ "MPS_CLS_DIPIPV6MASK_1_TABLE", 0x12054, 0 },
|
|
{ "MPS_CLS_DIPIPV6MASK_2_TABLE", 0x12038, 0 },
|
|
{ "MPS_CLS_DIPIPV6MASK_2_TABLE", 0x12058, 0 },
|
|
{ "MPS_CLS_DIPIPV6MASK_3_TABLE", 0x1203c, 0 },
|
|
{ "MPS_CLS_DIPIPV6MASK_3_TABLE", 0x1205c, 0 },
|
|
{ "MPS_RX_HASH_LKP_TABLE", 0x12060, 0 },
|
|
{ "MPS_RX_HASH_LKP_TABLE", 0x12064, 0 },
|
|
{ "MPS_RX_HASH_LKP_TABLE", 0x12068, 0 },
|
|
{ "MPS_RX_HASH_LKP_TABLE", 0x1206c, 0 },
|
|
{ "MPS_CLS_SRAM_L", 0xe000, 0 },
|
|
{ "DisEncapOuterRplct", 31, 1 },
|
|
{ "DisEncap", 30, 1 },
|
|
{ "MultiListen3", 29, 1 },
|
|
{ "MultiListen2", 28, 1 },
|
|
{ "MultiListen1", 27, 1 },
|
|
{ "MultiListen0", 26, 1 },
|
|
{ "Priority3", 23, 3 },
|
|
{ "Priority2", 20, 3 },
|
|
{ "Priority1", 17, 3 },
|
|
{ "Priority0", 14, 3 },
|
|
{ "Valid", 13, 1 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_CLS_SRAM_L", 0xe008, 0 },
|
|
{ "DisEncapOuterRplct", 31, 1 },
|
|
{ "DisEncap", 30, 1 },
|
|
{ "MultiListen3", 29, 1 },
|
|
{ "MultiListen2", 28, 1 },
|
|
{ "MultiListen1", 27, 1 },
|
|
{ "MultiListen0", 26, 1 },
|
|
{ "Priority3", 23, 3 },
|
|
{ "Priority2", 20, 3 },
|
|
{ "Priority1", 17, 3 },
|
|
{ "Priority0", 14, 3 },
|
|
{ "Valid", 13, 1 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_CLS_SRAM_L", 0xe010, 0 },
|
|
{ "DisEncapOuterRplct", 31, 1 },
|
|
{ "DisEncap", 30, 1 },
|
|
{ "MultiListen3", 29, 1 },
|
|
{ "MultiListen2", 28, 1 },
|
|
{ "MultiListen1", 27, 1 },
|
|
{ "MultiListen0", 26, 1 },
|
|
{ "Priority3", 23, 3 },
|
|
{ "Priority2", 20, 3 },
|
|
{ "Priority1", 17, 3 },
|
|
{ "Priority0", 14, 3 },
|
|
{ "Valid", 13, 1 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_CLS_SRAM_L", 0xe018, 0 },
|
|
{ "DisEncapOuterRplct", 31, 1 },
|
|
{ "DisEncap", 30, 1 },
|
|
{ "MultiListen3", 29, 1 },
|
|
{ "MultiListen2", 28, 1 },
|
|
{ "MultiListen1", 27, 1 },
|
|
{ "MultiListen0", 26, 1 },
|
|
{ "Priority3", 23, 3 },
|
|
{ "Priority2", 20, 3 },
|
|
{ "Priority1", 17, 3 },
|
|
{ "Priority0", 14, 3 },
|
|
{ "Valid", 13, 1 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
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|
|
{ "MPS_CLS_SRAM_L", 0xefe0, 0 },
|
|
{ "DisEncapOuterRplct", 31, 1 },
|
|
{ "DisEncap", 30, 1 },
|
|
{ "MultiListen3", 29, 1 },
|
|
{ "MultiListen2", 28, 1 },
|
|
{ "MultiListen1", 27, 1 },
|
|
{ "MultiListen0", 26, 1 },
|
|
{ "Priority3", 23, 3 },
|
|
{ "Priority2", 20, 3 },
|
|
{ "Priority1", 17, 3 },
|
|
{ "Priority0", 14, 3 },
|
|
{ "Valid", 13, 1 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_CLS_SRAM_L", 0xefe8, 0 },
|
|
{ "DisEncapOuterRplct", 31, 1 },
|
|
{ "DisEncap", 30, 1 },
|
|
{ "MultiListen3", 29, 1 },
|
|
{ "MultiListen2", 28, 1 },
|
|
{ "MultiListen1", 27, 1 },
|
|
{ "MultiListen0", 26, 1 },
|
|
{ "Priority3", 23, 3 },
|
|
{ "Priority2", 20, 3 },
|
|
{ "Priority1", 17, 3 },
|
|
{ "Priority0", 14, 3 },
|
|
{ "Valid", 13, 1 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_CLS_SRAM_L", 0xeff0, 0 },
|
|
{ "DisEncapOuterRplct", 31, 1 },
|
|
{ "DisEncap", 30, 1 },
|
|
{ "MultiListen3", 29, 1 },
|
|
{ "MultiListen2", 28, 1 },
|
|
{ "MultiListen1", 27, 1 },
|
|
{ "MultiListen0", 26, 1 },
|
|
{ "Priority3", 23, 3 },
|
|
{ "Priority2", 20, 3 },
|
|
{ "Priority1", 17, 3 },
|
|
{ "Priority0", 14, 3 },
|
|
{ "Valid", 13, 1 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_CLS_SRAM_L", 0xeff8, 0 },
|
|
{ "DisEncapOuterRplct", 31, 1 },
|
|
{ "DisEncap", 30, 1 },
|
|
{ "MultiListen3", 29, 1 },
|
|
{ "MultiListen2", 28, 1 },
|
|
{ "MultiListen1", 27, 1 },
|
|
{ "MultiListen0", 26, 1 },
|
|
{ "Priority3", 23, 3 },
|
|
{ "Priority2", 20, 3 },
|
|
{ "Priority1", 17, 3 },
|
|
{ "Priority0", 14, 3 },
|
|
{ "Valid", 13, 1 },
|
|
{ "Replicate", 12, 1 },
|
|
{ "PF", 9, 3 },
|
|
{ "VF_Valid", 8, 1 },
|
|
{ "VF", 0, 8 },
|
|
{ "MPS_CLS_SRAM_H", 0xe004, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe00c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe014, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe01c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe024, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe02c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe034, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe03c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe044, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe04c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe054, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe05c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe064, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe06c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe074, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe07c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe084, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe08c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe094, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe09c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0a4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0ac, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0b4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0bc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0c4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0cc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0d4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0dc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0e4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0ec, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0f4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0fc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe104, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe10c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe114, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe11c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe124, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe12c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe134, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe13c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe144, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe14c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe154, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe15c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe164, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe16c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe174, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe17c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe184, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe18c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe194, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe19c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1a4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1ac, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1b4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1bc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1c4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1cc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
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{ "MPS_CLS_SRAM_H", 0xe24c, 0 },
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{ "MPS_CLS_SRAM_H", 0xe254, 0 },
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{ "MacParityMaskSize", 4, 4 },
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{ "MPS_CLS_SRAM_H", 0xe25c, 0 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "MPS_CLS_SRAM_H", 0xe264, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "MPS_CLS_SRAM_H", 0xe26c, 0 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "MPS_CLS_SRAM_H", 0xe274, 0 },
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{ "MacParityMaskSize", 4, 4 },
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{ "MPS_CLS_SRAM_H", 0xe27c, 0 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "MPS_CLS_SRAM_H", 0xe284, 0 },
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{ "MPS_CLS_SRAM_H", 0xe314, 0 },
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{ "MPS_CLS_SRAM_H", 0xe324, 0 },
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{ "MPS_CLS_SRAM_H", 0xe32c, 0 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe334, 0 },
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{ "MacParityMaskSize", 4, 4 },
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{ "MPS_CLS_SRAM_H", 0xe33c, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe344, 0 },
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{ "MacParityMaskSize", 4, 4 },
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{ "MPS_CLS_SRAM_H", 0xe34c, 0 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe354, 0 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe364, 0 },
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{ "MPS_CLS_SRAM_H", 0xe36c, 0 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe374, 0 },
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{ "MPS_CLS_SRAM_H", 0xe37c, 0 },
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{ "MacParityMaskSize", 4, 4 },
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{ "MPS_CLS_SRAM_H", 0xe384, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "MPS_CLS_SRAM_H", 0xe38c, 0 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe394, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParity1", 9, 1 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe39c, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe3a4, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe3ac, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe3b4, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe3bc, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParity1", 9, 1 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe3c4, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe3cc, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe3d4, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe3dc, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParity0", 8, 1 },
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{ "MacParityMaskSize", 4, 4 },
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{ "PortMap", 0, 4 },
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{ "MPS_CLS_SRAM_H", 0xe3e4, 0 },
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{ "MacParity2", 10, 1 },
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{ "MacParity1", 9, 1 },
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{ "MPS_CLS_SRAM_H", 0xe554, 0 },
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|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee64, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee6c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee74, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee7c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee84, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee8c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee94, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee9c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeea4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeeac, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeeb4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeebc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeec4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeecc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeed4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeedc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeee4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeeec, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeef4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeefc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef04, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef0c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef14, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef1c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef24, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef2c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef34, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef3c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef44, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef4c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef54, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef5c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef64, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef6c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef74, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef7c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef84, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef8c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef94, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef9c, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefa4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefac, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefb4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefbc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefc4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefcc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefd4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefdc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefe4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefec, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeff4, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeffc, 0 },
|
|
{ "MacParity2", 10, 1 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_TCAM_DATA0", 0xf000, 0 },
|
|
{ "MPS_CLS_TCAM_DATA1", 0xf004, 0 },
|
|
{ "VIDL", 16, 16 },
|
|
{ "DMACH", 0, 16 },
|
|
{ "MPS_CLS_TCAM_DATA2_CTL", 0xf008, 0 },
|
|
{ "CtlCmdType", 31, 1 },
|
|
{ "CtlReqID", 30, 1 },
|
|
{ "CtlTcamSel", 25, 1 },
|
|
{ "CtlTcamIndex", 17, 8 },
|
|
{ "CtlXYBitSel", 16, 1 },
|
|
{ "DataPortNum", 12, 4 },
|
|
{ "DataLkpType", 10, 2 },
|
|
{ "DataDipHit", 8, 1 },
|
|
{ "DataVIDH2", 7, 1 },
|
|
{ "DataVIDH1", 0, 7 },
|
|
{ "MPS_CLS_TCAM_RDATA0_REQ_ID0", 0xf010, 0 },
|
|
{ "MPS_CLS_TCAM_RDATA1_REQ_ID0", 0xf014, 0 },
|
|
{ "VIDL", 16, 16 },
|
|
{ "DMACH", 0, 16 },
|
|
{ "MPS_CLS_TCAM_RDATA2_REQ_ID0", 0xf018, 0 },
|
|
{ "DataPortNum", 12, 4 },
|
|
{ "DataLkpType", 10, 2 },
|
|
{ "DataDipHit", 8, 1 },
|
|
{ "DataVIDH2", 7, 1 },
|
|
{ "DataVIDH1", 0, 7 },
|
|
{ "MPS_CLS_TCAM_RDATA0_REQ_ID1", 0xf020, 0 },
|
|
{ "MPS_CLS_TCAM_RDATA1_REQ_ID1", 0xf024, 0 },
|
|
{ "VIDL", 16, 16 },
|
|
{ "DMACH", 0, 16 },
|
|
{ "MPS_CLS_TCAM_RDATA2_REQ_ID1", 0xf028, 0 },
|
|
{ "DataPortNum", 12, 4 },
|
|
{ "DataLkpType", 10, 2 },
|
|
{ "DataDipHit", 8, 1 },
|
|
{ "DataVIDH2", 7, 1 },
|
|
{ "DataVIDH1", 0, 7 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_cpl_switch_regs[] = {
|
|
{ "CPL_SWITCH_CNTRL", 0x19040, 0 },
|
|
{ "cpl_pkt_tid", 8, 24 },
|
|
{ "cim_split_enable", 6, 1 },
|
|
{ "cim_truncate_enable", 5, 1 },
|
|
{ "cim_to_up_full_size", 4, 1 },
|
|
{ "cpu_no_enable", 3, 1 },
|
|
{ "switch_table_enable", 2, 1 },
|
|
{ "sge_enable", 1, 1 },
|
|
{ "cim_enable", 0, 1 },
|
|
{ "CPL_SWITCH_TBL_IDX", 0x19044, 0 },
|
|
{ "CPL_SWITCH_TBL_DATA", 0x19048, 0 },
|
|
{ "CPL_SWITCH_ZERO_ERROR", 0x1904c, 0 },
|
|
{ "zero_cmd_ch1", 8, 8 },
|
|
{ "zero_cmd_ch0", 0, 8 },
|
|
{ "CPL_INTR_ENABLE", 0x19050, 0 },
|
|
{ "perr_cpl_128to128_1", 7, 1 },
|
|
{ "perr_cpl_128to128_0", 6, 1 },
|
|
{ "cim_op_map_perr", 5, 1 },
|
|
{ "cim_ovfl_error", 4, 1 },
|
|
{ "tp_framing_error", 3, 1 },
|
|
{ "sge_framing_error", 2, 1 },
|
|
{ "cim_framing_error", 1, 1 },
|
|
{ "zero_switch_error", 0, 1 },
|
|
{ "CPL_INTR_CAUSE", 0x19054, 0 },
|
|
{ "perr_cpl_128to128_1", 7, 1 },
|
|
{ "perr_cpl_128to128_0", 6, 1 },
|
|
{ "cim_op_map_perr", 5, 1 },
|
|
{ "cim_ovfl_error", 4, 1 },
|
|
{ "tp_framing_error", 3, 1 },
|
|
{ "sge_framing_error", 2, 1 },
|
|
{ "cim_framing_error", 1, 1 },
|
|
{ "zero_switch_error", 0, 1 },
|
|
{ "CPL_MAP_TBL_IDX", 0x19058, 0 },
|
|
{ "cim_split_opcode_program", 8, 1 },
|
|
{ "cpl_map_tbl_idx", 0, 8 },
|
|
{ "CPL_MAP_TBL_DATA", 0x1905c, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_smb_regs[] = {
|
|
{ "SMB_GLOBAL_TIME_CFG", 0x19060, 0 },
|
|
{ "MacroCntCfg", 8, 5 },
|
|
{ "MicroCntCfg", 0, 8 },
|
|
{ "SMB_MST_TIMEOUT_CFG", 0x19064, 0 },
|
|
{ "SMB_MST_CTL_CFG", 0x19068, 0 },
|
|
{ "MstFifoDbg", 31, 1 },
|
|
{ "MstFifoDbgClr", 30, 1 },
|
|
{ "MstRxByteCfg", 12, 6 },
|
|
{ "MstTxByteCfg", 6, 6 },
|
|
{ "MstReset", 1, 1 },
|
|
{ "MstCtlEn", 0, 1 },
|
|
{ "SMB_MST_CTL_STS", 0x1906c, 0 },
|
|
{ "MstRxByteCnt", 12, 6 },
|
|
{ "MstTxByteCnt", 6, 6 },
|
|
{ "MstBusySts", 0, 1 },
|
|
{ "SMB_MST_TX_FIFO_RDWR", 0x19070, 0 },
|
|
{ "SMB_MST_RX_FIFO_RDWR", 0x19074, 0 },
|
|
{ "SMB_SLV_TIMEOUT_CFG", 0x19078, 0 },
|
|
{ "SMB_SLV_CTL_CFG", 0x1907c, 0 },
|
|
{ "SlvFifoDbg", 31, 1 },
|
|
{ "SlvFifoDbgClr", 30, 1 },
|
|
{ "SlvCrcOutBitInv", 21, 1 },
|
|
{ "SlvCrcOutBitRev", 20, 1 },
|
|
{ "SlvCrcInBitRev", 19, 1 },
|
|
{ "SlvCrcPreset", 11, 8 },
|
|
{ "SlvAddrCfg", 4, 7 },
|
|
{ "SlvAlrtSet", 2, 1 },
|
|
{ "SlvReset", 1, 1 },
|
|
{ "SlvCtlEn", 0, 1 },
|
|
{ "SMB_SLV_CTL_STS", 0x19080, 0 },
|
|
{ "SlvFifoTxCnt", 12, 6 },
|
|
{ "SlvFifoCnt", 6, 6 },
|
|
{ "SlvAlrtSts", 2, 1 },
|
|
{ "SlvBusySts", 0, 1 },
|
|
{ "SMB_SLV_FIFO_RDWR", 0x19084, 0 },
|
|
{ "SMB_INT_ENABLE", 0x1908c, 0 },
|
|
{ "MstTxFifoParEn", 21, 1 },
|
|
{ "MstRxFifoParEn", 20, 1 },
|
|
{ "SlvFifoParEn", 19, 1 },
|
|
{ "SlvUnExpBusStopEn", 18, 1 },
|
|
{ "SlvUnExpBusStartEn", 17, 1 },
|
|
{ "SlvCommandCodeInvEn", 16, 1 },
|
|
{ "SlvByteCntErrEn", 15, 1 },
|
|
{ "SlvUnExpAckMstEn", 14, 1 },
|
|
{ "SlvUnExpNackMstEn", 13, 1 },
|
|
{ "SlvNoBusStopEn", 12, 1 },
|
|
{ "SlvNoRepStartEn", 11, 1 },
|
|
{ "SlvRxAddrIntEn", 10, 1 },
|
|
{ "SlvRxPecErrIntEn", 9, 1 },
|
|
{ "SlvPrepToArpIntEn", 8, 1 },
|
|
{ "SlvTimeOutIntEn", 7, 1 },
|
|
{ "SlvErrIntEn", 6, 1 },
|
|
{ "SlvDoneIntEn", 5, 1 },
|
|
{ "SlvRxRdyIntEn", 4, 1 },
|
|
{ "MstTimeOutIntEn", 3, 1 },
|
|
{ "MstNAckIntEn", 2, 1 },
|
|
{ "MstLostArbIntEn", 1, 1 },
|
|
{ "MstDoneIntEn", 0, 1 },
|
|
{ "SMB_INT_CAUSE", 0x19090, 0 },
|
|
{ "MstTxFifoParInt", 21, 1 },
|
|
{ "MstRxFifoParInt", 20, 1 },
|
|
{ "SlvFifoParInt", 19, 1 },
|
|
{ "SlvUnExpBusStopInt", 18, 1 },
|
|
{ "SlvUnExpBusStartInt", 17, 1 },
|
|
{ "SlvCommandCodeInvInt", 16, 1 },
|
|
{ "SlvByteCntErrInt", 15, 1 },
|
|
{ "SlvUnExpAckMstInt", 14, 1 },
|
|
{ "SlvUnExpNackMstInt", 13, 1 },
|
|
{ "SlvNoBusStopInt", 12, 1 },
|
|
{ "SlvNoRepStartInt", 11, 1 },
|
|
{ "SlvRxAddrInt", 10, 1 },
|
|
{ "SlvRxPecErrInt", 9, 1 },
|
|
{ "SlvPrepToArpInt", 8, 1 },
|
|
{ "SlvTimeOutInt", 7, 1 },
|
|
{ "SlvErrInt", 6, 1 },
|
|
{ "SlvDoneInt", 5, 1 },
|
|
{ "SlvRxRdyInt", 4, 1 },
|
|
{ "MstTimeOutInt", 3, 1 },
|
|
{ "MstNAckInt", 2, 1 },
|
|
{ "MstLostArbInt", 1, 1 },
|
|
{ "MstDoneInt", 0, 1 },
|
|
{ "SMB_DEBUG_DATA", 0x19094, 0 },
|
|
{ "DebugDataH", 16, 16 },
|
|
{ "DebugDataL", 0, 16 },
|
|
{ "SMB_PERR_EN", 0x19098, 0 },
|
|
{ "MstTxFifo", 21, 1 },
|
|
{ "MstRxFifo", 19, 1 },
|
|
{ "SlvFifo", 18, 1 },
|
|
{ "MstTxFifoPerrEn", 2, 1 },
|
|
{ "MstRxFifoPerrEn", 1, 1 },
|
|
{ "SlvFifoPerrEn", 0, 1 },
|
|
{ "SMB_PERR_INJ", 0x1909c, 0 },
|
|
{ "MstTxInjDataErr", 3, 1 },
|
|
{ "MstRxInjDataErr", 2, 1 },
|
|
{ "SlvInjDataErr", 1, 1 },
|
|
{ "FifoInjDataErrEn", 0, 1 },
|
|
{ "SMB_SLV_ARP_CTL", 0x190a0, 0 },
|
|
{ "ArpCommandCode", 2, 8 },
|
|
{ "ArpAddrRes", 1, 1 },
|
|
{ "ArpAddrVal", 0, 1 },
|
|
{ "SMB_ARP_UDID0", 0x190a4, 0 },
|
|
{ "SMB_ARP_UDID1", 0x190a8, 0 },
|
|
{ "SubsystemVendorID", 16, 16 },
|
|
{ "SubsystemDeviceID", 0, 16 },
|
|
{ "SMB_ARP_UDID2", 0x190ac, 0 },
|
|
{ "DeviceID", 16, 16 },
|
|
{ "Interface", 0, 16 },
|
|
{ "SMB_ARP_UDID3", 0x190b0, 0 },
|
|
{ "DeviceCap", 24, 8 },
|
|
{ "VersionID", 16, 8 },
|
|
{ "VendorID", 0, 16 },
|
|
{ "SMB_SLV_AUX_ADDR0", 0x190b4, 0 },
|
|
{ "AuxAddr0Val", 6, 1 },
|
|
{ "AuxAddr0", 0, 6 },
|
|
{ "SMB_SLV_AUX_ADDR1", 0x190b8, 0 },
|
|
{ "AuxAddr1Val", 6, 1 },
|
|
{ "AuxAddr1", 0, 6 },
|
|
{ "SMB_SLV_AUX_ADDR2", 0x190bc, 0 },
|
|
{ "AuxAddr2Val", 6, 1 },
|
|
{ "AuxAddr2", 0, 6 },
|
|
{ "SMB_SLV_AUX_ADDR3", 0x190c0, 0 },
|
|
{ "AuxAddr3Val", 6, 1 },
|
|
{ "AuxAddr3", 0, 6 },
|
|
{ "SMB_COMMAND_CODE0", 0x190c4, 0 },
|
|
{ "SMB_COMMAND_CODE1", 0x190c8, 0 },
|
|
{ "SMB_COMMAND_CODE2", 0x190cc, 0 },
|
|
{ "SMB_COMMAND_CODE3", 0x190d0, 0 },
|
|
{ "SMB_COMMAND_CODE4", 0x190d4, 0 },
|
|
{ "SMB_COMMAND_CODE5", 0x190d8, 0 },
|
|
{ "SMB_COMMAND_CODE6", 0x190dc, 0 },
|
|
{ "SMB_COMMAND_CODE7", 0x190e0, 0 },
|
|
{ "SMB_MICRO_CNT_CLK_CFG", 0x190e4, 0 },
|
|
{ "MacroCntClkCfg", 8, 5 },
|
|
{ "MicroCntClkCfg", 0, 8 },
|
|
{ "SMB_CTL_STATUS", 0x190e8, 0 },
|
|
{ "MstBusBusy", 2, 1 },
|
|
{ "SlvBusBusy", 1, 1 },
|
|
{ "BusBusy", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_i2cm_regs[] = {
|
|
{ "I2CM_CFG", 0x190f0, 0 },
|
|
{ "I2CM_DATA", 0x190f4, 0 },
|
|
{ "I2CM_OP", 0x190f8, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Ack", 30, 1 },
|
|
{ "Cont", 1, 1 },
|
|
{ "Op", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_mi_regs[] = {
|
|
{ "MI_CFG", 0x19100, 0 },
|
|
{ "T4_St", 14, 1 },
|
|
{ "ClkDiv", 5, 8 },
|
|
{ "St", 3, 2 },
|
|
{ "PreEn", 2, 1 },
|
|
{ "MDIInv", 1, 1 },
|
|
{ "MDIO_1P2V_Sel", 0, 1 },
|
|
{ "MI_ADDR", 0x19104, 0 },
|
|
{ "PhyAddr", 5, 5 },
|
|
{ "RegAddr", 0, 5 },
|
|
{ "MI_DATA", 0x19108, 0 },
|
|
{ "MI_OP", 0x1910c, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "St", 3, 2 },
|
|
{ "Inc", 2, 1 },
|
|
{ "Op", 0, 2 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_uart_regs[] = {
|
|
{ "UART_CONFIG", 0x19110, 0 },
|
|
{ "StopBits", 22, 2 },
|
|
{ "Parity", 20, 2 },
|
|
{ "DataBits", 16, 4 },
|
|
{ "ClkDiv", 0, 12 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_pmu_regs[] = {
|
|
{ "PMU_PART_CG_PWRMODE", 0x19120, 0 },
|
|
{ "PL_DIS_PRTY_CHK", 20, 1 },
|
|
{ "SGE_Part_CGEn", 19, 1 },
|
|
{ "PDP_Part_CGEn", 18, 1 },
|
|
{ "TP_Part_CGEn", 17, 1 },
|
|
{ "EDC0_Part_CGEn", 16, 1 },
|
|
{ "EDC1_Part_CGEn", 15, 1 },
|
|
{ "LE_Part_CGEn", 14, 1 },
|
|
{ "MA_Part_CGEn", 13, 1 },
|
|
{ "PCIE_Part_CGEn", 10, 1 },
|
|
{ "InitPowerMode", 0, 2 },
|
|
{ "PMU_SLEEPMODE_WAKEUP", 0x19124, 0 },
|
|
{ "GlobalDeepSleepEn", 6, 1 },
|
|
{ "HWWakeUpEn", 5, 1 },
|
|
{ "Port3SleepMode", 4, 1 },
|
|
{ "Port2SleepMode", 3, 1 },
|
|
{ "Port1SleepMode", 2, 1 },
|
|
{ "Port0SleepMode", 1, 1 },
|
|
{ "WakeUp", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_ulp_rx_regs[] = {
|
|
{ "ULP_RX_CTL", 0x19150, 0 },
|
|
{ "PCMD1Threshold", 24, 8 },
|
|
{ "PCMD0Threshold", 16, 8 },
|
|
{ "disable_0B_STAG_ERR", 14, 1 },
|
|
{ "RDMA_0b_wr_opcode", 10, 4 },
|
|
{ "RDMA_0b_wr_pass", 9, 1 },
|
|
{ "STAG_RQE", 8, 1 },
|
|
{ "RDMA_State_En", 7, 1 },
|
|
{ "Crc1_En", 6, 1 },
|
|
{ "RDMA_0b_wr_cqe", 5, 1 },
|
|
{ "PCIE_Atrb_En", 4, 1 },
|
|
{ "RDMA_permissive_mode", 3, 1 },
|
|
{ "PagePodME", 2, 1 },
|
|
{ "IscsiTagTcb", 1, 1 },
|
|
{ "TddpTagTcb", 0, 1 },
|
|
{ "ULP_RX_INT_ENABLE", 0x19154, 0 },
|
|
{ "SE_CNT_MISMATCH_1", 26, 1 },
|
|
{ "SE_CNT_MISMATCH_0", 25, 1 },
|
|
{ "ENABLE_CTX_1", 24, 1 },
|
|
{ "ENABLE_CTX_0", 23, 1 },
|
|
{ "ENABLE_FF", 22, 1 },
|
|
{ "ENABLE_APF_1", 21, 1 },
|
|
{ "ENABLE_APF_0", 20, 1 },
|
|
{ "ENABLE_AF_1", 19, 1 },
|
|
{ "ENABLE_AF_0", 18, 1 },
|
|
{ "ENABLE_DDPDF_1", 17, 1 },
|
|
{ "ENABLE_DDPMF_1", 16, 1 },
|
|
{ "ENABLE_MEMRF_1", 15, 1 },
|
|
{ "ENABLE_PRSDF_1", 14, 1 },
|
|
{ "ENABLE_DDPDF_0", 13, 1 },
|
|
{ "ENABLE_DDPMF_0", 12, 1 },
|
|
{ "ENABLE_MEMRF_0", 11, 1 },
|
|
{ "ENABLE_PRSDF_0", 10, 1 },
|
|
{ "ENABLE_PCMDF_1", 9, 1 },
|
|
{ "ENABLE_TPTCF_1", 8, 1 },
|
|
{ "ENABLE_DDPCF_1", 7, 1 },
|
|
{ "ENABLE_MPARF_1", 6, 1 },
|
|
{ "ENABLE_MPARC_1", 5, 1 },
|
|
{ "ENABLE_PCMDF_0", 4, 1 },
|
|
{ "ENABLE_TPTCF_0", 3, 1 },
|
|
{ "ENABLE_DDPCF_0", 2, 1 },
|
|
{ "ENABLE_MPARF_0", 1, 1 },
|
|
{ "ENABLE_MPARC_0", 0, 1 },
|
|
{ "ULP_RX_INT_CAUSE", 0x19158, 0 },
|
|
{ "SE_CNT_MISMATCH_1", 26, 1 },
|
|
{ "SE_CNT_MISMATCH_0", 25, 1 },
|
|
{ "CAUSE_CTX_1", 24, 1 },
|
|
{ "CAUSE_CTX_0", 23, 1 },
|
|
{ "CAUSE_FF", 22, 1 },
|
|
{ "CAUSE_APF_1", 21, 1 },
|
|
{ "CAUSE_APF_0", 20, 1 },
|
|
{ "CAUSE_AF_1", 19, 1 },
|
|
{ "CAUSE_AF_0", 18, 1 },
|
|
{ "CAUSE_DDPDF_1", 17, 1 },
|
|
{ "CAUSE_DDPMF_1", 16, 1 },
|
|
{ "CAUSE_MEMRF_1", 15, 1 },
|
|
{ "CAUSE_PRSDF_1", 14, 1 },
|
|
{ "CAUSE_DDPDF_0", 13, 1 },
|
|
{ "CAUSE_DDPMF_0", 12, 1 },
|
|
{ "CAUSE_MEMRF_0", 11, 1 },
|
|
{ "CAUSE_PRSDF_0", 10, 1 },
|
|
{ "CAUSE_PCMDF_1", 9, 1 },
|
|
{ "CAUSE_TPTCF_1", 8, 1 },
|
|
{ "CAUSE_DDPCF_1", 7, 1 },
|
|
{ "CAUSE_MPARF_1", 6, 1 },
|
|
{ "CAUSE_MPARC_1", 5, 1 },
|
|
{ "CAUSE_PCMDF_0", 4, 1 },
|
|
{ "CAUSE_TPTCF_0", 3, 1 },
|
|
{ "CAUSE_DDPCF_0", 2, 1 },
|
|
{ "CAUSE_MPARF_0", 1, 1 },
|
|
{ "CAUSE_MPARC_0", 0, 1 },
|
|
{ "ULP_RX_ISCSI_LLIMIT", 0x1915c, 0 },
|
|
{ "IscsiLlimit", 6, 26 },
|
|
{ "ULP_RX_ISCSI_ULIMIT", 0x19160, 0 },
|
|
{ "IscsiUlimit", 6, 26 },
|
|
{ "ULP_RX_ISCSI_TAGMASK", 0x19164, 0 },
|
|
{ "IscsiTagMask", 6, 26 },
|
|
{ "ULP_RX_ISCSI_PSZ", 0x19168, 0 },
|
|
{ "Hpz3", 24, 4 },
|
|
{ "Hpz2", 16, 4 },
|
|
{ "Hpz1", 8, 4 },
|
|
{ "Hpz0", 0, 4 },
|
|
{ "ULP_RX_TDDP_LLIMIT", 0x1916c, 0 },
|
|
{ "TddpLlimit", 6, 26 },
|
|
{ "ULP_RX_TDDP_ULIMIT", 0x19170, 0 },
|
|
{ "TddpUlimit", 6, 26 },
|
|
{ "ULP_RX_TDDP_TAGMASK", 0x19174, 0 },
|
|
{ "TddpTagMask", 6, 26 },
|
|
{ "ULP_RX_TDDP_PSZ", 0x19178, 0 },
|
|
{ "Hpz3", 24, 4 },
|
|
{ "Hpz2", 16, 4 },
|
|
{ "Hpz1", 8, 4 },
|
|
{ "Hpz0", 0, 4 },
|
|
{ "ULP_RX_STAG_LLIMIT", 0x1917c, 0 },
|
|
{ "ULP_RX_STAG_ULIMIT", 0x19180, 0 },
|
|
{ "ULP_RX_RQ_LLIMIT", 0x19184, 0 },
|
|
{ "ULP_RX_RQ_ULIMIT", 0x19188, 0 },
|
|
{ "ULP_RX_PBL_LLIMIT", 0x1918c, 0 },
|
|
{ "ULP_RX_PBL_ULIMIT", 0x19190, 0 },
|
|
{ "ULP_RX_CTX_BASE", 0x19194, 0 },
|
|
{ "ULP_RX_PERR_ENABLE", 0x1919c, 0 },
|
|
{ "PERR_SE_CNT_MISMATCH_1", 26, 1 },
|
|
{ "PERR_SE_CNT_MISMATCH_0", 25, 1 },
|
|
{ "PERR_ENABLE_CTX_1", 24, 1 },
|
|
{ "PERR_ENABLE_CTX_0", 23, 1 },
|
|
{ "PERR_ENABLE_FF", 22, 1 },
|
|
{ "PERR_ENABLE_APF_1", 21, 1 },
|
|
{ "PERR_ENABLE_APF_0", 20, 1 },
|
|
{ "PERR_ENABLE_AF_1", 19, 1 },
|
|
{ "PERR_ENABLE_AF_0", 18, 1 },
|
|
{ "PERR_ENABLE_DDPDF_1", 17, 1 },
|
|
{ "PERR_ENABLE_DDPMF_1", 16, 1 },
|
|
{ "PERR_ENABLE_MEMRF_1", 15, 1 },
|
|
{ "PERR_ENABLE_PRSDF_1", 14, 1 },
|
|
{ "PERR_ENABLE_DDPDF_0", 13, 1 },
|
|
{ "PERR_ENABLE_DDPMF_0", 12, 1 },
|
|
{ "PERR_ENABLE_MEMRF_0", 11, 1 },
|
|
{ "PERR_ENABLE_PRSDF_0", 10, 1 },
|
|
{ "PERR_ENABLE_PCMDF_1", 9, 1 },
|
|
{ "PERR_ENABLE_TPTCF_1", 8, 1 },
|
|
{ "PERR_ENABLE_DDPCF_1", 7, 1 },
|
|
{ "PERR_ENABLE_MPARF_1", 6, 1 },
|
|
{ "PERR_ENABLE_MPARC_1", 5, 1 },
|
|
{ "PERR_ENABLE_PCMDF_0", 4, 1 },
|
|
{ "PERR_ENABLE_TPTCF_0", 3, 1 },
|
|
{ "PERR_ENABLE_DDPCF_0", 2, 1 },
|
|
{ "PERR_ENABLE_MPARF_0", 1, 1 },
|
|
{ "PERR_ENABLE_MPARC_0", 0, 1 },
|
|
{ "ULP_RX_PERR_INJECT", 0x191a0, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "ULP_RX_RQUDP_LLIMIT", 0x191a4, 0 },
|
|
{ "ULP_RX_RQUDP_ULIMIT", 0x191a8, 0 },
|
|
{ "ULP_RX_CTX_ACC_CH0", 0x191ac, 0 },
|
|
{ "REQ", 21, 1 },
|
|
{ "WB", 20, 1 },
|
|
{ "TID", 0, 20 },
|
|
{ "ULP_RX_CTX_ACC_CH1", 0x191b0, 0 },
|
|
{ "REQ", 21, 1 },
|
|
{ "WB", 20, 1 },
|
|
{ "TID", 0, 20 },
|
|
{ "ULP_RX_SE_CNT_ERR", 0x191d0, 0 },
|
|
{ "ERR_CH1", 4, 4 },
|
|
{ "ERR_CH0", 0, 4 },
|
|
{ "ULP_RX_SE_CNT_CLR", 0x191d4, 0 },
|
|
{ "CLR_CH0", 4, 4 },
|
|
{ "CLR_CH1", 0, 4 },
|
|
{ "ULP_RX_SE_CNT_CH0", 0x191d8, 0 },
|
|
{ "SOP_CNT_OUT0", 28, 4 },
|
|
{ "EOP_CNT_OUT0", 24, 4 },
|
|
{ "SOP_CNT_AL0", 20, 4 },
|
|
{ "EOP_CNT_AL0", 16, 4 },
|
|
{ "SOP_CNT_MR0", 12, 4 },
|
|
{ "EOP_CNT_MR0", 8, 4 },
|
|
{ "SOP_CNT_IN0", 4, 4 },
|
|
{ "EOP_CNT_IN0", 0, 4 },
|
|
{ "ULP_RX_SE_CNT_CH1", 0x191dc, 0 },
|
|
{ "SOP_CNT_OUT1", 28, 4 },
|
|
{ "EOP_CNT_OUT1", 24, 4 },
|
|
{ "SOP_CNT_AL1", 20, 4 },
|
|
{ "EOP_CNT_AL1", 16, 4 },
|
|
{ "SOP_CNT_MR1", 12, 4 },
|
|
{ "EOP_CNT_MR1", 8, 4 },
|
|
{ "SOP_CNT_IN1", 4, 4 },
|
|
{ "EOP_CNT_IN1", 0, 4 },
|
|
{ "ULP_RX_DBG_CTL", 0x191e0, 0 },
|
|
{ "EN_DBG_H", 17, 1 },
|
|
{ "EN_DBG_L", 16, 1 },
|
|
{ "SEL_H", 8, 8 },
|
|
{ "SEL_L", 0, 8 },
|
|
{ "ULP_RX_DBG_DATAH", 0x191e4, 0 },
|
|
{ "ULP_RX_DBG_DATAL", 0x191e8, 0 },
|
|
{ "ULP_RX_LA_CHNL", 0x19238, 0 },
|
|
{ "ULP_RX_LA_CTL", 0x1923c, 0 },
|
|
{ "ULP_RX_LA_RDPTR", 0x19240, 0 },
|
|
{ "ULP_RX_LA_RDDATA", 0x19244, 0 },
|
|
{ "ULP_RX_LA_WRPTR", 0x19248, 0 },
|
|
{ "ULP_RX_LA_RESERVED", 0x1924c, 0 },
|
|
{ "ULP_RX_CQE_GEN_EN", 0x19250, 0 },
|
|
{ "Termimate_msg", 1, 1 },
|
|
{ "Terminate_with_err", 0, 1 },
|
|
{ "ULP_RX_ATOMIC_OPCODES", 0x19254, 0 },
|
|
{ "atomic_req_qno", 22, 2 },
|
|
{ "atomic_rsp_qno", 20, 2 },
|
|
{ "immediate_qno", 18, 2 },
|
|
{ "immediate_with_se_qno", 16, 2 },
|
|
{ "atomic_wr_opcode", 12, 4 },
|
|
{ "atomic_rd_opcode", 8, 4 },
|
|
{ "immediate_opcode", 4, 4 },
|
|
{ "immediate_with_se_opcode", 0, 4 },
|
|
{ "ULP_RX_T10_CRC_ENDIAN_SWITCHING", 0x19258, 0 },
|
|
{ "ULP_RX_MISC_FEATURE_ENABLE", 0x1925c, 0 },
|
|
{ "iscsi_dcrc_error_cmp_en", 25, 1 },
|
|
{ "IscsiTagPI", 24, 1 },
|
|
{ "ddp_version_1", 22, 2 },
|
|
{ "ddp_version_0", 20, 2 },
|
|
{ "rdma_version_1", 18, 2 },
|
|
{ "rdma_version_0", 16, 2 },
|
|
{ "pbl_bound_check_w_pglen", 15, 1 },
|
|
{ "zbyte_fix_disable", 14, 1 },
|
|
{ "t10_offset_update_en", 13, 1 },
|
|
{ "ulp_insert_pi", 12, 1 },
|
|
{ "pdu_dpi", 11, 1 },
|
|
{ "iscsi_eff_offset_en", 10, 1 },
|
|
{ "iscsi_all_cmp_mode", 9, 1 },
|
|
{ "iscsi_enable_hdr_cmd", 8, 1 },
|
|
{ "iscsi_force_cmp_mode", 7, 1 },
|
|
{ "iscsi_enable_cmp_mode", 6, 1 },
|
|
{ "pio_rdma_send_rqe", 5, 1 },
|
|
{ "terminate_status_en", 4, 1 },
|
|
{ "multiple_pref_enable", 3, 1 },
|
|
{ "umudp_pbl_pref_enable", 2, 1 },
|
|
{ "rdma_pbl_pref_en", 1, 1 },
|
|
{ "sdc_crc_prot_en", 0, 1 },
|
|
{ "ULP_RX_CH0_CGEN", 0x19260, 0 },
|
|
{ "BYPASS_CGEN", 7, 1 },
|
|
{ "TDDP_CGEN", 6, 1 },
|
|
{ "ISCSI_CGEN", 5, 1 },
|
|
{ "RDMA_CGEN", 4, 1 },
|
|
{ "CHANNEL_CGEN", 3, 1 },
|
|
{ "All_DataPath_CGEN", 2, 1 },
|
|
{ "T10Diff_DataPath_CGEN", 1, 1 },
|
|
{ "Rdma_DataPath_CGEN", 0, 1 },
|
|
{ "ULP_RX_CH1_CGEN", 0x19264, 0 },
|
|
{ "BYPASS_CGEN", 7, 1 },
|
|
{ "TDDP_CGEN", 6, 1 },
|
|
{ "ISCSI_CGEN", 5, 1 },
|
|
{ "RDMA_CGEN", 4, 1 },
|
|
{ "CHANNEL_CGEN", 3, 1 },
|
|
{ "All_DataPath_CGEN", 2, 1 },
|
|
{ "T10Diff_DataPath_CGEN", 1, 1 },
|
|
{ "Rdma_DataPath_CGEN", 0, 1 },
|
|
{ "ULP_RX_RFE_DISABLE", 0x19268, 0 },
|
|
{ "ULP_RX_INT_ENABLE_2", 0x1926c, 0 },
|
|
{ "ULPRX2MA_IntfPerr", 8, 1 },
|
|
{ "ALN_SDC_ERR_1", 7, 1 },
|
|
{ "ALN_SDC_ERR_0", 6, 1 },
|
|
{ "PF_UNTAGGED_TPT_1", 5, 1 },
|
|
{ "PF_UNTAGGED_TPT_0", 4, 1 },
|
|
{ "PF_PBL_1", 3, 1 },
|
|
{ "PF_PBL_0", 2, 1 },
|
|
{ "DDP_HINT_1", 1, 1 },
|
|
{ "DDP_HINT_0", 0, 1 },
|
|
{ "ULP_RX_INT_CAUSE_2", 0x19270, 0 },
|
|
{ "ULPRX2MA_IntfPerr", 8, 1 },
|
|
{ "ALN_SDC_ERR_1", 7, 1 },
|
|
{ "ALN_SDC_ERR_0", 6, 1 },
|
|
{ "PF_UNTAGGED_TPT_1", 5, 1 },
|
|
{ "PF_UNTAGGED_TPT_0", 4, 1 },
|
|
{ "PF_PBL_1", 3, 1 },
|
|
{ "PF_PBL_0", 2, 1 },
|
|
{ "DDP_HINT_1", 1, 1 },
|
|
{ "DDP_HINT_0", 0, 1 },
|
|
{ "ULP_RX_PERR_ENABLE_2", 0x19274, 0 },
|
|
{ "ENABLE_ULPRX2MA_IntfPerr", 8, 1 },
|
|
{ "ENABLE_ALN_SDC_ERR_1", 7, 1 },
|
|
{ "ENABLE_ALN_SDC_ERR_0", 6, 1 },
|
|
{ "ENABLE_PF_UNTAGGED_TPT_1", 5, 1 },
|
|
{ "ENABLE_PF_UNTAGGED_TPT_0", 4, 1 },
|
|
{ "ENABLE_PF_PBL_1", 3, 1 },
|
|
{ "ENABLE_PF_PBL_0", 2, 1 },
|
|
{ "ENABLE_DDP_HINT_1", 1, 1 },
|
|
{ "ENABLE_DDP_HINT_0", 0, 1 },
|
|
{ "ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT", 0x19278, 0 },
|
|
{ "ULP_RX_ATOMIC_LEN", 0x1927c, 0 },
|
|
{ "atomic_rpl_len", 16, 8 },
|
|
{ "atomic_req_len", 8, 8 },
|
|
{ "atomic_immediate_len", 0, 8 },
|
|
{ "ULP_RX_CGEN_GLOBAL", 0x19280, 0 },
|
|
{ "ULP_RX_CTX_SKIP_MA_REQ", 0x19284, 0 },
|
|
{ "clear_ctx_err_cnt1", 3, 1 },
|
|
{ "clear_ctx_err_cnt0", 2, 1 },
|
|
{ "skip_ma_req_en1", 1, 1 },
|
|
{ "skip_ma_req_en0", 0, 1 },
|
|
{ "ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID", 0x19288, 0 },
|
|
{ "ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID", 0x1928c, 0 },
|
|
{ "ULP_RX_MSN_CHECK_ENABLE", 0x19290, 0 },
|
|
{ "Rd_or_Term_msn_check_enable", 2, 1 },
|
|
{ "atomic_op_msn_check_enable", 1, 1 },
|
|
{ "send_msn_check_enable", 0, 1 },
|
|
{ "ULP_RX_TLS_PP_LLIMIT", 0x192a4, 0 },
|
|
{ "TlsPpLlimit", 6, 26 },
|
|
{ "ULP_RX_TLS_PP_ULIMIT", 0x192a8, 0 },
|
|
{ "TlsPpUlimit", 6, 26 },
|
|
{ "ULP_RX_TLS_KEY_LLIMIT", 0x192ac, 0 },
|
|
{ "TlsKeyLlimit", 8, 24 },
|
|
{ "ULP_RX_TLS_KEY_ULIMIT", 0x192b0, 0 },
|
|
{ "TlsKeyUlimit", 8, 24 },
|
|
{ "ULP_RX_TLS_CTL", 0x192bc, 0 },
|
|
{ "TlsPerrEn", 4, 1 },
|
|
{ "TlsDisableIFuse", 2, 1 },
|
|
{ "TlsDisableCFuse", 1, 1 },
|
|
{ "TlsDisable", 0, 1 },
|
|
{ "ULP_RX_TLS_IND_CMD", 0x19348, 0 },
|
|
{ "ULP_RX_TLS_IND_DATA", 0x1934c, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_sf_regs[] = {
|
|
{ "SF_DATA", 0x193f8, 0 },
|
|
{ "SF_OP", 0x193fc, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Lock", 4, 1 },
|
|
{ "Cont", 3, 1 },
|
|
{ "ByteCnt", 1, 2 },
|
|
{ "Op", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_pl_regs[] = {
|
|
{ "PL_PF_INT_CAUSE", 0x1e3c0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1e3c4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1e3c8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1e7c0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1e7c4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1e7c8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1ebc0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1ebc4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1ebc8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1efc0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1efc4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1efc8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1f3c0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1f3c4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1f3c8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1f7c0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1f7c4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1f7c8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1fbc0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1fbc4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1fbc8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1ffc0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1ffc4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1ffc8, 0 },
|
|
{ "PL_WHOAMI", 0x19400, 0 },
|
|
{ "PortxMap", 24, 3 },
|
|
{ "SourceBus", 16, 2 },
|
|
{ "SourcePF", 9, 3 },
|
|
{ "IsVF", 8, 1 },
|
|
{ "VFID", 0, 8 },
|
|
{ "PL_PERR_CAUSE", 0x19404, 0 },
|
|
{ "UART", 28, 1 },
|
|
{ "ULP_TX", 27, 1 },
|
|
{ "SGE", 26, 1 },
|
|
{ "HMA", 25, 1 },
|
|
{ "CPL_SWITCH", 24, 1 },
|
|
{ "ULP_RX", 23, 1 },
|
|
{ "PM_RX", 22, 1 },
|
|
{ "PM_TX", 21, 1 },
|
|
{ "MA", 20, 1 },
|
|
{ "TP", 19, 1 },
|
|
{ "LE", 18, 1 },
|
|
{ "EDC1", 17, 1 },
|
|
{ "EDC0", 16, 1 },
|
|
{ "MC0", 15, 1 },
|
|
{ "PCIE", 14, 1 },
|
|
{ "PMU", 13, 1 },
|
|
{ "MAC", 9, 1 },
|
|
{ "SMB", 8, 1 },
|
|
{ "SF", 7, 1 },
|
|
{ "PL", 6, 1 },
|
|
{ "NCSI", 5, 1 },
|
|
{ "MPS", 4, 1 },
|
|
{ "MI", 3, 1 },
|
|
{ "DBG", 2, 1 },
|
|
{ "I2CM", 1, 1 },
|
|
{ "CIM", 0, 1 },
|
|
{ "PL_PERR_ENABLE", 0x19408, 0 },
|
|
{ "UART", 28, 1 },
|
|
{ "ULP_TX", 27, 1 },
|
|
{ "SGE", 26, 1 },
|
|
{ "HMA", 25, 1 },
|
|
{ "CPL_SWITCH", 24, 1 },
|
|
{ "ULP_RX", 23, 1 },
|
|
{ "PM_RX", 22, 1 },
|
|
{ "PM_TX", 21, 1 },
|
|
{ "MA", 20, 1 },
|
|
{ "TP", 19, 1 },
|
|
{ "LE", 18, 1 },
|
|
{ "EDC1", 17, 1 },
|
|
{ "EDC0", 16, 1 },
|
|
{ "MC0", 15, 1 },
|
|
{ "PCIE", 14, 1 },
|
|
{ "PMU", 13, 1 },
|
|
{ "MAC", 9, 1 },
|
|
{ "SMB", 8, 1 },
|
|
{ "SF", 7, 1 },
|
|
{ "PL", 6, 1 },
|
|
{ "NCSI", 5, 1 },
|
|
{ "MPS", 4, 1 },
|
|
{ "MI", 3, 1 },
|
|
{ "DBG", 2, 1 },
|
|
{ "I2CM", 1, 1 },
|
|
{ "CIM", 0, 1 },
|
|
{ "PL_INT_CAUSE", 0x1940c, 0 },
|
|
{ "FLR", 30, 1 },
|
|
{ "SW_CIM", 29, 1 },
|
|
{ "UART", 28, 1 },
|
|
{ "ULP_TX", 27, 1 },
|
|
{ "SGE", 26, 1 },
|
|
{ "HMA", 25, 1 },
|
|
{ "CPL_SWITCH", 24, 1 },
|
|
{ "ULP_RX", 23, 1 },
|
|
{ "PM_RX", 22, 1 },
|
|
{ "PM_TX", 21, 1 },
|
|
{ "MA", 20, 1 },
|
|
{ "TP", 19, 1 },
|
|
{ "LE", 18, 1 },
|
|
{ "EDC1", 17, 1 },
|
|
{ "EDC0", 16, 1 },
|
|
{ "MC0", 15, 1 },
|
|
{ "PCIE", 14, 1 },
|
|
{ "PMU", 13, 1 },
|
|
{ "MAC1", 10, 1 },
|
|
{ "MAC0", 9, 1 },
|
|
{ "SMB", 8, 1 },
|
|
{ "SF", 7, 1 },
|
|
{ "PL", 6, 1 },
|
|
{ "NCSI", 5, 1 },
|
|
{ "MPS", 4, 1 },
|
|
{ "MI", 3, 1 },
|
|
{ "DBG", 2, 1 },
|
|
{ "I2CM", 1, 1 },
|
|
{ "CIM", 0, 1 },
|
|
{ "PL_INT_ENABLE", 0x19410, 0 },
|
|
{ "FLR", 30, 1 },
|
|
{ "SW_CIM", 29, 1 },
|
|
{ "UART", 28, 1 },
|
|
{ "ULP_TX", 27, 1 },
|
|
{ "SGE", 26, 1 },
|
|
{ "HMA", 25, 1 },
|
|
{ "CPL_SWITCH", 24, 1 },
|
|
{ "ULP_RX", 23, 1 },
|
|
{ "PM_RX", 22, 1 },
|
|
{ "PM_TX", 21, 1 },
|
|
{ "MA", 20, 1 },
|
|
{ "TP", 19, 1 },
|
|
{ "LE", 18, 1 },
|
|
{ "EDC1", 17, 1 },
|
|
{ "EDC0", 16, 1 },
|
|
{ "MC0", 15, 1 },
|
|
{ "PCIE", 14, 1 },
|
|
{ "PMU", 13, 1 },
|
|
{ "MAC1", 10, 1 },
|
|
{ "MAC0", 9, 1 },
|
|
{ "SMB", 8, 1 },
|
|
{ "SF", 7, 1 },
|
|
{ "PL", 6, 1 },
|
|
{ "NCSI", 5, 1 },
|
|
{ "MPS", 4, 1 },
|
|
{ "MI", 3, 1 },
|
|
{ "DBG", 2, 1 },
|
|
{ "I2CM", 1, 1 },
|
|
{ "CIM", 0, 1 },
|
|
{ "PL_INT_MAP0", 0x19414, 0 },
|
|
{ "MapNCSI", 16, 9 },
|
|
{ "MapDefault", 0, 9 },
|
|
{ "PL_INT_MAP1", 0x19418, 0 },
|
|
{ "MapMAC1", 16, 9 },
|
|
{ "MapMAC0", 0, 9 },
|
|
{ "PL_INT_MAP3", 0x19420, 0 },
|
|
{ "MapMI", 16, 9 },
|
|
{ "MapSMB", 0, 9 },
|
|
{ "PL_INT_MAP4", 0x19424, 0 },
|
|
{ "MapDBG", 16, 9 },
|
|
{ "MapI2CM", 0, 9 },
|
|
{ "PL_RST", 0x19428, 0 },
|
|
{ "AutoPciePause", 4, 1 },
|
|
{ "FatalPerrEn", 3, 1 },
|
|
{ "SWIntCIM", 2, 1 },
|
|
{ "PIORst", 1, 1 },
|
|
{ "PIORstMode", 0, 1 },
|
|
{ "PL_PL_INT_CAUSE", 0x19430, 0 },
|
|
{ "PL_BusPerr", 6, 1 },
|
|
{ "FatalPerr", 4, 1 },
|
|
{ "InvalidAccess", 3, 1 },
|
|
{ "Timeout", 2, 1 },
|
|
{ "PLErr", 1, 1 },
|
|
{ "PL_PL_INT_ENABLE", 0x19434, 0 },
|
|
{ "PL_BusPerr", 6, 1 },
|
|
{ "FatalPerr", 4, 1 },
|
|
{ "InvalidAccess", 3, 1 },
|
|
{ "Timeout", 2, 1 },
|
|
{ "PLErr", 1, 1 },
|
|
{ "PL_PL_PERR_ENABLE", 0x19438, 0 },
|
|
{ "PL_BusPerr", 6, 1 },
|
|
{ "PL_REV", 0x1943c, 0 },
|
|
{ "ChipID", 4, 4 },
|
|
{ "Rev", 0, 4 },
|
|
{ "PL_PCIE_LINK", 0x19440, 0 },
|
|
{ "LN0_AESTAT", 27, 3 },
|
|
{ "LN0_AECMD", 24, 3 },
|
|
{ "StateCfgInitF", 16, 8 },
|
|
{ "StateCfgInit", 12, 4 },
|
|
{ "PHY_STATUS", 10, 1 },
|
|
{ "SPEED", 8, 2 },
|
|
{ "PERstTimeout", 7, 1 },
|
|
{ "LTSSMEnable", 6, 1 },
|
|
{ "LTSSM", 0, 6 },
|
|
{ "PL_PCIE_CTL_STAT", 0x19444, 0 },
|
|
{ "Status", 16, 16 },
|
|
{ "Control", 0, 16 },
|
|
{ "PL_SEMAPHORE_CTL", 0x1944c, 0 },
|
|
{ "LockStatus", 16, 8 },
|
|
{ "OwnerOverride", 8, 1 },
|
|
{ "EnablePF", 0, 8 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19450, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19454, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19458, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x1945c, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19460, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19464, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19468, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x1946c, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_PORTX_MAP", 0x19474, 0 },
|
|
{ "MAP7", 28, 3 },
|
|
{ "MAP6", 24, 3 },
|
|
{ "MAP5", 20, 3 },
|
|
{ "MAP4", 16, 3 },
|
|
{ "MAP3", 12, 3 },
|
|
{ "MAP2", 8, 3 },
|
|
{ "MAP1", 4, 3 },
|
|
{ "MAP0", 0, 3 },
|
|
{ "PL_VF_SLICE_L", 0x19490, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x19498, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194a0, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194a8, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194b0, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194b8, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194c0, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194c8, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x19494, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x1949c, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194a4, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194ac, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194b4, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194bc, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194c4, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194cc, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_TIMEOUT_CTL", 0x194f0, 0 },
|
|
{ "PerrCapture", 16, 1 },
|
|
{ "Timeout", 0, 16 },
|
|
{ "PL_TIMEOUT_STATUS0", 0x194f4, 0 },
|
|
{ "Addr", 2, 28 },
|
|
{ "PL_TIMEOUT_STATUS1", 0x194f8, 0 },
|
|
{ "Valid", 31, 1 },
|
|
{ "ValidPerr", 30, 1 },
|
|
{ "Write", 22, 1 },
|
|
{ "Bus", 20, 2 },
|
|
{ "PF", 16, 3 },
|
|
{ "VFID", 0, 9 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_le_regs[] = {
|
|
{ "LE_DB_ID", 0x19c00, 0 },
|
|
{ "LE_DB_CONFIG", 0x19c04, 0 },
|
|
{ "CHK_FUL_TUP_ZERO", 27, 1 },
|
|
{ "PRI_HASH", 26, 1 },
|
|
{ "EXTN_HASH_IPV4", 25, 1 },
|
|
{ "PROTOCOLMASKEN", 24, 1 },
|
|
{ "SRVRSRAMEN", 22, 1 },
|
|
{ "HASHEN", 20, 1 },
|
|
{ "ASLIPCOMPEN_IPV4", 18, 1 },
|
|
{ "BUILD", 16, 1 },
|
|
{ "IGNR_TUP_ZERO", 9, 1 },
|
|
{ "IGNR_LIP_ZERO", 8, 1 },
|
|
{ "CLCAM_INIT_BUSY", 7, 1 },
|
|
{ "CLCAM_INIT", 6, 1 },
|
|
{ "MTCAM_INIT_BUSY", 5, 1 },
|
|
{ "MTCAM_INIT", 4, 1 },
|
|
{ "REGION_EN", 0, 4 },
|
|
{ "LE_DB_EXEC_CTRL", 0x19c08, 0 },
|
|
{ "TPDB_IF_PAUSE_ACK", 10, 1 },
|
|
{ "TPDB_IF_PAUSE_REQ", 9, 1 },
|
|
{ "ERRSTOP_EN", 8, 1 },
|
|
{ "CMDLIMIT", 0, 8 },
|
|
{ "LE_DB_PS_CTRL", 0x19c0c, 0 },
|
|
{ "SRAMDEEPSLEEP_STAT", 11, 1 },
|
|
{ "CLTCAMDEEPSLEEP_STAT", 10, 1 },
|
|
{ "TCAMDEEPSLEEP_STAT", 9, 1 },
|
|
{ "SRAMDEEPSLEEP", 8, 1 },
|
|
{ "CLTCAMDEEPSLEEP", 7, 1 },
|
|
{ "TCAMDEEPSLEEP", 6, 1 },
|
|
{ "SRVRAMCLKOFF", 5, 1 },
|
|
{ "HASHCLKOFF", 4, 1 },
|
|
{ "LE_DB_ACTIVE_TABLE_START_INDEX", 0x19c10, 0 },
|
|
{ "LE_DB_NORM_FILT_TABLE_START_INDEX", 0x19c14, 0 },
|
|
{ "LE_DB_SRVR_START_INDEX", 0x19c18, 0 },
|
|
{ "LE_DB_HPRI_FILT_TABLE_START_INDEX", 0x19c1c, 0 },
|
|
{ "LE_DB_ACT_CNT_IPV4", 0x19c20, 0 },
|
|
{ "LE_DB_ACT_CNT_IPV6", 0x19c24, 0 },
|
|
{ "LE_DB_ACT_CNT_IPV4_TCAM", 0x19c94, 0 },
|
|
{ "LE_DB_ACT_CNT_IPV6_TCAM", 0x19c98, 0 },
|
|
{ "LE_DB_REQ_RSP_CNT", 0x19ce4, 0 },
|
|
{ "RspCnt", 16, 16 },
|
|
{ "ReqCnt", 0, 16 },
|
|
{ "LE_HASH_COLLISION", 0x19fc4, 0 },
|
|
{ "LE_GLOBAL_COLLISION", 0x19fc8, 0 },
|
|
{ "LE_DB_HASH_CONFIG", 0x19c28, 0 },
|
|
{ "NUMHASHBKT", 20, 5 },
|
|
{ "HASHTBLSIZE", 3, 17 },
|
|
{ "LE_DB_MIN_NUM_ACTV_TCAM_ENTRIES", 0x19c2c, 0 },
|
|
{ "LE_DB_MAX_NUM_HASH_ENTRIES", 0x19c70, 0 },
|
|
{ "LE_DB_RSP_CODE_0", 0x19c74, 0 },
|
|
{ "SUCCESS", 25, 5 },
|
|
{ "TCAM_ACTV_SUCC", 20, 5 },
|
|
{ "HASH_ACTV_SUCC", 15, 5 },
|
|
{ "TCAM_SRVR_HIT", 10, 5 },
|
|
{ "SRAM_SRVR_HIT", 5, 5 },
|
|
{ "TCAM_ACTV_HIT", 0, 5 },
|
|
{ "LE_DB_RSP_CODE_1", 0x19c78, 0 },
|
|
{ "HASH_ACTV_HIT", 25, 5 },
|
|
{ "MISS", 20, 5 },
|
|
{ "NORM_FILT_HIT", 15, 5 },
|
|
{ "HPRI_FILT_HIT", 10, 5 },
|
|
{ "ACTV_OPEN_ERR", 5, 5 },
|
|
{ "ACTV_FULL_ERR", 0, 5 },
|
|
{ "LE_DB_RSP_CODE_2", 0x19c7c, 0 },
|
|
{ "SRCH_RGN_HIT", 25, 5 },
|
|
{ "CLIP_FAIL", 20, 5 },
|
|
{ "LIP_ZERO_ERR", 15, 5 },
|
|
{ "UNKNOWN_CMD", 10, 5 },
|
|
{ "CMD_TID_ERR", 5, 5 },
|
|
{ "INTERNAL_ERR", 0, 5 },
|
|
{ "LE_DB_RSP_CODE_3", 0x19c80, 0 },
|
|
{ "SRAM_SRVR_HIT_ACTF", 25, 5 },
|
|
{ "TCAM_SRVR_HIT_ACTF", 20, 5 },
|
|
{ "INVLDRD", 15, 5 },
|
|
{ "TUPLZERO", 10, 5 },
|
|
{ "LE_DB_HASH_TBL_BASE_ADDR", 0x19c30, 0 },
|
|
{ "HASHTBLADDR", 4, 28 },
|
|
{ "LE_TCAM_SIZE", 0x19c34, 0 },
|
|
{ "LE_DB_INT_ENABLE", 0x19c38, 0 },
|
|
{ "ClipSubErr", 29, 1 },
|
|
{ "ClCamFifoerr", 28, 1 },
|
|
{ "HashTblMemCrcErr", 27, 1 },
|
|
{ "CTcamInvldEnt", 26, 1 },
|
|
{ "TcamInvldEnt", 25, 1 },
|
|
{ "TotCntErr", 24, 1 },
|
|
{ "CmdPrsrIntErr", 23, 1 },
|
|
{ "CmdTidErr", 22, 1 },
|
|
{ "ActRgnFull", 21, 1 },
|
|
{ "ActCntIPv6Tzero", 20, 1 },
|
|
{ "ActCntIPv4Tzero", 19, 1 },
|
|
{ "ActCntIPv6zero", 18, 1 },
|
|
{ "ActCntIPv4zero", 17, 1 },
|
|
{ "MaifwrIntPerr", 16, 1 },
|
|
{ "HashTblMemAccErr", 15, 1 },
|
|
{ "TcamCrcErr", 14, 1 },
|
|
{ "TcamIntPerr", 13, 1 },
|
|
{ "VfSramPerr", 12, 1 },
|
|
{ "SrvSramPerr", 11, 1 },
|
|
{ "SsramIntPerr", 10, 1 },
|
|
{ "ClCamIntPerr", 9, 1 },
|
|
{ "ClCamCrcParErr", 8, 1 },
|
|
{ "HashTblAccFail", 7, 1 },
|
|
{ "TcamAccFail", 6, 1 },
|
|
{ "SrvSramAccFail", 5, 1 },
|
|
{ "ClipTcamAccFail", 4, 1 },
|
|
{ "UnknownCmd", 3, 1 },
|
|
{ "LIP0", 2, 1 },
|
|
{ "LIPMiss", 1, 1 },
|
|
{ "PipelineErr", 0, 1 },
|
|
{ "LE_DB_INT_CAUSE", 0x19c3c, 0 },
|
|
{ "ClipSubErr", 29, 1 },
|
|
{ "ClCamFifoerr", 28, 1 },
|
|
{ "HashTblMemCrcErr", 27, 1 },
|
|
{ "CTcamInvldEnt", 26, 1 },
|
|
{ "TcamInvldEnt", 25, 1 },
|
|
{ "TotCntErr", 24, 1 },
|
|
{ "CmdPrsrIntErr", 23, 1 },
|
|
{ "CmdTidErr", 22, 1 },
|
|
{ "ActRgnFull", 21, 1 },
|
|
{ "ActCntIPv6Tzero", 20, 1 },
|
|
{ "ActCntIPv4Tzero", 19, 1 },
|
|
{ "ActCntIPv6zero", 18, 1 },
|
|
{ "ActCntIPv4zero", 17, 1 },
|
|
{ "MaifwrIntPerr", 16, 1 },
|
|
{ "HashTblMemAccErr", 15, 1 },
|
|
{ "TcamCrcErr", 14, 1 },
|
|
{ "TcamIntPerr", 13, 1 },
|
|
{ "VfSramPerr", 12, 1 },
|
|
{ "SrvSramPerr", 11, 1 },
|
|
{ "SsramIntPerr", 10, 1 },
|
|
{ "ClCamIntPerr", 9, 1 },
|
|
{ "ClCamCrcParErr", 8, 1 },
|
|
{ "HashTblAccFail", 7, 1 },
|
|
{ "TcamAccFail", 6, 1 },
|
|
{ "SrvSramAccFail", 5, 1 },
|
|
{ "ClipTcamAccFail", 4, 1 },
|
|
{ "UnknownCmd", 3, 1 },
|
|
{ "LIP0", 2, 1 },
|
|
{ "LIPMiss", 1, 1 },
|
|
{ "PipelineErr", 0, 1 },
|
|
{ "LE_PERR_ENABLE", 0x19cf8, 0 },
|
|
{ "BkChkPeriod", 22, 10 },
|
|
{ "TcamBkChkEn", 21, 1 },
|
|
{ "MaifwrIntPerr", 16, 1 },
|
|
{ "HashTblMemAccErr", 15, 1 },
|
|
{ "TcamCrcErr", 14, 1 },
|
|
{ "TcamIntPerr", 13, 1 },
|
|
{ "VfSramPerr", 12, 1 },
|
|
{ "SrvSramPerr", 11, 1 },
|
|
{ "SsramIntPerr", 10, 1 },
|
|
{ "ClCamIntPerr", 9, 1 },
|
|
{ "ClCamCrcParErr", 8, 1 },
|
|
{ "HashTblAccFail", 7, 1 },
|
|
{ "TcamAccFail", 6, 1 },
|
|
{ "SrvSramAccFail", 5, 1 },
|
|
{ "ClipTcamAccFail", 4, 1 },
|
|
{ "ClCamFifoerr", 2, 1 },
|
|
{ "HashTblMemCrcErr", 1, 1 },
|
|
{ "PipelineErr", 0, 1 },
|
|
{ "LE_DB_ERR_CMD_TID", 0x19c48, 0 },
|
|
{ "ERR_CID", 22, 8 },
|
|
{ "ERR_PROT", 20, 2 },
|
|
{ "ERR_TID", 0, 20 },
|
|
{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c50, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c54, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c58, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c5c, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c60, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c64, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c68, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c6c, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA", 0x19ca0, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA", 0x19ca4, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA", 0x19ca8, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA", 0x19cac, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA", 0x19cb0, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA", 0x19cb4, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA", 0x19cb8, 0 },
|
|
{ "LE_DB_DBG_MATCH_DATA", 0x19cbc, 0 },
|
|
{ "LE_DB_DBG_MATCH_CMD_IDX_MASK", 0x19c40, 0 },
|
|
{ "CMD_CMP_MASK", 20, 5 },
|
|
{ "TID_CMP_MASK", 0, 20 },
|
|
{ "LE_DB_DBG_MATCH_CMD_IDX_DATA", 0x19c44, 0 },
|
|
{ "CMD_CMP", 20, 5 },
|
|
{ "TID_CMP", 0, 20 },
|
|
{ "LE_DB_DBGI_CONFIG", 0x19cf0, 0 },
|
|
{ "DBGICMDRANGE", 22, 3 },
|
|
{ "DBGICMDMSKREAD", 21, 1 },
|
|
{ "DBGICMDSEARCH", 20, 1 },
|
|
{ "DBGICMDREAD", 19, 1 },
|
|
{ "DBGICMDLEARN", 18, 1 },
|
|
{ "DBGICMDWRITE", 17, 1 },
|
|
{ "DBGICMDIPv6", 16, 1 },
|
|
{ "DBGICMDBUSY", 3, 1 },
|
|
{ "DBGICMDSTRT", 2, 1 },
|
|
{ "DBGICMDMODE", 0, 2 },
|
|
{ "LE_DB_DBGI_REQ_CMD", 0x19cf4, 0 },
|
|
{ "DBGICMD", 20, 4 },
|
|
{ "DBGITID", 0, 20 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d00, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d04, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d08, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d0c, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d10, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d14, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d18, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d1c, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d20, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d24, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d28, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d50, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d54, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d58, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d5c, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d60, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d64, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d68, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d6c, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d70, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d74, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d78, 0 },
|
|
{ "LE_DB_DBGI_RSP_STATUS", 0x19d94, 0 },
|
|
{ "DBGIRspTid", 12, 20 },
|
|
{ "DBGIRspMsg", 8, 4 },
|
|
{ "DBGIRspLearn", 2, 1 },
|
|
{ "DBGIRspHit", 1, 1 },
|
|
{ "DBGIRspValid", 0, 1 },
|
|
{ "LE_DBG_SEL", 0x19d98, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19da0, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19da4, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19da8, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dac, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19db0, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19db4, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19db8, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dbc, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dc0, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dc4, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dc8, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dcc, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dd0, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dd4, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dd8, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19ddc, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19de0, 0 },
|
|
{ "LE_DB_TCAM_TID_BASE", 0x19df0, 0 },
|
|
{ "LE_DB_CLCAM_TID_BASE", 0x19df4, 0 },
|
|
{ "LE_DB_HASH_TID_BASE", 0x19df8, 0 },
|
|
{ "LE_DB_SSRAM_TID_BASE", 0x19dfc, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e00, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e04, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e08, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e0c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e10, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e50, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e54, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e58, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e5c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e60, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e64, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e68, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e6c, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19ea0, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19ea4, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19ea8, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19eac, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19eb0, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19eb4, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19eb8, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19ebc, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ec4, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ec8, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ecc, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ed0, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ed4, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ed8, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19edc, 0 },
|
|
{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ee0, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_TUP_IPV4", 0x19ee4, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_TUP_IPV4", 0x19ee8, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_TUP_IPV4", 0x19eec, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_FLT_IPV4", 0x19ef0, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_FLT_IPV4", 0x19ef4, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f04, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f08, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f0c, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f10, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f14, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f18, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f1c, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f20, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f24, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_FLT_IPV6", 0x19f28, 0 },
|
|
{ "LE_DB_PSV_FILTER_MASK_FLT_IPV6", 0x19f2c, 0 },
|
|
{ "LE_DB_SRVR_SRAM_CONFIG", 0x19f34, 0 },
|
|
{ "PRI_HFILT", 4, 1 },
|
|
{ "PRI_SRVR", 3, 1 },
|
|
{ "PRI_FILT", 2, 1 },
|
|
{ "SRVRINITBUSY", 1, 1 },
|
|
{ "SRVRINIT", 0, 1 },
|
|
{ "LE_DB_SRVR_VF_SRCH_TABLE_CTRL", 0x19f38, 0 },
|
|
{ "VFLUTBUSY", 10, 1 },
|
|
{ "VFLUTSTART", 9, 1 },
|
|
{ "RDWR", 8, 1 },
|
|
{ "VFINDEX", 0, 8 },
|
|
{ "LE_DB_SRVR_VF_SRCH_TABLE_DATA", 0x19f3c, 0 },
|
|
{ "SRCHHADDR", 12, 12 },
|
|
{ "SRCHLADDR", 0, 12 },
|
|
{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f40, 0 },
|
|
{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f44, 0 },
|
|
{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f48, 0 },
|
|
{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f4c, 0 },
|
|
{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f50, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f90, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f94, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f98, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f9c, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa0, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa4, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa8, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fac, 0 },
|
|
{ "LE_DEBUG_LA_CONFIG", 0x19fd0, 0 },
|
|
{ "LE_REQ_DEBUG_LA_DATA", 0x19fd4, 0 },
|
|
{ "LE_REQ_DEBUG_LA_WRPTR", 0x19fd8, 0 },
|
|
{ "LE_RSP_DEBUG_LA_DATA", 0x19fdc, 0 },
|
|
{ "LE_RSP_DEBUG_LA_WRPTR", 0x19fe0, 0 },
|
|
{ "LE_DEBUG_LA_SEL_DATA", 0x19fe4, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_ncsi_regs[] = {
|
|
{ "NCSI_PORT_CFGREG", 0x1a000, 0 },
|
|
{ "WireEn", 28, 4 },
|
|
{ "strp_crc", 24, 4 },
|
|
{ "rx_halt", 22, 1 },
|
|
{ "flush_rx_fifo", 21, 1 },
|
|
{ "hw_arb_en", 20, 1 },
|
|
{ "soft_pkg_sel", 19, 1 },
|
|
{ "err_discard_en", 18, 1 },
|
|
{ "max_pkt_size", 4, 14 },
|
|
{ "rx_byte_swap", 3, 1 },
|
|
{ "tx_byte_swap", 2, 1 },
|
|
{ "NCSI_RST_CTRL", 0x1a004, 0 },
|
|
{ "mac_ref_rst", 2, 1 },
|
|
{ "mac_rx_rst", 1, 1 },
|
|
{ "mac_tx_rst", 0, 1 },
|
|
{ "NCSI_CH0_SADDR_LOW", 0x1a010, 0 },
|
|
{ "NCSI_CH0_SADDR_HIGH", 0x1a014, 0 },
|
|
{ "CHO_SADDR_EN", 31, 1 },
|
|
{ "CH0_SADDR_HIGH", 0, 16 },
|
|
{ "NCSI_CH1_SADDR_LOW", 0x1a018, 0 },
|
|
{ "NCSI_CH1_SADDR_HIGH", 0x1a01c, 0 },
|
|
{ "CH1_SADDR_EN", 31, 1 },
|
|
{ "CH1_SADDR_HIGH", 0, 16 },
|
|
{ "NCSI_CH2_SADDR_LOW", 0x1a020, 0 },
|
|
{ "NCSI_CH2_SADDR_HIGH", 0x1a024, 0 },
|
|
{ "CH2_SADDR_EN", 31, 1 },
|
|
{ "CH2_SADDR_HIGH", 0, 16 },
|
|
{ "NCSI_CH3_SADDR_LOW", 0x1a028, 0 },
|
|
{ "NCSI_CH3_SADDR_HIGH", 0x1a02c, 0 },
|
|
{ "CH3_SADDR_EN", 31, 1 },
|
|
{ "CH3_SADDR_HIGH", 0, 16 },
|
|
{ "NCSI_WORK_REQHDR_0", 0x1a030, 0 },
|
|
{ "NCSI_WORK_REQHDR_1", 0x1a034, 0 },
|
|
{ "NCSI_WORK_REQHDR_2", 0x1a038, 0 },
|
|
{ "NCSI_WORK_REQHDR_3", 0x1a03c, 0 },
|
|
{ "NCSI_MPS_HDR_LO", 0x1a040, 0 },
|
|
{ "NCSI_MPS_HDR_HI", 0x1a044, 0 },
|
|
{ "NCSI_CTL", 0x1a048, 0 },
|
|
{ "STRIP_OVLAN", 3, 1 },
|
|
{ "bmc_drop_non_bc", 2, 1 },
|
|
{ "bmc_rx_fwd_all", 1, 1 },
|
|
{ "FWD_BMC", 0, 1 },
|
|
{ "NCSI_NCSI_ETYPE", 0x1a04c, 0 },
|
|
{ "NCSI_RX_FIFO_CNT", 0x1a050, 0 },
|
|
{ "NCSI_RX_ERR_CNT", 0x1a054, 0 },
|
|
{ "NCSI_RX_OF_CNT", 0x1a058, 0 },
|
|
{ "NCSI_RX_MS_CNT", 0x1a05c, 0 },
|
|
{ "NCSI_RX_IE_CNT", 0x1a060, 0 },
|
|
{ "NCSI_MPS_DEMUX_CNT", 0x1a064, 0 },
|
|
{ "MPS2CIM_CNT", 16, 9 },
|
|
{ "MPS2BMC_CNT", 0, 9 },
|
|
{ "NCSI_CIM_DEMUX_CNT", 0x1a068, 0 },
|
|
{ "CIM2MPS_CNT", 16, 9 },
|
|
{ "CIM2BMC_CNT", 0, 9 },
|
|
{ "NCSI_TX_FIFO_CNT", 0x1a06c, 0 },
|
|
{ "NCSI_SE_CNT_CTL", 0x1a0b0, 0 },
|
|
{ "NCSI_SE_CNT_MPS", 0x1a0b4, 0 },
|
|
{ "NCSI_SE_CNT_CIM", 0x1a0b8, 0 },
|
|
{ "NCSI_BUS_DEBUG", 0x1a0bc, 0 },
|
|
{ "NCSI_LA_RDPTR", 0x1a0c0, 0 },
|
|
{ "NCSI_LA_RDDATA", 0x1a0c4, 0 },
|
|
{ "NCSI_LA_WRPTR", 0x1a0c8, 0 },
|
|
{ "NCSI_LA_RESERVED", 0x1a0cc, 0 },
|
|
{ "NCSI_LA_CTL", 0x1a0d0, 0 },
|
|
{ "NCSI_INT_ENABLE", 0x1a0d4, 0 },
|
|
{ "CIM_DM_prty_err", 8, 1 },
|
|
{ "MPS_DM_prty_err", 7, 1 },
|
|
{ "token", 6, 1 },
|
|
{ "arb_done", 5, 1 },
|
|
{ "arb_started", 4, 1 },
|
|
{ "WOL", 3, 1 },
|
|
{ "MACInt", 2, 1 },
|
|
{ "TXFIFO_prty_err", 1, 1 },
|
|
{ "RXFIFO_prty_err", 0, 1 },
|
|
{ "NCSI_INT_CAUSE", 0x1a0d8, 0 },
|
|
{ "CIM_DM_prty_err", 8, 1 },
|
|
{ "MPS_DM_prty_err", 7, 1 },
|
|
{ "token", 6, 1 },
|
|
{ "arb_done", 5, 1 },
|
|
{ "arb_started", 4, 1 },
|
|
{ "WOL", 3, 1 },
|
|
{ "MACInt", 2, 1 },
|
|
{ "TXFIFO_prty_err", 1, 1 },
|
|
{ "RXFIFO_prty_err", 0, 1 },
|
|
{ "NCSI_STATUS", 0x1a0dc, 0 },
|
|
{ "Master", 1, 1 },
|
|
{ "arb_status", 0, 1 },
|
|
{ "NCSI_PAUSE_CTRL", 0x1a0e0, 0 },
|
|
{ "NCSI_PAUSE_TIMEOUT", 0x1a0e4, 0 },
|
|
{ "NCSI_PAUSE_WM", 0x1a0ec, 0 },
|
|
{ "PauseHWM", 16, 11 },
|
|
{ "PauseLWM", 0, 11 },
|
|
{ "NCSI_DEBUG", 0x1a0f0, 0 },
|
|
{ "TxFIFO_empty", 4, 1 },
|
|
{ "TxFIFO_full", 3, 1 },
|
|
{ "PKG_ID", 0, 3 },
|
|
{ "NCSI_PERR_INJECT", 0x1a0f4, 0 },
|
|
{ "MemSel", 1, 1 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "NCSI_PERR_ENABLE", 0x1a0f8, 0 },
|
|
{ "CIM_DM_prty_err", 8, 1 },
|
|
{ "MPS_DM_prty_err", 7, 1 },
|
|
{ "TXFIFO_prty_err", 1, 1 },
|
|
{ "RXFIFO_prty_err", 0, 1 },
|
|
{ "NCSI_MACB_NETWORK_CTRL", 0x1a100, 0 },
|
|
{ "TxSndZeroPause", 12, 1 },
|
|
{ "TxSndPause", 11, 1 },
|
|
{ "TxStop", 10, 1 },
|
|
{ "TxStart", 9, 1 },
|
|
{ "BackPress", 8, 1 },
|
|
{ "StatWrEn", 7, 1 },
|
|
{ "IncrStat", 6, 1 },
|
|
{ "ClearStat", 5, 1 },
|
|
{ "EnMgmtPort", 4, 1 },
|
|
{ "TxEn", 3, 1 },
|
|
{ "RxEn", 2, 1 },
|
|
{ "LoopLocal", 1, 1 },
|
|
{ "LoopPHY", 0, 1 },
|
|
{ "NCSI_MACB_NETWORK_CFG", 0x1a104, 0 },
|
|
{ "PClkDiv128", 22, 1 },
|
|
{ "CopyPause", 21, 1 },
|
|
{ "NonStdPreOK", 20, 1 },
|
|
{ "NoFCS", 19, 1 },
|
|
{ "RxEnHalfDup", 18, 1 },
|
|
{ "NoCopyFCS", 17, 1 },
|
|
{ "LenChkEn", 16, 1 },
|
|
{ "RxBufOffset", 14, 2 },
|
|
{ "PauseEn", 13, 1 },
|
|
{ "RetryTest", 12, 1 },
|
|
{ "PClkDiv", 10, 2 },
|
|
{ "ExtClass", 9, 1 },
|
|
{ "En1536Frame", 8, 1 },
|
|
{ "UCastHashEn", 7, 1 },
|
|
{ "MCastHashEn", 6, 1 },
|
|
{ "RxBCastDis", 5, 1 },
|
|
{ "CopyAllFrames", 4, 1 },
|
|
{ "JumboEn", 3, 1 },
|
|
{ "SerEn", 2, 1 },
|
|
{ "FullDuplex", 1, 1 },
|
|
{ "Speed", 0, 1 },
|
|
{ "NCSI_MACB_NETWORK_STATUS", 0x1a108, 0 },
|
|
{ "PHYMgmtStatus", 2, 1 },
|
|
{ "MDIStatus", 1, 1 },
|
|
{ "LinkStatus", 0, 1 },
|
|
{ "NCSI_MACB_TX_STATUS", 0x1a114, 0 },
|
|
{ "UnderrunErr", 6, 1 },
|
|
{ "TxComplete", 5, 1 },
|
|
{ "BufferExhausted", 4, 1 },
|
|
{ "TxProgress", 3, 1 },
|
|
{ "RetryLimit", 2, 1 },
|
|
{ "ColEvent", 1, 1 },
|
|
{ "UsedBitRead", 0, 1 },
|
|
{ "NCSI_MACB_RX_BUF_QPTR", 0x1a118, 0 },
|
|
{ "RxBufQPtr", 2, 30 },
|
|
{ "NCSI_MACB_TX_BUF_QPTR", 0x1a11c, 0 },
|
|
{ "TxBufQPtr", 2, 30 },
|
|
{ "NCSI_MACB_RX_STATUS", 0x1a120, 0 },
|
|
{ "RxOverrunErr", 2, 1 },
|
|
{ "FrameRcvd", 1, 1 },
|
|
{ "NoRxBuf", 0, 1 },
|
|
{ "NCSI_MACB_INT_STATUS", 0x1a124, 0 },
|
|
{ "PauseTimeZero", 13, 1 },
|
|
{ "PauseRcvd", 12, 1 },
|
|
{ "HRespNotOK", 11, 1 },
|
|
{ "RxOverrun", 10, 1 },
|
|
{ "LinkChange", 9, 1 },
|
|
{ "TxComplete", 7, 1 },
|
|
{ "TxBufErr", 6, 1 },
|
|
{ "RetryLimitErr", 5, 1 },
|
|
{ "TxBufUnderrun", 4, 1 },
|
|
{ "TxUsedBitRead", 3, 1 },
|
|
{ "RxUsedBitRead", 2, 1 },
|
|
{ "RxComplete", 1, 1 },
|
|
{ "MgmtFrameSent", 0, 1 },
|
|
{ "NCSI_MACB_INT_EN", 0x1a128, 0 },
|
|
{ "PauseTimeZero", 13, 1 },
|
|
{ "PauseRcvd", 12, 1 },
|
|
{ "HRespNotOK", 11, 1 },
|
|
{ "RxOverrun", 10, 1 },
|
|
{ "LinkChange", 9, 1 },
|
|
{ "TxComplete", 7, 1 },
|
|
{ "TxBufErr", 6, 1 },
|
|
{ "RetryLimitErr", 5, 1 },
|
|
{ "TxBufUnderrun", 4, 1 },
|
|
{ "TxUsedBitRead", 3, 1 },
|
|
{ "RxUsedBitRead", 2, 1 },
|
|
{ "RxComplete", 1, 1 },
|
|
{ "MgmtFrameSent", 0, 1 },
|
|
{ "NCSI_MACB_INT_DIS", 0x1a12c, 0 },
|
|
{ "PauseTimeZero", 13, 1 },
|
|
{ "PauseRcvd", 12, 1 },
|
|
{ "HRespNotOK", 11, 1 },
|
|
{ "RxOverrun", 10, 1 },
|
|
{ "LinkChange", 9, 1 },
|
|
{ "TxComplete", 7, 1 },
|
|
{ "TxBufErr", 6, 1 },
|
|
{ "RetryLimitErr", 5, 1 },
|
|
{ "TxBufUnderrun", 4, 1 },
|
|
{ "TxUsedBitRead", 3, 1 },
|
|
{ "RxUsedBitRead", 2, 1 },
|
|
{ "RxComplete", 1, 1 },
|
|
{ "MgmtFrameSent", 0, 1 },
|
|
{ "NCSI_MACB_INT_MASK", 0x1a130, 0 },
|
|
{ "PauseTimeZero", 13, 1 },
|
|
{ "PauseRcvd", 12, 1 },
|
|
{ "HRespNotOK", 11, 1 },
|
|
{ "RxOverrun", 10, 1 },
|
|
{ "LinkChange", 9, 1 },
|
|
{ "TxComplete", 7, 1 },
|
|
{ "TxBufErr", 6, 1 },
|
|
{ "RetryLimitErr", 5, 1 },
|
|
{ "TxBufUnderrun", 4, 1 },
|
|
{ "TxUsedBitRead", 3, 1 },
|
|
{ "RxUsedBitRead", 2, 1 },
|
|
{ "RxComplete", 1, 1 },
|
|
{ "MgmtFrameSent", 0, 1 },
|
|
{ "NCSI_MACB_PAUSE_TIME", 0x1a138, 0 },
|
|
{ "NCSI_MACB_PAUSE_FRAMES_RCVD", 0x1a13c, 0 },
|
|
{ "NCSI_MACB_TX_FRAMES_OK", 0x1a140, 0 },
|
|
{ "NCSI_MACB_SINGLE_COL_FRAMES", 0x1a144, 0 },
|
|
{ "NCSI_MACB_MUL_COL_FRAMES", 0x1a148, 0 },
|
|
{ "NCSI_MACB_RX_FRAMES_OK", 0x1a14c, 0 },
|
|
{ "NCSI_MACB_FCS_ERR", 0x1a150, 0 },
|
|
{ "NCSI_MACB_ALIGN_ERR", 0x1a154, 0 },
|
|
{ "NCSI_MACB_DEF_TX_FRAMES", 0x1a158, 0 },
|
|
{ "NCSI_MACB_LATE_COL", 0x1a15c, 0 },
|
|
{ "NCSI_MACB_EXCESSIVE_COL", 0x1a160, 0 },
|
|
{ "NCSI_MACB_TX_UNDERRUN_ERR", 0x1a164, 0 },
|
|
{ "NCSI_MACB_CARRIER_SENSE_ERR", 0x1a168, 0 },
|
|
{ "NCSI_MACB_RX_RESOURCE_ERR", 0x1a16c, 0 },
|
|
{ "NCSI_MACB_RX_OVERRUN_ERR", 0x1a170, 0 },
|
|
{ "NCSI_MACB_RX_SYMBOL_ERR", 0x1a174, 0 },
|
|
{ "NCSI_MACB_RX_OVERSIZE_FRAME", 0x1a178, 0 },
|
|
{ "NCSI_MACB_RX_JABBER_ERR", 0x1a17c, 0 },
|
|
{ "NCSI_MACB_RX_UNDERSIZE_FRAME", 0x1a180, 0 },
|
|
{ "NCSI_MACB_SQE_TEST_ERR", 0x1a184, 0 },
|
|
{ "NCSI_MACB_LENGTH_ERR", 0x1a188, 0 },
|
|
{ "NCSI_MACB_TX_PAUSE_FRAMES", 0x1a18c, 0 },
|
|
{ "NCSI_MACB_HASH_LOW", 0x1a190, 0 },
|
|
{ "NCSI_MACB_HASH_HIGH", 0x1a194, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_1_LOW", 0x1a198, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_1_HIGH", 0x1a19c, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_2_LOW", 0x1a1a0, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_2_HIGH", 0x1a1a4, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_3_LOW", 0x1a1a8, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_3_HIGH", 0x1a1ac, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_4_LOW", 0x1a1b0, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_4_HIGH", 0x1a1b4, 0 },
|
|
{ "NCSI_MACB_TYPE_ID", 0x1a1b8, 0 },
|
|
{ "NCSI_MACB_TX_PAUSE_QUANTUM", 0x1a1bc, 0 },
|
|
{ "NCSI_MACB_USER_IO", 0x1a1c0, 0 },
|
|
{ "UserProgInput", 16, 16 },
|
|
{ "UserProgOutput", 0, 16 },
|
|
{ "NCSI_MACB_WOL_CFG", 0x1a1c4, 0 },
|
|
{ "MCHashEn", 19, 1 },
|
|
{ "Specific1En", 18, 1 },
|
|
{ "ARPEn", 17, 1 },
|
|
{ "MagicPktEn", 16, 1 },
|
|
{ "ARPIPAddr", 0, 16 },
|
|
{ "NCSI_MACB_REV_STATUS", 0x1a1fc, 0 },
|
|
{ "PartRef", 16, 16 },
|
|
{ "DesRev", 0, 16 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_mac_regs[] = {
|
|
{ "MAC_PORT_CFG", 0x30800, 0 },
|
|
{ "MAC_Clk_Sel", 29, 3 },
|
|
{ "Ena_err_rsp", 28, 1 },
|
|
{ "SinkTx", 27, 1 },
|
|
{ "SinkTxOnLinkDown", 26, 1 },
|
|
{ "debug_clr", 25, 1 },
|
|
{ "LoopNoFwd", 24, 1 },
|
|
{ "pll_sel", 23, 1 },
|
|
{ "port_map", 20, 3 },
|
|
{ "Smux_Rx_Loop", 19, 1 },
|
|
{ "Rx_Lane_Swap", 18, 1 },
|
|
{ "Tx_Lane_Swap", 17, 1 },
|
|
{ "Aec_pat_data", 15, 1 },
|
|
{ "Signal_Det", 14, 1 },
|
|
{ "macclk_sel", 13, 1 },
|
|
{ "xgmii_sel", 12, 1 },
|
|
{ "debug_port_sel", 10, 2 },
|
|
{ "SmuxTxSel", 9, 1 },
|
|
{ "SmuxRxSel", 8, 1 },
|
|
{ "Enable_25G", 7, 1 },
|
|
{ "Enable_50G", 6, 1 },
|
|
{ "PortSpeed", 4, 2 },
|
|
{ "Rx_Byte_Swap", 3, 1 },
|
|
{ "Tx_Byte_Swap", 2, 1 },
|
|
{ "debug_tx_rx_sel", 1, 1 },
|
|
{ "Port_Sel", 0, 1 },
|
|
{ "MAC_PORT_RESET_CTRL", 0x30804, 0 },
|
|
{ "TWGDSK_HSSC16B", 31, 1 },
|
|
{ "EEE_RESET", 30, 1 },
|
|
{ "PTP_TIMER", 29, 1 },
|
|
{ "MtipRefReset", 28, 1 },
|
|
{ "MAC100G40G_RESET", 27, 1 },
|
|
{ "MAC10G1G_RESET", 26, 1 },
|
|
{ "MtipRegReset", 25, 1 },
|
|
{ "PCS1G_RESET", 24, 1 },
|
|
{ "AEC3Reset", 23, 1 },
|
|
{ "AEC2Reset", 22, 1 },
|
|
{ "AEC1Reset", 21, 1 },
|
|
{ "AEC0Reset", 20, 1 },
|
|
{ "AET3Reset", 19, 1 },
|
|
{ "AET2Reset", 18, 1 },
|
|
{ "AET1Reset", 17, 1 },
|
|
{ "AET0Reset", 16, 1 },
|
|
{ "PCS10G_RESET", 15, 1 },
|
|
{ "PCS40G_RESET", 14, 1 },
|
|
{ "PCS100G_RESET", 13, 1 },
|
|
{ "TXIF_Reset", 12, 1 },
|
|
{ "RXIF_Reset", 11, 1 },
|
|
{ "AuxExt_Reset", 10, 1 },
|
|
{ "MtipSd3TxRst", 9, 1 },
|
|
{ "MtipSd2TxRst", 8, 1 },
|
|
{ "MtipSd1TxRst", 7, 1 },
|
|
{ "MtipSd0TxRst", 6, 1 },
|
|
{ "MtipSd3RxRst", 5, 1 },
|
|
{ "MtipSd2RxRst", 4, 1 },
|
|
{ "MtipSd1RxRst", 3, 1 },
|
|
{ "WOL_Reset", 2, 1 },
|
|
{ "MtipSd0RxRst", 1, 1 },
|
|
{ "HSS_Reset", 0, 1 },
|
|
{ "MAC_PORT_LED_CFG", 0x30808, 0 },
|
|
{ "Led1_Cfg1", 14, 2 },
|
|
{ "Led0_Cfg1", 12, 2 },
|
|
{ "Led1_tlo", 11, 1 },
|
|
{ "Led1_thi", 10, 1 },
|
|
{ "Led0_tlo", 9, 1 },
|
|
{ "Led0_thi", 8, 1 },
|
|
{ "Led1_Cfg", 5, 3 },
|
|
{ "Led1_Polarity_Inv", 4, 1 },
|
|
{ "Led0_Cfg", 1, 3 },
|
|
{ "Led0_Polarity_Inv", 0, 1 },
|
|
{ "MAC_PORT_LED_COUNTHI", 0x3080c, 0 },
|
|
{ "MAC_PORT_LED_COUNTLO", 0x30810, 0 },
|
|
{ "MAC_PORT_CFG3", 0x30814, 0 },
|
|
{ "REF_Clk_Sel", 30, 2 },
|
|
{ "sgmii_sd_sig_det", 29, 1 },
|
|
{ "sgmii_sgpcs_ena", 28, 1 },
|
|
{ "FPGA_PTP_PORT", 26, 2 },
|
|
{ "FCSDisCtrl", 25, 1 },
|
|
{ "SigDetCtrl", 24, 1 },
|
|
{ "tx_lane", 23, 1 },
|
|
{ "rx_lane", 22, 1 },
|
|
{ "se_clr", 21, 1 },
|
|
{ "an_ena", 17, 4 },
|
|
{ "sd_rx_clk_ena", 13, 4 },
|
|
{ "sd_tx_clk_ena", 9, 4 },
|
|
{ "SGMIISEL", 8, 1 },
|
|
{ "HSSPLLSEL", 4, 4 },
|
|
{ "HSSC16C20SEL", 0, 4 },
|
|
{ "MAC_PORT_CFG2", 0x30818, 0 },
|
|
{ "Rx_Polarity_Inv", 28, 4 },
|
|
{ "Tx_Polarity_Inv", 24, 4 },
|
|
{ "InstanceNum", 22, 2 },
|
|
{ "StopOnPerr", 21, 1 },
|
|
{ "an_data_ctl", 19, 1 },
|
|
{ "PatEn", 18, 1 },
|
|
{ "MagicEn", 17, 1 },
|
|
{ "T5_AEC_PMA_TX_READY", 4, 4 },
|
|
{ "T5_AEC_PMA_RX_READY", 0, 4 },
|
|
{ "MAC_PORT_PKT_COUNT", 0x3081c, 0 },
|
|
{ "tx_sop_count", 24, 8 },
|
|
{ "tx_eop_count", 16, 8 },
|
|
{ "rx_sop_count", 8, 8 },
|
|
{ "rx_eop_count", 0, 8 },
|
|
{ "MAC_PORT_CFG4", 0x30820, 0 },
|
|
{ "AEC3_RX_WIDTH", 14, 2 },
|
|
{ "AEC2_RX_WIDTH", 12, 2 },
|
|
{ "AEC1_RX_WIDTH", 10, 2 },
|
|
{ "AEC0_RX_WIDTH", 8, 2 },
|
|
{ "AEC3_TX_WIDTH", 6, 2 },
|
|
{ "AEC2_TX_WIDTH", 4, 2 },
|
|
{ "AEC1_TX_WIDTH", 2, 2 },
|
|
{ "AEC0_TX_WIDTH", 0, 2 },
|
|
{ "MAC_PORT_MAGIC_MACID_LO", 0x30824, 0 },
|
|
{ "MAC_PORT_MAGIC_MACID_HI", 0x30828, 0 },
|
|
{ "MAC_PORT_MTIP_RESET_CTRL", 0x3082c, 0 },
|
|
{ "an_reset_sd_tx_clk", 31, 1 },
|
|
{ "an_reset_sd_rx_clk", 30, 1 },
|
|
{ "sgmii_reset_tx_clk", 29, 1 },
|
|
{ "sgmii_reset_rx_clk", 28, 1 },
|
|
{ "sgmii_reset_ref_clk", 27, 1 },
|
|
{ "pcs10g_reset_xfi_rxclk", 26, 1 },
|
|
{ "pcs10g_reset_xfi_txclk", 25, 1 },
|
|
{ "pcs10g_reset_sd_tx_clk", 24, 1 },
|
|
{ "pcs10g_reset_sd_rx_clk", 23, 1 },
|
|
{ "pcs40g_reset_rxclk", 22, 1 },
|
|
{ "pcs40g_reset_sd_tx_clk", 21, 1 },
|
|
{ "pcs40g_reset_sd0_rx_clk", 20, 1 },
|
|
{ "pcs40g_reset_sd1_rx_clk", 19, 1 },
|
|
{ "pcs40g_reset_sd2_rx_clk", 18, 1 },
|
|
{ "pcs40g_reset_sd3_rx_clk", 17, 1 },
|
|
{ "pcs100g_reset_cgmii_rxclk", 16, 1 },
|
|
{ "pcs100g_reset_cgmii_txclk", 15, 1 },
|
|
{ "pcs100g_reset_tx_clk", 14, 1 },
|
|
{ "pcs100g_reset_sd0_rx_clk", 13, 1 },
|
|
{ "pcs100g_reset_sd1_rx_clk", 12, 1 },
|
|
{ "pcs100g_reset_sd2_rx_clk", 11, 1 },
|
|
{ "pcs100g_reset_sd3_rx_clk", 10, 1 },
|
|
{ "mac40g100g_reset_txclk", 9, 1 },
|
|
{ "mac40g100g_reset_rxclk", 8, 1 },
|
|
{ "mac40g100g_reset_ff_tx_clk", 7, 1 },
|
|
{ "mac40g100g_reset_ff_rx_clk", 6, 1 },
|
|
{ "mac40g100g_reset_ts_clk", 5, 1 },
|
|
{ "mac1g10g_reset_rxclk", 4, 1 },
|
|
{ "mac1g10g_reset_txclk", 3, 1 },
|
|
{ "mac1g10g_reset_ff_rx_clk", 2, 1 },
|
|
{ "mac1g10g_reset_ff_tx_clk", 1, 1 },
|
|
{ "xgmii_clk_reset", 0, 1 },
|
|
{ "MAC_PORT_MTIP_GATE_CTRL", 0x30830, 0 },
|
|
{ "an_gate_sd_tx_clk", 31, 1 },
|
|
{ "an_gate_sd_rx_clk", 30, 1 },
|
|
{ "sgmii_gate_tx_clk", 29, 1 },
|
|
{ "sgmii_gate_rx_clk", 28, 1 },
|
|
{ "sgmii_gate_ref_clk", 27, 1 },
|
|
{ "pcs10g_gate_xfi_rxclk", 26, 1 },
|
|
{ "pcs10g_gate_xfi_txclk", 25, 1 },
|
|
{ "pcs10g_gate_sd_tx_clk", 24, 1 },
|
|
{ "pcs10g_gate_sd_rx_clk", 23, 1 },
|
|
{ "pcs40g_gate_rxclk", 22, 1 },
|
|
{ "pcs40g_gate_sd_tx_clk", 21, 1 },
|
|
{ "pcs40g_gate_sd_rx_clk", 20, 1 },
|
|
{ "pcs100g_gate_cgmii_rxclk", 19, 1 },
|
|
{ "pcs100g_gate_cgmii_txclk", 18, 1 },
|
|
{ "pcs100g_gate_tx_clk", 17, 1 },
|
|
{ "pcs100g_gate_sd_rx_clk", 16, 1 },
|
|
{ "mac40g100g_gate_txclk", 15, 1 },
|
|
{ "mac40g100g_gate_rxclk", 14, 1 },
|
|
{ "mac40g100g_gate_ff_tx_clk", 13, 1 },
|
|
{ "mac40g100g_gate_ff_rx_clk", 12, 1 },
|
|
{ "mac40g100g_ts_clk", 11, 1 },
|
|
{ "mac1g10g_gate_rxclk", 10, 1 },
|
|
{ "mac1g10g_gate_txclk", 9, 1 },
|
|
{ "mac1g10g_gate_ff_rx_clk", 8, 1 },
|
|
{ "mac1g10g_gate_ff_tx_clk", 7, 1 },
|
|
{ "aec_rx", 6, 1 },
|
|
{ "aec_tx", 5, 1 },
|
|
{ "pcs100g_clk_enable", 4, 1 },
|
|
{ "pcs40g_clk_enable", 3, 1 },
|
|
{ "pcs10g_clk_enable", 2, 1 },
|
|
{ "pcs1g_clk_enable", 1, 1 },
|
|
{ "an_clk_enable", 0, 1 },
|
|
{ "MAC_PORT_LINK_STATUS", 0x30834, 0 },
|
|
{ "hi_ber", 7, 1 },
|
|
{ "an_done", 6, 1 },
|
|
{ "align_done", 5, 1 },
|
|
{ "block_lock", 4, 1 },
|
|
{ "remflt", 3, 1 },
|
|
{ "locflt", 2, 1 },
|
|
{ "linkup", 1, 1 },
|
|
{ "linkdn", 0, 1 },
|
|
{ "MAC_PORT_AEC_ADD_CTL_STAT_0", 0x30838, 0 },
|
|
{ "AEC_SYS_LANE_TYPE_3", 11, 1 },
|
|
{ "AEC_SYS_LANE_TYPE_2", 10, 1 },
|
|
{ "AEC_SYS_LANE_TYPE_1", 9, 1 },
|
|
{ "AEC_SYS_LANE_TYPE_0", 8, 1 },
|
|
{ "AEC_SYS_LANE_SELECT_3", 6, 2 },
|
|
{ "AEC_SYS_LANE_SELECT_2", 4, 2 },
|
|
{ "AEC_SYS_LANE_SELECT_1", 2, 2 },
|
|
{ "AEC_SYS_LANE_SELECT_O", 0, 2 },
|
|
{ "MAC_PORT_AEC_ADD_CTL_STAT_1", 0x3083c, 0 },
|
|
{ "AEC_RX_UNKNOWN_LANE_3", 11, 1 },
|
|
{ "AEC_RX_UNKNOWN_LANE_2", 10, 1 },
|
|
{ "AEC_RX_UNKNOWN_LANE_1", 9, 1 },
|
|
{ "AEC_RX_UNKNOWN_LANE_0", 8, 1 },
|
|
{ "AEC_RX_LANE_ID_3", 6, 2 },
|
|
{ "AEC_RX_LANE_ID_2", 4, 2 },
|
|
{ "AEC_RX_LANE_ID_1", 2, 2 },
|
|
{ "AEC_RX_LANE_ID_O", 0, 2 },
|
|
{ "MAC_PORT_AEC_XGMII_TIMER_LO_40G", 0x30840, 0 },
|
|
{ "MAC_PORT_AEC_XGMII_TIMER_HI_40G", 0x30844, 0 },
|
|
{ "MAC_PORT_AEC_XGMII_TIMER_LO_100G", 0x30848, 0 },
|
|
{ "MAC_PORT_AEC_XGMII_TIMER_HI_100G", 0x3084c, 0 },
|
|
{ "MAC_PORT_AEC_DEBUG_LO_0", 0x30850, 0 },
|
|
{ "CTL_FSM_CUR_STATE", 28, 3 },
|
|
{ "CIN_FSM_CUR_STATE", 26, 2 },
|
|
{ "CRI_FSM_CUR_STATE", 23, 3 },
|
|
{ "CU_C3_ACK_VALUE", 21, 2 },
|
|
{ "CU_C2_ACK_VALUE", 19, 2 },
|
|
{ "CU_C1_ACK_VALUE", 17, 2 },
|
|
{ "CU_C0_ACK_VALUE", 15, 2 },
|
|
{ "CX_INIT", 13, 1 },
|
|
{ "CX_PRESET", 12, 1 },
|
|
{ "CUF_C3_UPDATE", 9, 2 },
|
|
{ "CUF_C2_UPDATE", 7, 2 },
|
|
{ "CUF_C1_UPDATE", 5, 2 },
|
|
{ "CUF_C0_UPDATE", 3, 2 },
|
|
{ "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
|
|
{ "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
|
|
{ "REG_MAN_DEC_REQ", 0, 1 },
|
|
{ "MAC_PORT_AEC_DEBUG_HI_0", 0x30854, 0 },
|
|
{ "FC_LSNA_", 12, 1 },
|
|
{ "CUF_C0_FSM_DEBUG", 9, 3 },
|
|
{ "CUF_C1_FSM_DEBUG", 6, 3 },
|
|
{ "CUF_C2_FSM_DEBUG", 3, 3 },
|
|
{ "LCK_FSM_CUR_STATE", 0, 3 },
|
|
{ "MAC_PORT_AEC_DEBUG_LO_1", 0x30858, 0 },
|
|
{ "CTL_FSM_CUR_STATE", 28, 3 },
|
|
{ "CIN_FSM_CUR_STATE", 26, 2 },
|
|
{ "CRI_FSM_CUR_STATE", 23, 3 },
|
|
{ "CU_C3_ACK_VALUE", 21, 2 },
|
|
{ "CU_C2_ACK_VALUE", 19, 2 },
|
|
{ "CU_C1_ACK_VALUE", 17, 2 },
|
|
{ "CU_C0_ACK_VALUE", 15, 2 },
|
|
{ "CX_INIT", 13, 1 },
|
|
{ "CX_PRESET", 12, 1 },
|
|
{ "CUF_C3_UPDATE", 9, 2 },
|
|
{ "CUF_C2_UPDATE", 7, 2 },
|
|
{ "CUF_C1_UPDATE", 5, 2 },
|
|
{ "CUF_C0_UPDATE", 3, 2 },
|
|
{ "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
|
|
{ "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
|
|
{ "REG_MAN_DEC_REQ", 0, 1 },
|
|
{ "MAC_PORT_AEC_DEBUG_HI_1", 0x3085c, 0 },
|
|
{ "FC_LSNA_", 12, 1 },
|
|
{ "CUF_C0_FSM_DEBUG", 9, 3 },
|
|
{ "CUF_C1_FSM_DEBUG", 6, 3 },
|
|
{ "CUF_C2_FSM_DEBUG", 3, 3 },
|
|
{ "LCK_FSM_CUR_STATE", 0, 3 },
|
|
{ "MAC_PORT_AEC_DEBUG_LO_2", 0x30860, 0 },
|
|
{ "CTL_FSM_CUR_STATE", 28, 3 },
|
|
{ "CIN_FSM_CUR_STATE", 26, 2 },
|
|
{ "CRI_FSM_CUR_STATE", 23, 3 },
|
|
{ "CU_C3_ACK_VALUE", 21, 2 },
|
|
{ "CU_C2_ACK_VALUE", 19, 2 },
|
|
{ "CU_C1_ACK_VALUE", 17, 2 },
|
|
{ "CU_C0_ACK_VALUE", 15, 2 },
|
|
{ "CX_INIT", 13, 1 },
|
|
{ "CX_PRESET", 12, 1 },
|
|
{ "CUF_C3_UPDATE", 9, 2 },
|
|
{ "CUF_C2_UPDATE", 7, 2 },
|
|
{ "CUF_C1_UPDATE", 5, 2 },
|
|
{ "CUF_C0_UPDATE", 3, 2 },
|
|
{ "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
|
|
{ "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
|
|
{ "REG_MAN_DEC_REQ", 0, 1 },
|
|
{ "MAC_PORT_AEC_DEBUG_HI_2", 0x30864, 0 },
|
|
{ "FC_LSNA_", 12, 1 },
|
|
{ "CUF_C0_FSM_DEBUG", 9, 3 },
|
|
{ "CUF_C1_FSM_DEBUG", 6, 3 },
|
|
{ "CUF_C2_FSM_DEBUG", 3, 3 },
|
|
{ "LCK_FSM_CUR_STATE", 0, 3 },
|
|
{ "MAC_PORT_AEC_DEBUG_LO_3", 0x30868, 0 },
|
|
{ "CTL_FSM_CUR_STATE", 28, 3 },
|
|
{ "CIN_FSM_CUR_STATE", 26, 2 },
|
|
{ "CRI_FSM_CUR_STATE", 23, 3 },
|
|
{ "CU_C3_ACK_VALUE", 21, 2 },
|
|
{ "CU_C2_ACK_VALUE", 19, 2 },
|
|
{ "CU_C1_ACK_VALUE", 17, 2 },
|
|
{ "CU_C0_ACK_VALUE", 15, 2 },
|
|
{ "CX_INIT", 13, 1 },
|
|
{ "CX_PRESET", 12, 1 },
|
|
{ "CUF_C3_UPDATE", 9, 2 },
|
|
{ "CUF_C2_UPDATE", 7, 2 },
|
|
{ "CUF_C1_UPDATE", 5, 2 },
|
|
{ "CUF_C0_UPDATE", 3, 2 },
|
|
{ "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
|
|
{ "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
|
|
{ "REG_MAN_DEC_REQ", 0, 1 },
|
|
{ "MAC_PORT_AEC_DEBUG_HI_3", 0x3086c, 0 },
|
|
{ "FC_LSNA_", 12, 1 },
|
|
{ "CUF_C0_FSM_DEBUG", 9, 3 },
|
|
{ "CUF_C1_FSM_DEBUG", 6, 3 },
|
|
{ "CUF_C2_FSM_DEBUG", 3, 3 },
|
|
{ "LCK_FSM_CUR_STATE", 0, 3 },
|
|
{ "MAC_PORT_MAC_DEBUG_RO", 0x30870, 0 },
|
|
{ "mac40g100g_tx_underflow", 13, 1 },
|
|
{ "mac1g10g_magic_ind", 12, 1 },
|
|
{ "mac1g10g_ff_rx_empty", 11, 1 },
|
|
{ "mac1g10g_ff_tx_ovr_err", 10, 1 },
|
|
{ "mac1g10g_if_mode_ena", 8, 2 },
|
|
{ "mac1g10g_mii_ena_10", 7, 1 },
|
|
{ "mac1g10g_pause_on", 6, 1 },
|
|
{ "mac1g10g_pfc_mode", 5, 1 },
|
|
{ "mac1g10g_rx_sfd_o", 4, 1 },
|
|
{ "mac1g10g_tx_empty", 3, 1 },
|
|
{ "mac1g10g_tx_sfd_o", 2, 1 },
|
|
{ "mac1g10g_tx_ts_frm_out", 1, 1 },
|
|
{ "mac1g10g_tx_underflow", 0, 1 },
|
|
{ "MAC_PORT_MAC_CTRL_RW", 0x30874, 0 },
|
|
{ "mac40g100g_ff_tx_pfc_xoff", 17, 8 },
|
|
{ "mac40g100g_tx_loc_fault", 16, 1 },
|
|
{ "mac40g100g_tx_rem_fault", 15, 1 },
|
|
{ "mac40g_loop_bck", 14, 1 },
|
|
{ "mac1g10g_magic_ena", 13, 1 },
|
|
{ "mac1g10g_if_mode_set", 11, 2 },
|
|
{ "mac1g10g_tx_loc_fault", 10, 1 },
|
|
{ "mac1g10g_tx_rem_fault", 9, 1 },
|
|
{ "mac1g10g_xoff_gen", 1, 8 },
|
|
{ "mac1g_loop_bck", 0, 1 },
|
|
{ "MAC_PORT_PCS_DEBUG0_RO", 0x30878, 0 },
|
|
{ "fpga_lock", 26, 4 },
|
|
{ "an_done", 25, 1 },
|
|
{ "an_int", 24, 1 },
|
|
{ "an_pcs_rx_clk_ena", 23, 1 },
|
|
{ "an_pcs_tx_clk_ena", 22, 1 },
|
|
{ "an_select", 17, 5 },
|
|
{ "an_prog", 16, 1 },
|
|
{ "pcs40g_block_lock", 12, 4 },
|
|
{ "pcs40g_ber_timer_done", 11, 1 },
|
|
{ "pcs10g_fec_locked", 10, 1 },
|
|
{ "pcs10g_block_lock", 9, 1 },
|
|
{ "sgmii_gmii_col", 8, 1 },
|
|
{ "sgmii_gmii_crs", 7, 1 },
|
|
{ "sgmii_sd_loopback", 6, 1 },
|
|
{ "sgmii_sg_an_done", 5, 1 },
|
|
{ "sgmii_sg_hd", 4, 1 },
|
|
{ "sgmii_sg_page_rx", 3, 1 },
|
|
{ "sgmii_sg_rx_sync", 2, 1 },
|
|
{ "sgmii_sg_speed", 0, 2 },
|
|
{ "MAC_PORT_PCS_CTRL_RW", 0x3087c, 0 },
|
|
{ "tx_li_fault", 31, 1 },
|
|
{ "pad", 30, 1 },
|
|
{ "blk_stb_val", 22, 8 },
|
|
{ "debug_sel", 18, 4 },
|
|
{ "sgmii_loop", 15, 3 },
|
|
{ "an_dis_timer", 14, 1 },
|
|
{ "pcs100g_ber_timer_short", 13, 1 },
|
|
{ "pcs100g_tx_lane_thresh", 9, 4 },
|
|
{ "pcs100g_vl_intvl", 8, 1 },
|
|
{ "sgmii_tx_lane_ckmult", 4, 3 },
|
|
{ "sgmii_tx_lane_thresh", 0, 4 },
|
|
{ "MAC_PORT_PCS_DEBUG1_RO", 0x30880, 0 },
|
|
{ "pcs100g_align_lock", 21, 1 },
|
|
{ "pcs100g_ber_timer_done", 20, 1 },
|
|
{ "pcs100g_block_lock", 0, 20 },
|
|
{ "MAC_PORT_PERR_INT_EN_100G", 0x30884, 0 },
|
|
{ "Perr_rx_fec100g_dly", 29, 1 },
|
|
{ "Perr_rx_fec100g", 28, 1 },
|
|
{ "Perr_rx3_fec100g_dk", 27, 1 },
|
|
{ "Perr_rx2_fec100g_dk", 26, 1 },
|
|
{ "Perr_rx1_fec100g_dk", 25, 1 },
|
|
{ "Perr_rx0_fec100g_dk", 24, 1 },
|
|
{ "Perr_tx3_pcs100g", 23, 1 },
|
|
{ "Perr_tx2_pcs100g", 22, 1 },
|
|
{ "Perr_tx1_pcs100g", 21, 1 },
|
|
{ "Perr_tx0_pcs100g", 20, 1 },
|
|
{ "Perr_rx19_pcs100g", 19, 1 },
|
|
{ "Perr_rx18_pcs100g", 18, 1 },
|
|
{ "Perr_rx17_pcs100g", 17, 1 },
|
|
{ "Perr_rx16_pcs100g", 16, 1 },
|
|
{ "Perr_rx15_pcs100g", 15, 1 },
|
|
{ "Perr_rx14_pcs100g", 14, 1 },
|
|
{ "Perr_rx13_pcs100g", 13, 1 },
|
|
{ "Perr_rx12_pcs100g", 12, 1 },
|
|
{ "Perr_rx11_pcs100g", 11, 1 },
|
|
{ "Perr_rx10_pcs100g", 10, 1 },
|
|
{ "Perr_rx9_pcs100g", 9, 1 },
|
|
{ "Perr_rx8_pcs100g", 8, 1 },
|
|
{ "Perr_rx7_pcs100g", 7, 1 },
|
|
{ "Perr_rx6_pcs100g", 6, 1 },
|
|
{ "Perr_rx5_pcs100g", 5, 1 },
|
|
{ "Perr_rx4_pcs100g", 4, 1 },
|
|
{ "Perr_rx3_pcs100g", 3, 1 },
|
|
{ "Perr_rx2_pcs100g", 2, 1 },
|
|
{ "Perr_rx1_pcs100g", 1, 1 },
|
|
{ "Perr_rx0_pcs100g", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_CAUSE_100G", 0x30888, 0 },
|
|
{ "Perr_rx_fec100g_dly", 29, 1 },
|
|
{ "Perr_rx_fec100g", 28, 1 },
|
|
{ "Perr_rx3_fec100g_dk", 27, 1 },
|
|
{ "Perr_rx2_fec100g_dk", 26, 1 },
|
|
{ "Perr_rx1_fec100g_dk", 25, 1 },
|
|
{ "Perr_rx0_fec100g_dk", 24, 1 },
|
|
{ "Perr_tx3_pcs100g", 23, 1 },
|
|
{ "Perr_tx2_pcs100g", 22, 1 },
|
|
{ "Perr_tx1_pcs100g", 21, 1 },
|
|
{ "Perr_tx0_pcs100g", 20, 1 },
|
|
{ "Perr_rx19_pcs100g", 19, 1 },
|
|
{ "Perr_rx18_pcs100g", 18, 1 },
|
|
{ "Perr_rx17_pcs100g", 17, 1 },
|
|
{ "Perr_rx16_pcs100g", 16, 1 },
|
|
{ "Perr_rx15_pcs100g", 15, 1 },
|
|
{ "Perr_rx14_pcs100g", 14, 1 },
|
|
{ "Perr_rx13_pcs100g", 13, 1 },
|
|
{ "Perr_rx12_pcs100g", 12, 1 },
|
|
{ "Perr_rx11_pcs100g", 11, 1 },
|
|
{ "Perr_rx10_pcs100g", 10, 1 },
|
|
{ "Perr_rx9_pcs100g", 9, 1 },
|
|
{ "Perr_rx8_pcs100g", 8, 1 },
|
|
{ "Perr_rx7_pcs100g", 7, 1 },
|
|
{ "Perr_rx6_pcs100g", 6, 1 },
|
|
{ "Perr_rx5_pcs100g", 5, 1 },
|
|
{ "Perr_rx4_pcs100g", 4, 1 },
|
|
{ "Perr_rx3_pcs100g", 3, 1 },
|
|
{ "Perr_rx2_pcs100g", 2, 1 },
|
|
{ "Perr_rx1_pcs100g", 1, 1 },
|
|
{ "Perr_rx0_pcs100g", 0, 1 },
|
|
{ "MAC_PORT_PERR_ENABLE_100G", 0x3088c, 0 },
|
|
{ "Perr_rx_fec100g_dly", 29, 1 },
|
|
{ "Perr_rx_fec100g", 28, 1 },
|
|
{ "Perr_rx3_fec100g_dk", 27, 1 },
|
|
{ "Perr_rx2_fec100g_dk", 26, 1 },
|
|
{ "Perr_rx1_fec100g_dk", 25, 1 },
|
|
{ "Perr_rx0_fec100g_dk", 24, 1 },
|
|
{ "Perr_tx3_pcs100g", 23, 1 },
|
|
{ "Perr_tx2_pcs100g", 22, 1 },
|
|
{ "Perr_tx1_pcs100g", 21, 1 },
|
|
{ "Perr_tx0_pcs100g", 20, 1 },
|
|
{ "Perr_rx19_pcs100g", 19, 1 },
|
|
{ "Perr_rx18_pcs100g", 18, 1 },
|
|
{ "Perr_rx17_pcs100g", 17, 1 },
|
|
{ "Perr_rx16_pcs100g", 16, 1 },
|
|
{ "Perr_rx15_pcs100g", 15, 1 },
|
|
{ "Perr_rx14_pcs100g", 14, 1 },
|
|
{ "Perr_rx13_pcs100g", 13, 1 },
|
|
{ "Perr_rx12_pcs100g", 12, 1 },
|
|
{ "Perr_rx11_pcs100g", 11, 1 },
|
|
{ "Perr_rx10_pcs100g", 10, 1 },
|
|
{ "Perr_rx9_pcs100g", 9, 1 },
|
|
{ "Perr_rx8_pcs100g", 8, 1 },
|
|
{ "Perr_rx7_pcs100g", 7, 1 },
|
|
{ "Perr_rx6_pcs100g", 6, 1 },
|
|
{ "Perr_rx5_pcs100g", 5, 1 },
|
|
{ "Perr_rx4_pcs100g", 4, 1 },
|
|
{ "Perr_rx3_pcs100g", 3, 1 },
|
|
{ "Perr_rx2_pcs100g", 2, 1 },
|
|
{ "Perr_rx1_pcs100g", 1, 1 },
|
|
{ "Perr_rx0_pcs100g", 0, 1 },
|
|
{ "MAC_PORT_MAC_STAT_DEBUG", 0x30890, 0 },
|
|
{ "MAC_PORT_MAC_25G_50G_AM0", 0x30894, 0 },
|
|
{ "MAC_PORT_MAC_25G_50G_AM1", 0x30898, 0 },
|
|
{ "MAC_PORT_MAC_25G_50G_AM2", 0x3089c, 0 },
|
|
{ "MAC_PORT_MAC_25G_50G_AM3", 0x308a0, 0 },
|
|
{ "MAC_PORT_MAC_AN_STATE_STATUS", 0x308a4, 0 },
|
|
{ "MAC_PORT_EPIO_DATA0", 0x308c0, 0 },
|
|
{ "MAC_PORT_EPIO_DATA1", 0x308c4, 0 },
|
|
{ "MAC_PORT_EPIO_DATA2", 0x308c8, 0 },
|
|
{ "MAC_PORT_EPIO_DATA3", 0x308cc, 0 },
|
|
{ "MAC_PORT_EPIO_OP", 0x308d0, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Write", 8, 1 },
|
|
{ "Address", 0, 8 },
|
|
{ "MAC_PORT_WOL_STATUS", 0x308d4, 0 },
|
|
{ "MagicDetected", 31, 1 },
|
|
{ "PatDetected", 30, 1 },
|
|
{ "ClearMagic", 4, 1 },
|
|
{ "ClearMatch", 3, 1 },
|
|
{ "MatchedFilter", 0, 3 },
|
|
{ "MAC_PORT_INT_EN", 0x308d8, 0 },
|
|
{ "pps", 30, 1 },
|
|
{ "tx_ts_avail", 29, 1 },
|
|
{ "single_alarm", 28, 1 },
|
|
{ "periodic_alarm", 27, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "an_page_rcvd", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "MAC_PORT_INT_CAUSE", 0x308dc, 0 },
|
|
{ "pps", 30, 1 },
|
|
{ "tx_ts_avail", 29, 1 },
|
|
{ "single_alarm", 28, 1 },
|
|
{ "periodic_alarm", 27, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "an_page_rcvd", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_EN", 0x308e0, 0 },
|
|
{ "Perr_pkt_ram", 31, 1 },
|
|
{ "Perr_mask_ram", 30, 1 },
|
|
{ "Perr_crc_ram", 29, 1 },
|
|
{ "rx_mac40g", 28, 1 },
|
|
{ "tx_mac40g", 27, 1 },
|
|
{ "rx_st_mac40g", 26, 1 },
|
|
{ "tx_st_mac40g", 25, 1 },
|
|
{ "tx_mac1g10g", 24, 1 },
|
|
{ "rx_mac1g10g", 23, 1 },
|
|
{ "rx_status_mac1g10g", 22, 1 },
|
|
{ "rx_st_mac1g10g", 21, 1 },
|
|
{ "tx_st_mac1g10g", 20, 1 },
|
|
{ "Perr_tx0_pcs40g", 19, 1 },
|
|
{ "Perr_tx1_pcs40g", 18, 1 },
|
|
{ "Perr_tx2_pcs40g", 17, 1 },
|
|
{ "Perr_tx3_pcs40g", 16, 1 },
|
|
{ "Perr_tx0_fec40g", 15, 1 },
|
|
{ "Perr_tx1_fec40g", 14, 1 },
|
|
{ "Perr_tx2_fec40g", 13, 1 },
|
|
{ "Perr_tx3_fec40g", 12, 1 },
|
|
{ "Perr_rx0_pcs40g", 11, 1 },
|
|
{ "Perr_rx1_pcs40g", 10, 1 },
|
|
{ "Perr_rx2_pcs40g", 9, 1 },
|
|
{ "Perr_rx3_pcs40g", 8, 1 },
|
|
{ "Perr_rx0_fec40g", 7, 1 },
|
|
{ "Perr_rx1_fec40g", 6, 1 },
|
|
{ "Perr_rx2_fec40g", 5, 1 },
|
|
{ "Perr_rx3_fec40g", 4, 1 },
|
|
{ "Perr_rx_pcs10g_lpbk", 3, 1 },
|
|
{ "Perr_rx_pcs10g", 2, 1 },
|
|
{ "Perr_rx_pcs1g", 1, 1 },
|
|
{ "Perr_tx_pcs1g", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_CAUSE", 0x308e4, 0 },
|
|
{ "Perr_pkt_ram", 31, 1 },
|
|
{ "Perr_mask_ram", 30, 1 },
|
|
{ "Perr_crc_ram", 29, 1 },
|
|
{ "rx_mac40g", 28, 1 },
|
|
{ "tx_mac40g", 27, 1 },
|
|
{ "rx_st_mac40g", 26, 1 },
|
|
{ "tx_st_mac40g", 25, 1 },
|
|
{ "tx_mac1g10g", 24, 1 },
|
|
{ "rx_mac1g10g", 23, 1 },
|
|
{ "rx_status_mac1g10g", 22, 1 },
|
|
{ "rx_st_mac1g10g", 21, 1 },
|
|
{ "tx_st_mac1g10g", 20, 1 },
|
|
{ "Perr_tx0_pcs40g", 19, 1 },
|
|
{ "Perr_tx1_pcs40g", 18, 1 },
|
|
{ "Perr_tx2_pcs40g", 17, 1 },
|
|
{ "Perr_tx3_pcs40g", 16, 1 },
|
|
{ "Perr_tx0_fec40g", 15, 1 },
|
|
{ "Perr_tx1_fec40g", 14, 1 },
|
|
{ "Perr_tx2_fec40g", 13, 1 },
|
|
{ "Perr_tx3_fec40g", 12, 1 },
|
|
{ "Perr_rx0_pcs40g", 11, 1 },
|
|
{ "Perr_rx1_pcs40g", 10, 1 },
|
|
{ "Perr_rx2_pcs40g", 9, 1 },
|
|
{ "Perr_rx3_pcs40g", 8, 1 },
|
|
{ "Perr_rx0_fec40g", 7, 1 },
|
|
{ "Perr_rx1_fec40g", 6, 1 },
|
|
{ "Perr_rx2_fec40g", 5, 1 },
|
|
{ "Perr_rx3_fec40g", 4, 1 },
|
|
{ "Perr_rx_pcs10g_lpbk", 3, 1 },
|
|
{ "Perr_rx_pcs10g", 2, 1 },
|
|
{ "Perr_rx_pcs1g", 1, 1 },
|
|
{ "Perr_tx_pcs1g", 0, 1 },
|
|
{ "MAC_PORT_PERR_ENABLE", 0x308e8, 0 },
|
|
{ "Perr_pkt_ram", 31, 1 },
|
|
{ "Perr_mask_ram", 30, 1 },
|
|
{ "Perr_crc_ram", 29, 1 },
|
|
{ "rx_mac40g", 28, 1 },
|
|
{ "tx_mac40g", 27, 1 },
|
|
{ "rx_st_mac40g", 26, 1 },
|
|
{ "tx_st_mac40g", 25, 1 },
|
|
{ "tx_mac1g10g", 24, 1 },
|
|
{ "rx_mac1g10g", 23, 1 },
|
|
{ "rx_status_mac1g10g", 22, 1 },
|
|
{ "rx_st_mac1g10g", 21, 1 },
|
|
{ "tx_st_mac1g10g", 20, 1 },
|
|
{ "Perr_tx0_pcs40g", 19, 1 },
|
|
{ "Perr_tx1_pcs40g", 18, 1 },
|
|
{ "Perr_tx2_pcs40g", 17, 1 },
|
|
{ "Perr_tx3_pcs40g", 16, 1 },
|
|
{ "Perr_tx0_fec40g", 15, 1 },
|
|
{ "Perr_tx1_fec40g", 14, 1 },
|
|
{ "Perr_tx2_fec40g", 13, 1 },
|
|
{ "Perr_tx3_fec40g", 12, 1 },
|
|
{ "Perr_rx0_pcs40g", 11, 1 },
|
|
{ "Perr_rx1_pcs40g", 10, 1 },
|
|
{ "Perr_rx2_pcs40g", 9, 1 },
|
|
{ "Perr_rx3_pcs40g", 8, 1 },
|
|
{ "Perr_rx0_fec40g", 7, 1 },
|
|
{ "Perr_rx1_fec40g", 6, 1 },
|
|
{ "Perr_rx2_fec40g", 5, 1 },
|
|
{ "Perr_rx3_fec40g", 4, 1 },
|
|
{ "Perr_rx_pcs10g_lpbk", 3, 1 },
|
|
{ "Perr_rx_pcs10g", 2, 1 },
|
|
{ "Perr_rx_pcs1g", 1, 1 },
|
|
{ "Perr_tx_pcs1g", 0, 1 },
|
|
{ "MAC_PORT_PERR_INJECT", 0x308ec, 0 },
|
|
{ "MemSel", 1, 6 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG0", 0x308f0, 0 },
|
|
{ "TXDTS", 31, 1 },
|
|
{ "TXCTS", 30, 1 },
|
|
{ "TXBTS", 29, 1 },
|
|
{ "TXATS", 28, 1 },
|
|
{ "TXDOBS", 27, 1 },
|
|
{ "TXCOBS", 26, 1 },
|
|
{ "TXBOBS", 25, 1 },
|
|
{ "TXAOBS", 24, 1 },
|
|
{ "HSSREFCLKVALIDA", 20, 1 },
|
|
{ "HSSREFCLKVALIDB", 19, 1 },
|
|
{ "HSSRESYNCA", 18, 1 },
|
|
{ "HSSAVDHI", 17, 1 },
|
|
{ "HSSRESYNCB", 16, 1 },
|
|
{ "HSSRECCALA", 15, 1 },
|
|
{ "HSSRXACMODE", 14, 1 },
|
|
{ "HSSRECCALB", 13, 1 },
|
|
{ "HSSPLLBYPA", 12, 1 },
|
|
{ "HSSPLLBYPB", 11, 1 },
|
|
{ "HSSPDWNPLLA", 10, 1 },
|
|
{ "HSSPDWNPLLB", 9, 1 },
|
|
{ "HSSVCOSELA", 8, 1 },
|
|
{ "HSSVCOSELB", 7, 1 },
|
|
{ "HSSCALCOMP", 6, 1 },
|
|
{ "HSSCALENAB", 5, 1 },
|
|
{ "HSSEXTC16SEL", 4, 1 },
|
|
{ "MAC_PORT_HSS_CFG1", 0x308f4, 0 },
|
|
{ "RXACONFIGSEL", 30, 2 },
|
|
{ "RXAQUIET", 29, 1 },
|
|
{ "RXAREFRESH", 28, 1 },
|
|
{ "RXBCONFIGSEL", 26, 2 },
|
|
{ "RXBQUIET", 25, 1 },
|
|
{ "RXBREFRESH", 24, 1 },
|
|
{ "RXCCONFIGSEL", 22, 2 },
|
|
{ "RXCQUIET", 21, 1 },
|
|
{ "RXCREFRESH", 20, 1 },
|
|
{ "RXDCONFIGSEL", 18, 2 },
|
|
{ "RXDQUIET", 17, 1 },
|
|
{ "RXDREFRESH", 16, 1 },
|
|
{ "TXACONFIGSEL", 14, 2 },
|
|
{ "TXAQUIET", 13, 1 },
|
|
{ "TXAREFRESH", 12, 1 },
|
|
{ "TXBCONFIGSEL", 10, 2 },
|
|
{ "TXBQUIET", 9, 1 },
|
|
{ "TXBREFRESH", 8, 1 },
|
|
{ "TXCCONFIGSEL", 6, 2 },
|
|
{ "TXCQUIET", 5, 1 },
|
|
{ "TXCREFRESH", 4, 1 },
|
|
{ "TXDCONFIGSEL", 2, 2 },
|
|
{ "TXDQUIET", 1, 1 },
|
|
{ "TXDREFRESH", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG2", 0x308f8, 0 },
|
|
{ "RXAASSTCLK", 31, 1 },
|
|
{ "T5RXAPRBSRST", 30, 1 },
|
|
{ "RXBASSTCLK", 29, 1 },
|
|
{ "T5RXBPRBSRST", 28, 1 },
|
|
{ "RXCASSTCLK", 27, 1 },
|
|
{ "T5RXCPRBSRST", 26, 1 },
|
|
{ "RXDASSTCLK", 25, 1 },
|
|
{ "T5RXDPRBSRST", 24, 1 },
|
|
{ "RXDDATASYNC", 23, 1 },
|
|
{ "RXCDATASYNC", 22, 1 },
|
|
{ "RXBDATASYNC", 21, 1 },
|
|
{ "RXADATASYNC", 20, 1 },
|
|
{ "RXDEARLYIN", 19, 1 },
|
|
{ "RXDLATEIN", 18, 1 },
|
|
{ "RXDPHSLOCK", 17, 1 },
|
|
{ "RXDPHSDNIN", 16, 1 },
|
|
{ "RXDPHSUPIN", 15, 1 },
|
|
{ "RXCEARLYIN", 14, 1 },
|
|
{ "RXCLATEIN", 13, 1 },
|
|
{ "RXCPHSLOCK", 12, 1 },
|
|
{ "RXCPHSDNIN", 11, 1 },
|
|
{ "RXCPHSUPIN", 10, 1 },
|
|
{ "RXBEARLYIN", 9, 1 },
|
|
{ "RXBLATEIN", 8, 1 },
|
|
{ "RXBPHSLOCK", 7, 1 },
|
|
{ "RXBPHSDNIN", 6, 1 },
|
|
{ "RXBPHSUPIN", 5, 1 },
|
|
{ "RXAEARLYIN", 4, 1 },
|
|
{ "RXALATEIN", 3, 1 },
|
|
{ "RXAPHSLOCK", 2, 1 },
|
|
{ "RXAPHSDNIN", 1, 1 },
|
|
{ "RXAPHSUPIN", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG3", 0x308fc, 0 },
|
|
{ "HSSCALSSTN", 22, 6 },
|
|
{ "HSSCALSSTP", 16, 6 },
|
|
{ "HSSPLLCONFIGB", 8, 8 },
|
|
{ "HSSPLLCONFIGA", 0, 8 },
|
|
{ "MAC_PORT_HSS_CFG4", 0x30900, 0 },
|
|
{ "HSSREFDIVA", 24, 4 },
|
|
{ "HSSREFDIVB", 20, 4 },
|
|
{ "HSSPLLDIV2B", 19, 1 },
|
|
{ "HSSPLLDIV2A", 18, 1 },
|
|
{ "HSSDIVSELA", 9, 9 },
|
|
{ "HSSDIVSELB", 0, 9 },
|
|
{ "MAC_PORT_HSS_STATUS", 0x30904, 0 },
|
|
{ "RXDERROFLOW", 19, 1 },
|
|
{ "RXCERROFLOW", 18, 1 },
|
|
{ "RXBERROFLOW", 17, 1 },
|
|
{ "RXAERROFLOW", 16, 1 },
|
|
{ "RXDPRBSSYNC", 15, 1 },
|
|
{ "RXCPRBSSYNC", 14, 1 },
|
|
{ "RXBPRBSSYNC", 13, 1 },
|
|
{ "RXAPRBSSYNC", 12, 1 },
|
|
{ "RXDPRBSERR", 11, 1 },
|
|
{ "RXCPRBSERR", 10, 1 },
|
|
{ "RXBPRBSERR", 9, 1 },
|
|
{ "RXAPRBSERR", 8, 1 },
|
|
{ "RXDSIGDET", 7, 1 },
|
|
{ "RXCSIGDET", 6, 1 },
|
|
{ "RXBSIGDET", 5, 1 },
|
|
{ "RXASIGDET", 4, 1 },
|
|
{ "HSSPLLLOCKB", 3, 1 },
|
|
{ "HSSPLLLOCKA", 2, 1 },
|
|
{ "HSSPRTREADYB", 1, 1 },
|
|
{ "HSSPRTREADYA", 0, 1 },
|
|
{ "MAC_PORT_HSS_EEE_STATUS", 0x30908, 0 },
|
|
{ "RXAQUIET_STATUS", 15, 1 },
|
|
{ "RXAREFRESH_STATUS", 14, 1 },
|
|
{ "RXBQUIET_STATUS", 13, 1 },
|
|
{ "RXBREFRESH_STATUS", 12, 1 },
|
|
{ "RXCQUIET_STATUS", 11, 1 },
|
|
{ "RXCREFRESH_STATUS", 10, 1 },
|
|
{ "RXDQUIET_STATUS", 9, 1 },
|
|
{ "RXDREFRESH_STATUS", 8, 1 },
|
|
{ "TXAQUIET_STATUS", 7, 1 },
|
|
{ "TXAREFRESH_STATUS", 6, 1 },
|
|
{ "TXBQUIET_STATUS", 5, 1 },
|
|
{ "TXBREFRESH_STATUS", 4, 1 },
|
|
{ "TXCQUIET_STATUS", 3, 1 },
|
|
{ "TXCREFRESH_STATUS", 2, 1 },
|
|
{ "TXDQUIET_STATUS", 1, 1 },
|
|
{ "TXDREFRESH_STATUS", 0, 1 },
|
|
{ "MAC_PORT_HSS_SIGDET_STATUS", 0x3090c, 0 },
|
|
{ "MAC_PORT_HSS_PL_CTL", 0x30910, 0 },
|
|
{ "TOV", 16, 8 },
|
|
{ "TSU", 8, 8 },
|
|
{ "IPW", 0, 8 },
|
|
{ "MAC_PORT_RUNT_FRAME", 0x30914, 0 },
|
|
{ "runtclear", 16, 1 },
|
|
{ "runt", 0, 16 },
|
|
{ "MAC_PORT_EEE_STATUS", 0x30918, 0 },
|
|
{ "eee_tx_10g_state", 10, 2 },
|
|
{ "eee_rx_10g_state", 8, 2 },
|
|
{ "eee_tx_1g_state", 6, 2 },
|
|
{ "eee_rx_1g_state", 4, 2 },
|
|
{ "pma_rx_refresh", 3, 1 },
|
|
{ "pma_rx_quiet", 2, 1 },
|
|
{ "pma_tx_refresh", 1, 1 },
|
|
{ "pma_tx_quiet", 0, 1 },
|
|
{ "MAC_PORT_CGEN", 0x3091c, 0 },
|
|
{ "CGEN", 8, 1 },
|
|
{ "sd7_CGEN", 7, 1 },
|
|
{ "sd6_CGEN", 6, 1 },
|
|
{ "sd5_CGEN", 5, 1 },
|
|
{ "sd4_CGEN", 4, 1 },
|
|
{ "sd3_CGEN", 3, 1 },
|
|
{ "sd2_CGEN", 2, 1 },
|
|
{ "sd1_CGEN", 1, 1 },
|
|
{ "sd0_CGEN", 0, 1 },
|
|
{ "MAC_PORT_CGEN_MTIP", 0x30920, 0 },
|
|
{ "MACSEG5_CGEN", 11, 1 },
|
|
{ "PCSSEG5_CGEN", 10, 1 },
|
|
{ "MACSEG4_CGEN", 9, 1 },
|
|
{ "PCSSEG4_CGEN", 8, 1 },
|
|
{ "MACSEG3_CGEN", 7, 1 },
|
|
{ "PCSSEG3_CGEN", 6, 1 },
|
|
{ "MACSEG2_CGEN", 5, 1 },
|
|
{ "PCSSEG2_CGEN", 4, 1 },
|
|
{ "MACSEG1_CGEN", 3, 1 },
|
|
{ "PCSSEG1_CGEN", 2, 1 },
|
|
{ "MACSEG0_CGEN", 1, 1 },
|
|
{ "PCSSEG0_CGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_TS_ID", 0x30924, 0 },
|
|
{ "MAC_PORT_TX_TS_VAL_LO", 0x30928, 0 },
|
|
{ "MAC_PORT_TX_TS_VAL_HI", 0x3092c, 0 },
|
|
{ "MAC_PORT_EEE_CTL", 0x30930, 0 },
|
|
{ "EEE_CTRL", 2, 30 },
|
|
{ "TICK_START", 1, 1 },
|
|
{ "En", 0, 1 },
|
|
{ "MAC_PORT_EEE_TX_CTL", 0x30934, 0 },
|
|
{ "WAKE_TIMER", 16, 16 },
|
|
{ "HSS_TIMER", 5, 4 },
|
|
{ "HSS_CTL", 4, 1 },
|
|
{ "LPI_ACTIVE", 3, 1 },
|
|
{ "LPI_TXHOLD", 2, 1 },
|
|
{ "LPI_REQ", 1, 1 },
|
|
{ "EEE_TX_RESET", 0, 1 },
|
|
{ "MAC_PORT_EEE_RX_CTL", 0x30938, 0 },
|
|
{ "WAKE_TIMER", 16, 16 },
|
|
{ "HSS_TIMER", 5, 4 },
|
|
{ "HSS_CTL", 4, 1 },
|
|
{ "LPI_IND", 1, 1 },
|
|
{ "EEE_RX_RESET", 0, 1 },
|
|
{ "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3093c, 0 },
|
|
{ "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x30940, 0 },
|
|
{ "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x30944, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x30948, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3094c, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x30950, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x30954, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x30958, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3095c, 0 },
|
|
{ "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x30960, 0 },
|
|
{ "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x30964, 0 },
|
|
{ "MAC_PORT_EEE_WF_COUNT", 0x30968, 0 },
|
|
{ "wake_cnt_clr", 16, 1 },
|
|
{ "wake_cnt", 0, 16 },
|
|
{ "MAC_PORT_PTP_TIMER_RD0_LO", 0x3096c, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD0_HI", 0x30970, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD1_LO", 0x30974, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD1_HI", 0x30978, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_WR_LO", 0x3097c, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_WR_HI", 0x30980, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_0", 0x30984, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_1", 0x30988, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3098c, 0 },
|
|
{ "MAC_PORT_PTP_SUM_LO", 0x30990, 0 },
|
|
{ "MAC_PORT_PTP_SUM_HI", 0x30994, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_INCR0", 0x30998, 0 },
|
|
{ "Y", 16, 16 },
|
|
{ "X", 0, 16 },
|
|
{ "MAC_PORT_PTP_TIMER_INCR1", 0x3099c, 0 },
|
|
{ "Y_TICK", 16, 16 },
|
|
{ "X_TICK", 0, 16 },
|
|
{ "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x309a0, 0 },
|
|
{ "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x309a4, 0 },
|
|
{ "B", 16, 16 },
|
|
{ "A", 0, 16 },
|
|
{ "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x309a8, 0 },
|
|
{ "MAC_PORT_PTP_CFG", 0x309ac, 0 },
|
|
{ "ALARM_EN", 21, 1 },
|
|
{ "ALARM_START", 20, 1 },
|
|
{ "PPS_EN", 19, 1 },
|
|
{ "FRZ", 18, 1 },
|
|
{ "OFFSER_ADJUST_SIGN", 17, 1 },
|
|
{ "ADD_OFFSET", 16, 1 },
|
|
{ "CYCLE1", 8, 8 },
|
|
{ "Q", 0, 8 },
|
|
{ "MAC_PORT_PTP_PPS", 0x309b0, 0 },
|
|
{ "MAC_PORT_PTP_SINGLE_ALARM", 0x309b4, 0 },
|
|
{ "MAC_PORT_PTP_PERIODIC_ALARM", 0x309b8, 0 },
|
|
{ "MAC_PORT_PTP_STATUS", 0x309bc, 0 },
|
|
{ "MAC_PORT_MTIP_REVISION", 0x30a00, 0 },
|
|
{ "CUSTREV", 16, 16 },
|
|
{ "VER", 8, 8 },
|
|
{ "REV", 0, 8 },
|
|
{ "MAC_PORT_MTIP_SCRATCH", 0x30a04, 0 },
|
|
{ "MAC_PORT_MTIP_COMMAND_CONFIG", 0x30a08, 0 },
|
|
{ "TX_FLUSH", 22, 1 },
|
|
{ "RX_SFD_ANY", 21, 1 },
|
|
{ "PAUSE_PFC_COMP", 20, 1 },
|
|
{ "PFC_MODE", 19, 1 },
|
|
{ "RS_COL_CNT_EXT", 18, 1 },
|
|
{ "NO_LGTH_CHECK", 17, 1 },
|
|
{ "SEND_IDLE", 16, 1 },
|
|
{ "PHY_TXENA", 15, 1 },
|
|
{ "RX_ERR_DISC", 14, 1 },
|
|
{ "CMD_FRAME_ENA", 13, 1 },
|
|
{ "SW_RESET", 12, 1 },
|
|
{ "TX_PAD_EN", 11, 1 },
|
|
{ "LOOPBACK_EN", 10, 1 },
|
|
{ "TX_ADDR_INS", 9, 1 },
|
|
{ "PAUSE_IGNORE", 8, 1 },
|
|
{ "PAUSE_FWD", 7, 1 },
|
|
{ "CRC_FWD", 6, 1 },
|
|
{ "PAD_EN", 5, 1 },
|
|
{ "PROMIS_EN", 4, 1 },
|
|
{ "WAN_MODE", 3, 1 },
|
|
{ "RX_ENA", 1, 1 },
|
|
{ "TX_ENA", 0, 1 },
|
|
{ "MAC_PORT_MTIP_MAC_ADDR_0", 0x30a0c, 0 },
|
|
{ "MAC_PORT_MTIP_MAC_ADDR_1", 0x30a10, 0 },
|
|
{ "MAC_PORT_MTIP_FRM_LENGTH", 0x30a14, 0 },
|
|
{ "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x30a1c, 0 },
|
|
{ "AVAIL", 16, 16 },
|
|
{ "EMPTY", 0, 16 },
|
|
{ "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x30a20, 0 },
|
|
{ "AVAIL", 16, 16 },
|
|
{ "EMPTY", 0, 16 },
|
|
{ "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x30a24, 0 },
|
|
{ "AlmstFull", 16, 16 },
|
|
{ "AlmstEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x30a28, 0 },
|
|
{ "AlmstFull", 16, 16 },
|
|
{ "AlmstEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x30a2c, 0 },
|
|
{ "ENABLE", 8, 1 },
|
|
{ "ADDR", 0, 6 },
|
|
{ "MAC_PORT_MTIP_MAC_STATUS", 0x30a40, 0 },
|
|
{ "TS_AVAIL", 3, 1 },
|
|
{ "PHY_LOS", 2, 1 },
|
|
{ "RX_REM_FAULT", 1, 1 },
|
|
{ "RX_LOC_FAULT", 0, 1 },
|
|
{ "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x30a44, 0 },
|
|
{ "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x30a48, 0 },
|
|
{ "MAC_PORT_MTIP_INIT_CREDIT", 0x30a4c, 0 },
|
|
{ "MAC_PORT_MTIP_CURRENT_CREDIT", 0x30a50, 0 },
|
|
{ "MAC_PORT_RX_PAUSE_STATUS", 0x30a74, 0 },
|
|
{ "MAC_PORT_MTIP_TS_TIMESTAMP", 0x30a7c, 0 },
|
|
{ "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x30a80, 0 },
|
|
{ "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x30a84, 0 },
|
|
{ "MAC_PORT_AFRAMESRECEIVEDOK", 0x30a88, 0 },
|
|
{ "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x30a8c, 0 },
|
|
{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x30a90, 0 },
|
|
{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x30a94, 0 },
|
|
{ "MAC_PORT_AALIGNMENTERRORS", 0x30a98, 0 },
|
|
{ "MAC_PORT_AALIGNMENTERRORSHI", 0x30a9c, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x30aa0, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x30aa4, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x30aa8, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x30aac, 0 },
|
|
{ "MAC_PORT_AFRAMETOOLONGERRORS", 0x30ab0, 0 },
|
|
{ "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x30ab4, 0 },
|
|
{ "MAC_PORT_AINRANGELENGTHERRORS", 0x30ab8, 0 },
|
|
{ "MAC_PORT_AINRANGELENGTHERRORSHI", 0x30abc, 0 },
|
|
{ "MAC_PORT_VLANTRANSMITTEDOK", 0x30ac0, 0 },
|
|
{ "MAC_PORT_VLANTRANSMITTEDOKHI", 0x30ac4, 0 },
|
|
{ "MAC_PORT_VLANRECEIVEDOK", 0x30ac8, 0 },
|
|
{ "MAC_PORT_VLANRECEIVEDOKHI", 0x30acc, 0 },
|
|
{ "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x30ad0, 0 },
|
|
{ "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x30ad4, 0 },
|
|
{ "MAC_PORT_AOCTETSRECEIVEDOK", 0x30ad8, 0 },
|
|
{ "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x30adc, 0 },
|
|
{ "MAC_PORT_IFINUCASTPKTS", 0x30ae0, 0 },
|
|
{ "MAC_PORT_IFINUCASTPKTSHI", 0x30ae4, 0 },
|
|
{ "MAC_PORT_IFINMULTICASTPKTS", 0x30ae8, 0 },
|
|
{ "MAC_PORT_IFINMULTICASTPKTSHI", 0x30aec, 0 },
|
|
{ "MAC_PORT_IFINBROADCASTPKTS", 0x30af0, 0 },
|
|
{ "MAC_PORT_IFINBROADCASTPKTSHI", 0x30af4, 0 },
|
|
{ "MAC_PORT_IFOUTERRORS", 0x30af8, 0 },
|
|
{ "MAC_PORT_IFOUTERRORSHI", 0x30afc, 0 },
|
|
{ "MAC_PORT_IFOUTUCASTPKTS", 0x30b08, 0 },
|
|
{ "MAC_PORT_IFOUTUCASTPKTSHI", 0x30b0c, 0 },
|
|
{ "MAC_PORT_IFOUTMULTICASTPKTS", 0x30b10, 0 },
|
|
{ "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x30b14, 0 },
|
|
{ "MAC_PORT_IFOUTBROADCASTPKTS", 0x30b18, 0 },
|
|
{ "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x30b1c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSDROPEVENTS", 0x30b20, 0 },
|
|
{ "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x30b24, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOCTETS", 0x30b28, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOCTETSHI", 0x30b2c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS", 0x30b30, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTSHI", 0x30b34, 0 },
|
|
{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x30b38, 0 },
|
|
{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x30b3c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x30b40, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x30b44, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x30b48, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x30b4c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x30b50, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x30b54, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x30b58, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x30b5c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x30b60, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x30b64, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x30b68, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x30b6c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x30b70, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x30b74, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x30b78, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x30b7c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSJABBERS", 0x30b80, 0 },
|
|
{ "MAC_PORT_ETHERSTATSJABBERSHI", 0x30b84, 0 },
|
|
{ "MAC_PORT_ETHERSTATSFRAGMENTS", 0x30b88, 0 },
|
|
{ "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x30b8c, 0 },
|
|
{ "MAC_PORT_IFINERRORS", 0x30b90, 0 },
|
|
{ "MAC_PORT_IFINERRORSHI", 0x30b94, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x30b98, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x30b9c, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x30ba0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x30ba4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x30ba8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x30bac, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x30bb0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x30bb4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x30bb8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x30bbc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x30bc0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x30bc4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x30bc8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x30bcc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x30bd0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x30bd4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x30bd8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x30bdc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x30be0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x30be4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x30be8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x30bec, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x30bf0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x30bf4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x30bf8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x30bfc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x30c00, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x30c04, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x30c08, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x30c0c, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x30c10, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x30c14, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x30c18, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x30c1c, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x30c20, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x30c24, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_REVISION", 0x30d00, 0 },
|
|
{ "CUSTREV", 16, 16 },
|
|
{ "VER", 8, 8 },
|
|
{ "REV", 0, 8 },
|
|
{ "MAC_PORT_MTIP_1G10G_SCRATCH", 0x30d04, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_COMMAND_CONFIG", 0x30d08, 0 },
|
|
{ "SHORT_DISCARD", 25, 1 },
|
|
{ "REG_LOWP_RXEMPTY", 24, 1 },
|
|
{ "TX_LOWP_ENA", 23, 1 },
|
|
{ "TX_FLUSH", 22, 1 },
|
|
{ "SFD_ANY", 21, 1 },
|
|
{ "PAUSE_PFC_COMP", 20, 1 },
|
|
{ "PFC_MODE", 19, 1 },
|
|
{ "COL_CNT_ExT", 18, 1 },
|
|
{ "NO_LGTH_CHECK", 17, 1 },
|
|
{ "FORCE_SEND_IDLE", 16, 1 },
|
|
{ "PHY_TXENA", 15, 1 },
|
|
{ "RX_ERR_DISC", 14, 1 },
|
|
{ "CNTL_FRM_ENA", 13, 1 },
|
|
{ "SW_RESET", 12, 1 },
|
|
{ "TX_PAD_EN", 11, 1 },
|
|
{ "LOOP_ENA", 10, 1 },
|
|
{ "TX_ADDR_INS", 9, 1 },
|
|
{ "PAUSE_IGNORE", 8, 1 },
|
|
{ "PAUSE_FWD", 7, 1 },
|
|
{ "CRC_FWD", 6, 1 },
|
|
{ "PAD_EN", 5, 1 },
|
|
{ "PROMIS_EN", 4, 1 },
|
|
{ "WAN_MODE", 3, 1 },
|
|
{ "RX_ENAMAC", 1, 1 },
|
|
{ "TX_ENAMAC", 0, 1 },
|
|
{ "MAC_PORT_MTIP_1G10G_MAC_ADDR_0", 0x30d0c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_MAC_ADDR_1", 0x30d10, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU", 0x30d14, 0 },
|
|
{ "SET_LEN", 16, 16 },
|
|
{ "FRM_LEN_SET", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS", 0x30d1c, 0 },
|
|
{ "EMPTY", 16, 16 },
|
|
{ "AVAIL", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS", 0x30d20, 0 },
|
|
{ "EMPTY", 16, 16 },
|
|
{ "AVAIL", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E", 0x30d24, 0 },
|
|
{ "AlmostFull", 16, 16 },
|
|
{ "AlmostEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E", 0x30d28, 0 },
|
|
{ "AlmostFull", 16, 16 },
|
|
{ "AlmostEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD", 0x30d2c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS", 0x30d30, 0 },
|
|
{ "Clk_divisor", 7, 9 },
|
|
{ "ENA_CLAUSE", 6, 1 },
|
|
{ "PREAMBLE_DISABLE", 5, 1 },
|
|
{ "Hold_time_setting", 2, 3 },
|
|
{ "MDIO_read_error", 1, 1 },
|
|
{ "MDIO_Busy", 0, 1 },
|
|
{ "MAC_PORT_MTIP_1G10G_MDIO_COMMAND", 0x30d34, 0 },
|
|
{ "READ_MODE", 15, 1 },
|
|
{ "POST_INCR_READ", 14, 1 },
|
|
{ "Port_PHY_Addr", 5, 5 },
|
|
{ "Device_Reg_Addr", 0, 5 },
|
|
{ "MAC_PORT_MTIP_1G10G_MDIO_DATA", 0x30d38, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_MDIO_REGADDR", 0x30d3c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_STATUS", 0x30d40, 0 },
|
|
{ "RX_LINT_FAULT", 7, 1 },
|
|
{ "RX_EMPTY", 6, 1 },
|
|
{ "TX_EMPTY", 5, 1 },
|
|
{ "RX_LOWP", 4, 1 },
|
|
{ "TS_AVAIL", 3, 1 },
|
|
{ "PHY_LOS", 2, 1 },
|
|
{ "RX_REM_FAULT", 1, 1 },
|
|
{ "RX_LOC_FAULT", 0, 1 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH", 0x30d44, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER", 0x30d48, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_INIT_CREDIT", 0x30d4c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA", 0x30d54, 0 },
|
|
{ "CL1_PAUSE_QUANTA", 16, 16 },
|
|
{ "CL0_PAUSE_QUANTA", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA", 0x30d58, 0 },
|
|
{ "CL3_PAUSE_QUANTA", 16, 16 },
|
|
{ "CL2_PAUSE_QUANTA", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA", 0x30d5c, 0 },
|
|
{ "CL5_PAUSE_QUANTA", 16, 16 },
|
|
{ "CL4_PAUSE_QUANTA", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA", 0x30d60, 0 },
|
|
{ "CL7_PAUSE_QUANTA", 16, 16 },
|
|
{ "CL6_PAUSE_QUANTA", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH", 0x30d64, 0 },
|
|
{ "CL1_QUANTA_THRESH", 16, 16 },
|
|
{ "CL0_QUANTA_THRESH", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH", 0x30d68, 0 },
|
|
{ "CL3_QUANTA_THRESH", 16, 16 },
|
|
{ "CL2_QUANTA_THRESH", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH", 0x30d6c, 0 },
|
|
{ "CL5_QUANTA_THRESH", 16, 16 },
|
|
{ "CL4_QUANTA_THRESH", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH", 0x30d70, 0 },
|
|
{ "CL7_QUANTA_THRESH", 16, 16 },
|
|
{ "CL6_QUANTA_THRESH", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS", 0x30d74, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TS_TIMESTAMP", 0x30d7c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_STATN_CONFIG", 0x30de0, 0 },
|
|
{ "CLEAR", 2, 1 },
|
|
{ "CLEAR_ON_READ", 1, 1 },
|
|
{ "SATURATE", 0, 1 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS", 0x30e00, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI", 0x30e04, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_OCTETSOK", 0x30e08, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI", 0x30e0c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS", 0x30e10, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI", 0x30e14, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES", 0x30e18, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI", 0x30e1c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_FRAMESOK", 0x30e20, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI", 0x30e24, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_CRCERRORS", 0x30e28, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI", 0x30e2c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_VLANOK", 0x30e30, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_VLANOKHI", 0x30e34, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINERRORS", 0x30e38, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI", 0x30e3c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS", 0x30e40, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI", 0x30e44, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS", 0x30e48, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI", 0x30e4c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS", 0x30e50, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI", 0x30e54, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS", 0x30e58, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI", 0x30e5c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS", 0x30e60, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI", 0x30e64, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS", 0x30e68, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI", 0x30e6c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS", 0x30e70, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI", 0x30e74, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS", 0x30e78, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI", 0x30e7c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS", 0x30e80, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI", 0x30e84, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS", 0x30e88, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI", 0x30e8c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS", 0x30e90, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI", 0x30e94, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS", 0x30e98, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x30e9c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX", 0x30ea0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI", 0x30ea4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS", 0x30ea8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI", 0x30eac, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS", 0x30eb0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI", 0x30eb4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS", 0x30eb8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI", 0x30ebc, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED", 0x30ec0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI", 0x30ec4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG", 0x30ec8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI", 0x30ecc, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS", 0x30ed0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI", 0x30ed4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS", 0x30f00, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI", 0x30f04, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_OCTETSOK", 0x30f08, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI", 0x30f0c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS", 0x30f10, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI", 0x30f14, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES", 0x30f18, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI", 0x30f1c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_FRAMESOK", 0x30f20, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI", 0x30f24, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_CRCERRORS", 0x30f28, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI", 0x30f2c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_VLANOK", 0x30f30, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_VLANOKHI", 0x30f34, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS", 0x30f38, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI", 0x30f3c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS", 0x30f40, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI", 0x30f44, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS", 0x30f48, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI", 0x30f4c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS", 0x30f50, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI", 0x30f54, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS", 0x30f58, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI", 0x30f5c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS", 0x30f60, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI", 0x30f64, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS", 0x30f68, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI", 0x30f6c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS", 0x30f70, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI", 0x30f74, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS", 0x30f78, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI", 0x30f7c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS", 0x30f80, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI", 0x30f84, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS", 0x30f88, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI", 0x30f8c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS", 0x30f90, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI", 0x30f94, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS", 0x30f98, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x30f9c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU", 0x30fa0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI", 0x30fa4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES", 0x30fc0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI", 0x30fc4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_IF_MODE", 0x31000, 0 },
|
|
{ "MII_ENA_10", 4, 1 },
|
|
{ "IF_MODE", 0, 2 },
|
|
{ "MAC_PORT_MTIP_1G10G_IF_STATUS", 0x31004, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0", 0x31080, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI", 0x31084, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1", 0x31088, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI", 0x3108c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2", 0x31090, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI", 0x31094, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3", 0x31098, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI", 0x3109c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4", 0x310a0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI", 0x310a4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5", 0x310a8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI", 0x310ac, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6", 0x310b0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI", 0x310b4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7", 0x310b8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI", 0x310bc, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0", 0x310c0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI", 0x310c4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1", 0x310c8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI", 0x310cc, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2", 0x310d0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI", 0x310d4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3", 0x310d8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI", 0x310dc, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4", 0x310e0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI", 0x310e4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5", 0x310e8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI", 0x310ec, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6", 0x310f0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI", 0x310f4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7", 0x310f8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI", 0x310fc, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_CONTROL", 0x31200, 0 },
|
|
{ "Reset", 15, 1 },
|
|
{ "Loopback", 14, 1 },
|
|
{ "Speed_Sel", 13, 1 },
|
|
{ "AN_EN", 12, 1 },
|
|
{ "PWR_DWN", 11, 1 },
|
|
{ "Isolate", 10, 1 },
|
|
{ "AN_RESTART", 9, 1 },
|
|
{ "DUPLEx_MODE", 8, 1 },
|
|
{ "Collision_Test", 7, 1 },
|
|
{ "Speed_Sel1", 6, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_STATUS", 0x31204, 0 },
|
|
{ "100BaseT4", 15, 1 },
|
|
{ "100BasexFullDplx", 14, 1 },
|
|
{ "100BasexHalfDplx", 13, 1 },
|
|
{ "10MbpsFullDplx", 12, 1 },
|
|
{ "10MbpsHalfDplx", 11, 1 },
|
|
{ "100BaseT2FullDplx", 10, 1 },
|
|
{ "100BaseT2HalfDplx", 9, 1 },
|
|
{ "ExtdStatus", 8, 1 },
|
|
{ "AN_Complete", 5, 1 },
|
|
{ "REM_FAULT", 4, 1 },
|
|
{ "AN_Ability", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "JabberDetect", 1, 1 },
|
|
{ "ExtdCapability", 0, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x31208, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x3120c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x31210, 0 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "RF2", 13, 1 },
|
|
{ "RF1", 12, 1 },
|
|
{ "PS2", 8, 1 },
|
|
{ "PS1", 7, 1 },
|
|
{ "HD", 6, 1 },
|
|
{ "FD", 5, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x31214, 0 },
|
|
{ "CuLinkStatus", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "CuDplxStatus", 12, 1 },
|
|
{ "CuSpeed", 10, 2 },
|
|
{ "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x31218, 0 },
|
|
{ "Next_Page_Able", 2, 1 },
|
|
{ "PAGE_RECEIVE", 1, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_NP_TX", 0x3121c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_LP_NP_RX", 0x31220, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x3123c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_SCRATCH", 0x31240, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_REV", 0x31244, 0 },
|
|
{ "CUSTREV", 16, 16 },
|
|
{ "VER", 8, 8 },
|
|
{ "REV", 0, 8 },
|
|
{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x31248, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x3124c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_IF_MODE", 0x31250, 0 },
|
|
{ "SGMII_DUPLEx", 4, 1 },
|
|
{ "SGMII_SPEED", 2, 2 },
|
|
{ "USE_SGMII_AN", 1, 1 },
|
|
{ "SGMII_ENA", 0, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_DECODE_ERROR", 0x31254, 0 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_CONTROL_1", 0x31300, 0 },
|
|
{ "Reset", 15, 1 },
|
|
{ "Loopback", 14, 1 },
|
|
{ "Speed_SEL", 13, 1 },
|
|
{ "Low_Power", 11, 1 },
|
|
{ "Speed_SEL1", 6, 1 },
|
|
{ "Speed_SEL2", 2, 4 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_STATUS_1", 0x31304, 0 },
|
|
{ "TX_LPI", 11, 1 },
|
|
{ "RX_LPI", 10, 1 },
|
|
{ "TX_LPI_ACTIVE", 9, 1 },
|
|
{ "RX_LPI_ACTIVE", 8, 1 },
|
|
{ "Fault", 7, 1 },
|
|
{ "PCS_RX_Link_STAT", 2, 1 },
|
|
{ "Low_power_Ability", 1, 1 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1", 0x31308, 0 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2", 0x3130c, 0 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY", 0x31310, 0 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO", 0x31314, 0 },
|
|
{ "Auto_Negotiation_Present", 7, 1 },
|
|
{ "DTE_xS_present", 5, 1 },
|
|
{ "PHY_xS_present", 4, 1 },
|
|
{ "PCS_present", 3, 1 },
|
|
{ "WIS_present", 2, 1 },
|
|
{ "PMD_PMA_Present", 1, 1 },
|
|
{ "Clause_22_Reg_Present", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI", 0x31318, 0 },
|
|
{ "Auto_Negotiation_Present", 7, 1 },
|
|
{ "DTE_xS_present", 5, 1 },
|
|
{ "PHY_xS_present", 4, 1 },
|
|
{ "PCS_present", 3, 1 },
|
|
{ "WIS_present", 2, 1 },
|
|
{ "PMD_PMA_Present", 1, 1 },
|
|
{ "Clause_22_Reg_Present", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_CONTROL_2", 0x3131c, 0 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_STATUS_2", 0x31320, 0 },
|
|
{ "Device_Present", 14, 2 },
|
|
{ "Transmit_Fault", 11, 1 },
|
|
{ "Receive_Fault", 10, 1 },
|
|
{ "10GBASE_W_Capable", 2, 1 },
|
|
{ "10GBASE_x_Capable", 1, 1 },
|
|
{ "10GBASE_R_Capable", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO", 0x31338, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI", 0x3133c, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1", 0x31380, 0 },
|
|
{ "10GBASE_R_RX_Link_Status", 12, 1 },
|
|
{ "PRBS9_Pttrn_Tstng_Ability", 3, 1 },
|
|
{ "PRBS31_Pttrn_Tstng_Ability", 2, 1 },
|
|
{ "10GBASE_R_PCS_High_BER", 1, 1 },
|
|
{ "10GBASE_R_PCS_Block_Lock", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2", 0x31384, 0 },
|
|
{ "Latched_Block_Lock", 15, 1 },
|
|
{ "Latched_High_BER", 14, 1 },
|
|
{ "BERBER_Counter", 8, 6 },
|
|
{ "ErrBlkCnt", 0, 8 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0", 0x31388, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1", 0x3138c, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2", 0x31390, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3", 0x31394, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0", 0x31398, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1", 0x3139c, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2", 0x313a0, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3", 0x313a4, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL", 0x313a8, 0 },
|
|
{ "PRBS9_TX_Tst_Pttrn_En", 6, 1 },
|
|
{ "PRBS31_RX_Tst_Pttrn_En", 5, 1 },
|
|
{ "PRBS31_TX_Tst_Pttrn_En", 4, 1 },
|
|
{ "TX_Test_Pattern_En", 3, 1 },
|
|
{ "RX_Test_Pattern_En", 2, 1 },
|
|
{ "Test_Pattern_Select", 1, 1 },
|
|
{ "Data_Pattern_Select", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER", 0x313ac, 0 },
|
|
{ "MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS", 0x313b4, 0 },
|
|
{ "Transmit_FIFO_Fault", 1, 1 },
|
|
{ "Receive_FIFO_Fault", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_CONTROL_1", 0x31400, 0 },
|
|
{ "RESET", 15, 1 },
|
|
{ "Loopback", 14, 1 },
|
|
{ "Speed_selection", 13, 1 },
|
|
{ "Low_power", 11, 1 },
|
|
{ "Speed_selection1", 6, 1 },
|
|
{ "Speed_selection2", 2, 4 },
|
|
{ "MAC_PORT_MTIP_KR4_STATUS_1", 0x31404, 0 },
|
|
{ "Fault", 7, 1 },
|
|
{ "Receive_link_STAT", 2, 1 },
|
|
{ "Low_power_ability", 1, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_DEVICE_ID0", 0x31408, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_DEVICE_ID1", 0x3140c, 0 },
|
|
{ "DEVICE_ID1", 16, 16 },
|
|
{ "MAC_PORT_MTIP_KR4_SPEED_ABILITY", 0x31410, 0 },
|
|
{ "100G_capable", 3, 1 },
|
|
{ "40G_capable", 2, 1 },
|
|
{ "10PASS_TS_2Base_TL_capable", 1, 1 },
|
|
{ "10G_capable", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1", 0x31414, 0 },
|
|
{ "TC_present", 6, 1 },
|
|
{ "DTE_xS_present", 5, 1 },
|
|
{ "PHY_xS_present", 4, 1 },
|
|
{ "PCS_present", 3, 1 },
|
|
{ "WIS_present", 2, 1 },
|
|
{ "PMD_PMA_present", 1, 1 },
|
|
{ "Clause_22_reg", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2", 0x31418, 0 },
|
|
{ "Vendor_specific_device", 15, 1 },
|
|
{ "Vendor_specific_device1", 14, 1 },
|
|
{ "Clause_22_ExT", 13, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_CONTROL_2", 0x3141c, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_STATUS_2", 0x31420, 0 },
|
|
{ "Device_present", 14, 2 },
|
|
{ "Transmit_fault", 11, 1 },
|
|
{ "Receive_fault", 10, 1 },
|
|
{ "100GBase_R_capable", 5, 1 },
|
|
{ "40GBase_R_capable", 4, 1 },
|
|
{ "10GBase_T_capable", 3, 1 },
|
|
{ "10GBase_W_capable", 2, 1 },
|
|
{ "10GBase_x_capable", 1, 1 },
|
|
{ "10GBase_R_capable", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_PKG_ID0", 0x31438, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_PKG_ID1", 0x3143c, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_BASE_R_STATUS_1", 0x31480, 0 },
|
|
{ "RX_link_status", 12, 1 },
|
|
{ "High_BER", 1, 1 },
|
|
{ "Block_lock", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_BASE_R_STATUS_2", 0x31484, 0 },
|
|
{ "Latched_bl_lk", 15, 1 },
|
|
{ "Latched_hg_br", 14, 1 },
|
|
{ "Ber_cnt", 8, 6 },
|
|
{ "Err_bl_cnt", 0, 8 },
|
|
{ "MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL", 0x314a8, 0 },
|
|
{ "TX_TP_EN", 3, 1 },
|
|
{ "RX_TP_EN", 2, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT", 0x314ac, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT", 0x314b0, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT", 0x314b4, 0 },
|
|
{ "HI_ORDER_CNT_EN", 15, 1 },
|
|
{ "ERR_BLK_CNTR", 0, 14 },
|
|
{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1", 0x314c8, 0 },
|
|
{ "LANE_ALIGN_STATUS", 12, 1 },
|
|
{ "LANE_3_BLK_LCK", 3, 1 },
|
|
{ "LANE_2_BLK_LC32_6431K", 2, 1 },
|
|
{ "LANE_1_BLK_LCK", 1, 1 },
|
|
{ "LANE_0_BLK_LCK", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2", 0x314cc, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3", 0x314d0, 0 },
|
|
{ "LANE_3_ALIGN_MRKR_LCK", 3, 1 },
|
|
{ "LANE_2_ALIGN_MRKR_LCK", 2, 1 },
|
|
{ "LANE_1_ALIGN_MRKR_LCK", 1, 1 },
|
|
{ "LANE_0_ALIGN_MRKR_LCK", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4", 0x314d4, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0", 0x31720, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1", 0x31724, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2", 0x31728, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3", 0x3172c, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_LANE_0_MAPPING", 0x31a40, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_LANE_1_MAPPING", 0x31a44, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_LANE_2_MAPPING", 0x31a48, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_LANE_3_MAPPING", 0x31a4c, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_SCRATCH", 0x31af0, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_CORE_REVISION", 0x31af4, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_VL_INTVL", 0x31af8, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_TX_LANE_THRESH", 0x31afc, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_CONTROL_1", 0x31b00, 0 },
|
|
{ "Reset", 15, 1 },
|
|
{ "Loopback", 14, 1 },
|
|
{ "Speed_selection", 13, 1 },
|
|
{ "Low_power", 11, 1 },
|
|
{ "Speed_selection1", 6, 1 },
|
|
{ "Speed_selection2", 2, 4 },
|
|
{ "MAC_PORT_MTIP_CR4_STATUS_1", 0x31b04, 0 },
|
|
{ "Fault", 7, 1 },
|
|
{ "RX_Link_Status", 2, 1 },
|
|
{ "Low_power_ability", 1, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_DEVICE_ID0", 0x31b08, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_DEVICE_ID1", 0x31b0c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_SPEED_ABILITY", 0x31b10, 0 },
|
|
{ "100G_capable", 8, 1 },
|
|
{ "40G_capable", 7, 1 },
|
|
{ "10PASS_TS_2Base_TL_capable", 1, 1 },
|
|
{ "10G_capable", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1", 0x31b14, 0 },
|
|
{ "TC_present", 6, 1 },
|
|
{ "DTE_xS_present", 5, 1 },
|
|
{ "PHY_xS_present", 4, 1 },
|
|
{ "PCS_present", 3, 1 },
|
|
{ "WIS_present", 2, 1 },
|
|
{ "PMD_PMA_present", 1, 1 },
|
|
{ "Clause22reg_present", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2", 0x31b18, 0 },
|
|
{ "VSD_2_PRESENT", 15, 1 },
|
|
{ "VSD_1_PRESENT", 14, 1 },
|
|
{ "Clause22_ExT_Present", 13, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_CONTROL_2", 0x31b1c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_STATUS_2", 0x31b20, 0 },
|
|
{ "Device_present", 14, 2 },
|
|
{ "Transmit_fault", 11, 1 },
|
|
{ "Receive_fault", 10, 1 },
|
|
{ "100GBase_R_capable", 5, 1 },
|
|
{ "40GBase_R_capable", 4, 1 },
|
|
{ "10GBase_T_capable", 3, 1 },
|
|
{ "10GBase_W_capable", 2, 1 },
|
|
{ "10GBase_x_capable", 1, 1 },
|
|
{ "10GBase_R_capable", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_PKG_ID0", 0x31b38, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_PKG_ID1", 0x31b3c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BASE_R_STATUS_1", 0x31b80, 0 },
|
|
{ "RX_Link_STAT", 12, 1 },
|
|
{ "High_BER", 1, 1 },
|
|
{ "Block_Lock", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_BASE_R_STATUS_2", 0x31b84, 0 },
|
|
{ "Latched_block_lock", 15, 1 },
|
|
{ "Latched_high_BER", 14, 1 },
|
|
{ "BER_counter", 8, 6 },
|
|
{ "Errored_blocks_cntr", 0, 8 },
|
|
{ "MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL", 0x31ba8, 0 },
|
|
{ "Scrambled_ID_TP_EN", 7, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT", 0x31bac, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT", 0x31bb0, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT", 0x31bb4, 0 },
|
|
{ "Hi_ORDER_CNT_Present", 15, 1 },
|
|
{ "ERR_BLKS_CNTR", 0, 14 },
|
|
{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1", 0x31bc8, 0 },
|
|
{ "LANE_ALIGN_STAT", 12, 1 },
|
|
{ "Lane_7_blck_lck", 7, 1 },
|
|
{ "Lane_6_blck_lck", 6, 1 },
|
|
{ "Lane_5_blck_lck", 5, 1 },
|
|
{ "Lane_4_blck_lck", 4, 1 },
|
|
{ "Lane_3_blck_lck", 3, 1 },
|
|
{ "Lane_2_blck_lck", 2, 1 },
|
|
{ "Lane_1_blck_lck", 1, 1 },
|
|
{ "Lane_0_blck_lck", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2", 0x31bcc, 0 },
|
|
{ "Lane_19_blck_lck", 11, 1 },
|
|
{ "Lane_18_blck_lck", 10, 1 },
|
|
{ "Lane_17_blck_lck", 9, 1 },
|
|
{ "Lane_16_blck_lck", 8, 1 },
|
|
{ "Lane_15_blck_lck", 7, 1 },
|
|
{ "Lane_14_blck_lck", 6, 1 },
|
|
{ "Lane_13_blck_lck", 5, 1 },
|
|
{ "Lane_12_blck_lck", 4, 1 },
|
|
{ "Lane_11_blck_lck", 3, 1 },
|
|
{ "Lane_10_blck_lck", 2, 1 },
|
|
{ "Lane_9_blck_lck", 1, 1 },
|
|
{ "Lane_8_blck_lck", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3", 0x31bd0, 0 },
|
|
{ "Lane7_algn_mrkr_lck", 7, 1 },
|
|
{ "Lane6_algn_mrkr_lck", 6, 1 },
|
|
{ "Lane5_algn_mrkr_lck", 5, 1 },
|
|
{ "Lane4_algn_mrkr_lck", 4, 1 },
|
|
{ "Lane3_algn_mrkr_lck", 3, 1 },
|
|
{ "Lane2_algn_mrkr_lck", 2, 1 },
|
|
{ "Lane1_algn_mrkr_lck", 1, 1 },
|
|
{ "Lane0_algn_mrkr_lck", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4", 0x31bd4, 0 },
|
|
{ "Lane19_algn_mrkr_lck", 11, 1 },
|
|
{ "Lane18_algn_mrkr_lck", 10, 1 },
|
|
{ "Lane17_algn_mrkr_lck", 9, 1 },
|
|
{ "Lane16_algn_mrkr_lck", 8, 1 },
|
|
{ "Lane15_algn_mrkr_lck", 7, 1 },
|
|
{ "Lane14_algn_mrkr_lck", 6, 1 },
|
|
{ "Lane13_algn_mrkr_lck", 5, 1 },
|
|
{ "Lane12_algn_mrkr_lck", 4, 1 },
|
|
{ "Lane11_algn_mrkr_lck", 3, 1 },
|
|
{ "Lane10_algn_mrkr_lck", 2, 1 },
|
|
{ "Lane9_algn_mrkr_lck", 1, 1 },
|
|
{ "Lane8_algn_mrkr_lck", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0", 0x31e20, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1", 0x31e24, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2", 0x31e28, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3", 0x31e2c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4", 0x31e30, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5", 0x31e34, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6", 0x31e38, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7", 0x31e3c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8", 0x31e40, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9", 0x31e44, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10", 0x31e48, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11", 0x31e4c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12", 0x31e50, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13", 0x31e54, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14", 0x31e58, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15", 0x31e5c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16", 0x31e60, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17", 0x31e64, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18", 0x31e68, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19", 0x31e6c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_0_MAPPING", 0x32140, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_1_MAPPING", 0x32144, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_2_MAPPING", 0x32148, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_3_MAPPING", 0x3214c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_4_MAPPING", 0x32150, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_5_MAPPING", 0x32154, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_6_MAPPING", 0x32158, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_7_MAPPING", 0x3215c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_8_MAPPING", 0x32160, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_9_MAPPING", 0x32164, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_10_MAPPING", 0x32168, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_11_MAPPING", 0x3216c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_12_MAPPING", 0x32170, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_13_MAPPING", 0x32174, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_14_MAPPING", 0x32178, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_15_MAPPING", 0x3217c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_16_MAPPING", 0x32180, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_17_MAPPING", 0x32184, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_18_MAPPING", 0x32188, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_19_MAPPING", 0x3218c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_SCRATCH", 0x321f0, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_CORE_REVISION", 0x321f4, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_CONTROL", 0x32200, 0 },
|
|
{ "RS_FEC_Bypass_Error_Indication", 1, 1 },
|
|
{ "RS_FEC_Bypass_Correction", 0, 1 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_STATUS", 0x32204, 0 },
|
|
{ "RS_FEC_PCS_align_status", 15, 1 },
|
|
{ "fec_align_status", 14, 1 },
|
|
{ "RS_FEC_high_SER", 2, 1 },
|
|
{ "RS_FEC_bypass_error_indication_ability", 1, 1 },
|
|
{ "RS_FEC_bypass_correction_ability", 0, 1 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_CCW_LO", 0x32208, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_CCW_HI", 0x3220c, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_NCCW_LO", 0x32210, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_NCCW_HI", 0x32214, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI", 0x32218, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO", 0x32228, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI", 0x3222c, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO", 0x32230, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI", 0x32234, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO", 0x32238, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI", 0x3223c, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO", 0x32240, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI", 0x32244, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL", 0x32400, 0 },
|
|
{ "RS_FEC_enabled_status", 15, 1 },
|
|
{ "RS_FEC_Enable", 2, 1 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1", 0x32404, 0 },
|
|
{ "deskew_empty", 12, 4 },
|
|
{ "fec_align_status_lh", 10, 1 },
|
|
{ "tx_dp_overflow", 9, 1 },
|
|
{ "rx_dp_overflow", 8, 1 },
|
|
{ "tx_datapath_restart", 7, 1 },
|
|
{ "rx_datapath_restart", 6, 1 },
|
|
{ "marker_check_restart", 5, 1 },
|
|
{ "fec_align_status_ll", 4, 1 },
|
|
{ "amps_lock", 0, 4 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2", 0x32408, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION", 0x3240c, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY", 0x32410, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS", 0x32414, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN", 0x32418, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER", 0x3241c, 0 },
|
|
{ "MAC_PORT_MTIP_FEC_ABILITY", 0x32618, 0 },
|
|
{ "BASE_R_FEC_Error_Indication_Ability", 1, 1 },
|
|
{ "BASE_R_FEC_Ability", 0, 1 },
|
|
{ "MAC_PORT_FEC_CONTROL", 0x3261c, 0 },
|
|
{ "fec_en_err_ind", 1, 1 },
|
|
{ "fec_en", 0, 1 },
|
|
{ "MAC_PORT_FEC_STATUS", 0x32620, 0 },
|
|
{ "FEC_LOCKED0", 1, 4 },
|
|
{ "FEC_LOCKED", 0, 1 },
|
|
{ "MAC_PORT_MTIP_FEC0_CERR_CNT_0", 0x32624, 0 },
|
|
{ "MAC_PORT_MTIP_FEC0_CERR_CNT_1", 0x32628, 0 },
|
|
{ "MAC_PORT_MTIP_FEC0_NCERR_CNT_0", 0x3262c, 0 },
|
|
{ "MAC_PORT_MTIP_FEC0_NCERR_CNT_1", 0x32630, 0 },
|
|
{ "MAC_PORT_MTIP_FEC_STATUS1", 0x32664, 0 },
|
|
{ "FEC_LOCKED0", 1, 4 },
|
|
{ "FEC_LOCKED", 0, 1 },
|
|
{ "MAC_PORT_MTIP_FEC1_CERR_CNT_0", 0x32668, 0 },
|
|
{ "MAC_PORT_MTIP_FEC1_CERR_CNT_1", 0x3266c, 0 },
|
|
{ "MAC_PORT_MTIP_FEC1_NCERR_CNT_0", 0x32670, 0 },
|
|
{ "MAC_PORT_MTIP_FEC1_NCERR_CNT_1", 0x32674, 0 },
|
|
{ "MAC_PORT_MTIP_FEC_STATUS2", 0x326a8, 0 },
|
|
{ "FEC_LOCKED0", 1, 4 },
|
|
{ "FEC_LOCKED", 0, 1 },
|
|
{ "MAC_PORT_MTIP_FEC2_CERR_CNT_0", 0x326ac, 0 },
|
|
{ "MAC_PORT_MTIP_FEC2_CERR_CNT_1", 0x326b0, 0 },
|
|
{ "MAC_PORT_MTIP_FEC2_NCERR_CNT_0", 0x326b4, 0 },
|
|
{ "MAC_PORT_MTIP_FEC2_NCERR_CNT_1", 0x326b8, 0 },
|
|
{ "MAC_PORT_MTIP_FEC_STATUS3", 0x326ec, 0 },
|
|
{ "FEC_LOCKED0", 1, 4 },
|
|
{ "FEC_LOCKED", 0, 1 },
|
|
{ "MAC_PORT_MTIP_FEC3_CERR_CNT_0", 0x326f0, 0 },
|
|
{ "MAC_PORT_MTIP_FEC3_CERR_CNT_1", 0x326f4, 0 },
|
|
{ "MAC_PORT_MTIP_FEC3_NCERR_CNT_0", 0x326f8, 0 },
|
|
{ "MAC_PORT_MTIP_FEC3_NCERR_CNT_1", 0x326fc, 0 },
|
|
{ "MAC_PORT_BEAN_CTL", 0x32c00, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS", 0x32c04, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0", 0x32c08, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1", 0x32c0c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2", 0x32c10, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0", 0x32c14, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1", 0x32c18, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2", 0x32c1c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT", 0x32c20, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0", 0x32c24, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1", 0x32c28, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2", 0x32c2c, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0", 0x32c30, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1", 0x32c34, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2", 0x32c38, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS", 0x32c3c, 0 },
|
|
{ "100GCR4", 11, 1 },
|
|
{ "100GKR4", 10, 1 },
|
|
{ "100GKP4", 9, 1 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ", 0x32a00, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C3", 6, 2 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT", 0x32a04, 0 },
|
|
{ "T5_AE0_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE0_RXSTAT_LSNA", 14, 1 },
|
|
{ "T5_AE0_RXSTAT_FEC", 13, 1 },
|
|
{ "T5_AE0_RXSTAT_TF", 12, 1 },
|
|
{ "T5_AE0_RXSTAT_C3", 6, 2 },
|
|
{ "T5_AE0_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE0_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE0_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ", 0x32a08, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "TXREQ_FEC", 11, 1 },
|
|
{ "T5_TXREQ_C3", 6, 2 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT", 0x32a0c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C3", 6, 2 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE", 0x32a10, 0 },
|
|
{ "SET_WAIT_TIMER", 13, 2 },
|
|
{ "C2_C3_STATE_SEL", 12, 1 },
|
|
{ "FFE4_EN", 11, 1 },
|
|
{ "FEC_REQUEST", 10, 1 },
|
|
{ "FEC_SUPPORTED", 9, 1 },
|
|
{ "TX_FIXED", 8, 1 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL", 0x32a14, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL", 0x32a18, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE", 0x32a1c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_1", 0x32a20, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C3", 6, 2 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_1", 0x32a24, 0 },
|
|
{ "T5_AE1_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE1_RXSTAT_LSNA", 14, 1 },
|
|
{ "T5_AE1_RXSTAT_FEC", 13, 1 },
|
|
{ "T5_AE1_RXSTAT_TF", 12, 1 },
|
|
{ "T5_AE1_RXSTAT_C3", 6, 2 },
|
|
{ "T5_AE1_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE1_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE1_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_1", 0x32a28, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "TXREQ_FEC", 11, 1 },
|
|
{ "T5_TXREQ_C3", 6, 2 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_1", 0x32a2c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C3", 6, 2 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_1", 0x32a30, 0 },
|
|
{ "SET_WAIT_TIMER", 13, 2 },
|
|
{ "C2_C3_STATE_SEL", 12, 1 },
|
|
{ "FFE4_EN", 11, 1 },
|
|
{ "FEC_REQUEST", 10, 1 },
|
|
{ "FEC_SUPPORTED", 9, 1 },
|
|
{ "TX_FIXED", 8, 1 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_1", 0x32a34, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_1", 0x32a38, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_1", 0x32a3c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_2", 0x32a40, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C3", 6, 2 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_2", 0x32a44, 0 },
|
|
{ "T5_AE2_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE2_RXSTAT_LSNA", 14, 1 },
|
|
{ "T5_AE2_RXSTAT_FEC", 13, 1 },
|
|
{ "T5_AE2_RXSTAT_TF", 12, 1 },
|
|
{ "T5_AE2_RXSTAT_C3", 6, 2 },
|
|
{ "T5_AE2_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE2_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE2_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_2", 0x32a48, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "TXREQ_FEC", 11, 1 },
|
|
{ "T5_TXREQ_C3", 6, 2 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_2", 0x32a4c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C3", 6, 2 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_2", 0x32a50, 0 },
|
|
{ "SET_WAIT_TIMER", 13, 2 },
|
|
{ "C2_C3_STATE_SEL", 12, 1 },
|
|
{ "FFE4_EN", 11, 1 },
|
|
{ "FEC_REQUEST", 10, 1 },
|
|
{ "FEC_SUPPORTED", 9, 1 },
|
|
{ "TX_FIXED", 8, 1 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_2", 0x32a54, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_2", 0x32a58, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_2", 0x32a5c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_3", 0x32a60, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C3", 6, 2 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_3", 0x32a64, 0 },
|
|
{ "T5_AE3_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE3_RXSTAT_LSNA", 14, 1 },
|
|
{ "T5_AE3_RXSTAT_FEC", 13, 1 },
|
|
{ "T5_AE3_RXSTAT_TF", 12, 1 },
|
|
{ "T5_AE3_RXSTAT_C3", 6, 2 },
|
|
{ "T5_AE3_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE3_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE3_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_3", 0x32a68, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "TXREQ_FEC", 11, 1 },
|
|
{ "T5_TXREQ_C3", 6, 2 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_3", 0x32a6c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C3", 6, 2 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_3", 0x32a70, 0 },
|
|
{ "SET_WAIT_TIMER", 13, 2 },
|
|
{ "C2_C3_STATE_SEL", 12, 1 },
|
|
{ "FFE4_EN", 11, 1 },
|
|
{ "FEC_REQUEST", 10, 1 },
|
|
{ "FEC_SUPPORTED", 9, 1 },
|
|
{ "TX_FIXED", 8, 1 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_3", 0x32a74, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_3", 0x32a78, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_3", 0x32a7c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_TX_DIS", 0x32a80, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL", 0x32a84, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET", 0x32a88, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS", 0x32a8c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_1", 0x32a90, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_1", 0x32a94, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_1", 0x32a98, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_1", 0x32a9c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_2", 0x32aa0, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_2", 0x32aa4, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_2", 0x32aa8, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_2", 0x32aac, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_3", 0x32ab0, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_3", 0x32ab4, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_3", 0x32ab8, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_3", 0x32abc, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x32b00, 0 },
|
|
{ "INIT_METH", 12, 4 },
|
|
{ "INIT_CNT", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_N0", 5, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x32b04, 0 },
|
|
{ "FEC_CNV", 15, 1 },
|
|
{ "EN_RETRY", 14, 1 },
|
|
{ "DPC_METH", 12, 2 },
|
|
{ "EN_P2", 11, 1 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_0", 0x32b08, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x32b0c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT5", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_0", 0x32b10, 0 },
|
|
{ "CTRL_STAT", 8, 5 },
|
|
{ "NEU_STATE", 4, 4 },
|
|
{ "CTRL_STATE", 0, 4 },
|
|
{ "MAC_PORT_AET_STATUS_20", 0x32b14, 0 },
|
|
{ "MAC_PORT_AET_LIMITS0", 0x32b18, 0 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x32b20, 0 },
|
|
{ "INIT_METH", 12, 4 },
|
|
{ "INIT_CNT", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_N0", 5, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x32b24, 0 },
|
|
{ "FEC_CNV", 15, 1 },
|
|
{ "EN_RETRY", 14, 1 },
|
|
{ "DPC_METH", 12, 2 },
|
|
{ "EN_P2", 11, 1 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_1", 0x32b28, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x32b2c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT5", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_1", 0x32b30, 0 },
|
|
{ "CTRL_STAT", 8, 5 },
|
|
{ "NEU_STATE", 4, 4 },
|
|
{ "CTRL_STATE", 0, 4 },
|
|
{ "MAC_PORT_AET_STATUS_21", 0x32b34, 0 },
|
|
{ "MAC_PORT_AET_LIMITS1", 0x32b38, 0 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x32b40, 0 },
|
|
{ "INIT_METH", 12, 4 },
|
|
{ "INIT_CNT", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_N0", 5, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x32b44, 0 },
|
|
{ "FEC_CNV", 15, 1 },
|
|
{ "EN_RETRY", 14, 1 },
|
|
{ "DPC_METH", 12, 2 },
|
|
{ "EN_P2", 11, 1 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_2", 0x32b48, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x32b4c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT5", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_2", 0x32b50, 0 },
|
|
{ "CTRL_STAT", 8, 5 },
|
|
{ "NEU_STATE", 4, 4 },
|
|
{ "CTRL_STATE", 0, 4 },
|
|
{ "MAC_PORT_AET_STATUS_22", 0x32b54, 0 },
|
|
{ "MAC_PORT_AET_LIMITS2", 0x32b58, 0 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x32b60, 0 },
|
|
{ "INIT_METH", 12, 4 },
|
|
{ "INIT_CNT", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_N0", 5, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x32b64, 0 },
|
|
{ "FEC_CNV", 15, 1 },
|
|
{ "EN_RETRY", 14, 1 },
|
|
{ "DPC_METH", 12, 2 },
|
|
{ "EN_P2", 11, 1 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_3", 0x32b68, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x32b6c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT5", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_3", 0x32b70, 0 },
|
|
{ "CTRL_STAT", 8, 5 },
|
|
{ "NEU_STATE", 4, 4 },
|
|
{ "CTRL_STATE", 0, 4 },
|
|
{ "MAC_PORT_AET_STATUS_23", 0x32b74, 0 },
|
|
{ "MAC_PORT_AET_LIMITS3", 0x32b78, 0 },
|
|
{ "MAC_PORT_ANALOG_TEST_MUX", 0x33814, 0 },
|
|
{ "MAC_PORT_PLLREFSEL_CONTROL", 0x33854, 0 },
|
|
{ "MAC_PORT_REFISINK_CONTROL", 0x33858, 0 },
|
|
{ "MAC_PORT_REFISRC_CONTROL", 0x3385c, 0 },
|
|
{ "MAC_PORT_REFVREG_CONTROL", 0x33860, 0 },
|
|
{ "MAC_PORT_VBGENDOC_CONTROL", 0x33864, 0 },
|
|
{ "BGCLKSEL", 2, 1 },
|
|
{ "VBGENDOC", 0, 2 },
|
|
{ "MAC_PORT_VREFTUNE_CONTROL", 0x33868, 0 },
|
|
{ "MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL", 0x33880, 0 },
|
|
{ "FRCCAL_COMP", 6, 1 },
|
|
{ "FRCERR", 5, 1 },
|
|
{ "CAL_BISTENAB", 4, 1 },
|
|
{ "RCAL_RESET", 0, 1 },
|
|
{ "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1", 0x33884, 0 },
|
|
{ "RCALBENAB", 3, 1 },
|
|
{ "RCALBUSY", 2, 1 },
|
|
{ "RCALERR", 1, 1 },
|
|
{ "RCALCOMP", 0, 1 },
|
|
{ "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2", 0x33888, 0 },
|
|
{ "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3", 0x3388c, 0 },
|
|
{ "MAC_PORT_INEQUALITY_CONTROL_AND_RESULT", 0x338c0, 0 },
|
|
{ "ISGT", 7, 1 },
|
|
{ "ISLT", 6, 1 },
|
|
{ "ISEQ", 5, 1 },
|
|
{ "ISVAL", 3, 2 },
|
|
{ "GTORLT", 1, 2 },
|
|
{ "INEQ", 0, 1 },
|
|
{ "MAC_PORT_INEQUALITY_LOW_LIMIT", 0x338c4, 0 },
|
|
{ "MAC_PORT_INEQUALITY_LOW_LIMIT_MASK", 0x338c8, 0 },
|
|
{ "MAC_PORT_INEQUALITY_HIGH_LIMIT", 0x338cc, 0 },
|
|
{ "MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK", 0x338d0, 0 },
|
|
{ "MAC_PORT_MACRO_TEST_CONTROL_6", 0x338e8, 0 },
|
|
{ "JTAGMD", 3, 1 },
|
|
{ "RXACMODE", 2, 1 },
|
|
{ "HSSACJPC", 1, 1 },
|
|
{ "HSSACJAC", 0, 1 },
|
|
{ "MAC_PORT_MACRO_TEST_CONTROL_5", 0x338ec, 0 },
|
|
{ "REFVALIDD", 6, 1 },
|
|
{ "REFVALIDC", 5, 1 },
|
|
{ "REFVALIDB", 4, 1 },
|
|
{ "REFVALIDA", 3, 1 },
|
|
{ "REFSELRESET", 2, 1 },
|
|
{ "SOFTRESET", 1, 1 },
|
|
{ "MACROTEST", 0, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x33b00, 0 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x33b04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x33b08, 0 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x33b0c, 0 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x33b10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "MAC_PORT_PLLA_POWER_CONTROL", 0x33b24, 0 },
|
|
{ "SPWRENA", 1, 1 },
|
|
{ "NPWRENA", 0, 1 },
|
|
{ "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x33b28, 0 },
|
|
{ "MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL", 0x33b38, 0 },
|
|
{ "MAC_PORT_PLLA_PCLK_CONTROL", 0x33b3c, 0 },
|
|
{ "SPEDIV", 3, 5 },
|
|
{ "PCKSEL", 0, 3 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x33b40, 0 },
|
|
{ "EMIL", 2, 1 },
|
|
{ "EMID", 1, 1 },
|
|
{ "EMIS", 0, 1 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x33b44, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x33b48, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x33b4c, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x33b50, 0 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x33bf0, 0 },
|
|
{ "PLLDIVA", 4, 1 },
|
|
{ "REFDIV", 0, 4 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x33bf4, 0 },
|
|
{ "RESYNC", 6, 1 },
|
|
{ "RXCLKSEL", 5, 1 },
|
|
{ "FRCBAND", 4, 1 },
|
|
{ "PLLBYP", 3, 1 },
|
|
{ "VCOSEL", 1, 1 },
|
|
{ "DIVSEL8", 0, 1 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x33bf8, 0 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x33bfc, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x33c00, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x33c04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x33c08, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x33c0c, 0 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x33c10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "MAC_PORT_PLLB_POWER_CONTROL", 0x33c24, 0 },
|
|
{ "SPWRENA", 1, 1 },
|
|
{ "NPWRENA", 0, 1 },
|
|
{ "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x33c28, 0 },
|
|
{ "MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL", 0x33c38, 0 },
|
|
{ "MAC_PORT_PLLB_PCLK_CONTROL", 0x33c3c, 0 },
|
|
{ "SPEDIV", 3, 5 },
|
|
{ "PCKSEL", 0, 3 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x33c40, 0 },
|
|
{ "EMIL", 2, 1 },
|
|
{ "EMID", 1, 1 },
|
|
{ "EMIS", 0, 1 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x33c44, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x33c48, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x33c4c, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x33c50, 0 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x33cf0, 0 },
|
|
{ "PLLDIVA", 4, 1 },
|
|
{ "REFDIV", 0, 4 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x33cf4, 0 },
|
|
{ "RESYNC", 6, 1 },
|
|
{ "RXCLKSEL", 5, 1 },
|
|
{ "FRCBAND", 4, 1 },
|
|
{ "PLLBYP", 3, 1 },
|
|
{ "VCOSEL", 1, 1 },
|
|
{ "DIVSEL8", 0, 1 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x33cf8, 0 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x33cfc, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x33000, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_RXLOOP", 5, 1 },
|
|
{ "T5_TX_ENFFE4", 4, 1 },
|
|
{ "T5_TX_BWSEL", 2, 2 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x33004, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "FRCERR", 10, 1 },
|
|
{ "ERROR", 9, 1 },
|
|
{ "SYNC", 8, 1 },
|
|
{ "P7CHK", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x33008, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "SASMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3300c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33010, 0 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33014, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33018, 0 },
|
|
{ "CALSSTN", 8, 6 },
|
|
{ "CALSSTP", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3301c, 0 },
|
|
{ "DRTOL", 2, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x33020, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x33024, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x33028, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT", 0x3302c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x33034, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33038, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "SASCMD", 10, 2 },
|
|
{ "C0UPDT", 6, 2 },
|
|
{ "C3UPDT", 4, 2 },
|
|
{ "C2UPDT", 2, 2 },
|
|
{ "C1UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3303c, 0 },
|
|
{ "C0STAT", 6, 2 },
|
|
{ "C3STAT", 4, 2 },
|
|
{ "C2STAT", 2, 2 },
|
|
{ "C1STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33040, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33044, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33048, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3304c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33050, 0 },
|
|
{ "ATUNEN", 8, 8 },
|
|
{ "ATUNEP", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33058, 0 },
|
|
{ "DCCCOMPINV", 8, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED", 0x33060, 0 },
|
|
{ "AS4X7", 14, 2 },
|
|
{ "AS4X6", 12, 2 },
|
|
{ "AS4X5", 10, 2 },
|
|
{ "AS4X4", 8, 2 },
|
|
{ "AS4X3", 6, 2 },
|
|
{ "AS4X2", 4, 2 },
|
|
{ "AS4X1", 2, 2 },
|
|
{ "AS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED", 0x33064, 0 },
|
|
{ "AS2X3", 6, 2 },
|
|
{ "AS2X2", 4, 2 },
|
|
{ "AS2X1", 2, 2 },
|
|
{ "AS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED", 0x33068, 0 },
|
|
{ "AS1X7", 14, 2 },
|
|
{ "AS1X6", 12, 2 },
|
|
{ "AS1X5", 10, 2 },
|
|
{ "AS1X4", 8, 2 },
|
|
{ "AS1X3", 6, 2 },
|
|
{ "AS1X2", 4, 2 },
|
|
{ "AS1X1", 2, 2 },
|
|
{ "AS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3306c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33070, 0 },
|
|
{ "AT2X", 8, 4 },
|
|
{ "AT4X", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33074, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33078, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3307c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33080, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33084, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33088, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3308c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3309c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x330a0, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 13, 2 },
|
|
{ "DCCLOCK", 11, 2 },
|
|
{ "DCCOFFSET", 8, 3 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x330a4, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x330a8, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x330ac, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE", 0x330c0, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x330c8, 0 },
|
|
{ "OS4X7", 14, 2 },
|
|
{ "OS4X6", 12, 2 },
|
|
{ "OS4X5", 10, 2 },
|
|
{ "OS4X4", 8, 2 },
|
|
{ "OS4X3", 6, 2 },
|
|
{ "OS4X2", 4, 2 },
|
|
{ "OS4X1", 2, 2 },
|
|
{ "OS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x330cc, 0 },
|
|
{ "OS2X3", 6, 2 },
|
|
{ "OS2X2", 4, 2 },
|
|
{ "OS2X1", 2, 2 },
|
|
{ "OS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x330d0, 0 },
|
|
{ "OS1X7", 14, 2 },
|
|
{ "OS1X6", 12, 2 },
|
|
{ "OS1X5", 10, 2 },
|
|
{ "OS1X4", 8, 2 },
|
|
{ "OS1X3", 6, 2 },
|
|
{ "OS1X2", 4, 2 },
|
|
{ "OS1X1", 2, 2 },
|
|
{ "OS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x330d8, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x330dc, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x330e0, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5", 0x330ec, 0 },
|
|
{ "ERRORP", 15, 1 },
|
|
{ "ERRORN", 14, 1 },
|
|
{ "TESTENA", 13, 1 },
|
|
{ "TUNEBIT", 10, 3 },
|
|
{ "DATAPOS", 8, 2 },
|
|
{ "SEGSEL", 3, 5 },
|
|
{ "TAPSEL", 1, 2 },
|
|
{ "DATASIGN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x330f0, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x330f4, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x330f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x330fc, 0 },
|
|
{ "SDOVRDEN", 15, 1 },
|
|
{ "BSOUTN", 7, 1 },
|
|
{ "BSOUTP", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x33100, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_RXLOOP", 5, 1 },
|
|
{ "T5_TX_ENFFE4", 4, 1 },
|
|
{ "T5_TX_BWSEL", 2, 2 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x33104, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "FRCERR", 10, 1 },
|
|
{ "ERROR", 9, 1 },
|
|
{ "SYNC", 8, 1 },
|
|
{ "P7CHK", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x33108, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "SASMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3310c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33110, 0 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33114, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33118, 0 },
|
|
{ "CALSSTN", 8, 6 },
|
|
{ "CALSSTP", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3311c, 0 },
|
|
{ "DRTOL", 2, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x33120, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x33124, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x33128, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT", 0x3312c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x33134, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33138, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "SASCMD", 10, 2 },
|
|
{ "C0UPDT", 6, 2 },
|
|
{ "C3UPDT", 4, 2 },
|
|
{ "C2UPDT", 2, 2 },
|
|
{ "C1UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3313c, 0 },
|
|
{ "C0STAT", 6, 2 },
|
|
{ "C3STAT", 4, 2 },
|
|
{ "C2STAT", 2, 2 },
|
|
{ "C1STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33140, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33144, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33148, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3314c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33150, 0 },
|
|
{ "ATUNEN", 8, 8 },
|
|
{ "ATUNEP", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33158, 0 },
|
|
{ "DCCCOMPINV", 8, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED", 0x33160, 0 },
|
|
{ "AS4X7", 14, 2 },
|
|
{ "AS4X6", 12, 2 },
|
|
{ "AS4X5", 10, 2 },
|
|
{ "AS4X4", 8, 2 },
|
|
{ "AS4X3", 6, 2 },
|
|
{ "AS4X2", 4, 2 },
|
|
{ "AS4X1", 2, 2 },
|
|
{ "AS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED", 0x33164, 0 },
|
|
{ "AS2X3", 6, 2 },
|
|
{ "AS2X2", 4, 2 },
|
|
{ "AS2X1", 2, 2 },
|
|
{ "AS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED", 0x33168, 0 },
|
|
{ "AS1X7", 14, 2 },
|
|
{ "AS1X6", 12, 2 },
|
|
{ "AS1X5", 10, 2 },
|
|
{ "AS1X4", 8, 2 },
|
|
{ "AS1X3", 6, 2 },
|
|
{ "AS1X2", 4, 2 },
|
|
{ "AS1X1", 2, 2 },
|
|
{ "AS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3316c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33170, 0 },
|
|
{ "AT2X", 8, 4 },
|
|
{ "AT4X", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33174, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33178, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3317c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33180, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33184, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33188, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3318c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3319c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x331a0, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 13, 2 },
|
|
{ "DCCLOCK", 11, 2 },
|
|
{ "DCCOFFSET", 8, 3 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x331a4, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x331a8, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x331ac, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE", 0x331c0, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x331c8, 0 },
|
|
{ "OS4X7", 14, 2 },
|
|
{ "OS4X6", 12, 2 },
|
|
{ "OS4X5", 10, 2 },
|
|
{ "OS4X4", 8, 2 },
|
|
{ "OS4X3", 6, 2 },
|
|
{ "OS4X2", 4, 2 },
|
|
{ "OS4X1", 2, 2 },
|
|
{ "OS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x331cc, 0 },
|
|
{ "OS2X3", 6, 2 },
|
|
{ "OS2X2", 4, 2 },
|
|
{ "OS2X1", 2, 2 },
|
|
{ "OS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x331d0, 0 },
|
|
{ "OS1X7", 14, 2 },
|
|
{ "OS1X6", 12, 2 },
|
|
{ "OS1X5", 10, 2 },
|
|
{ "OS1X4", 8, 2 },
|
|
{ "OS1X3", 6, 2 },
|
|
{ "OS1X2", 4, 2 },
|
|
{ "OS1X1", 2, 2 },
|
|
{ "OS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x331d8, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x331dc, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x331e0, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5", 0x331ec, 0 },
|
|
{ "ERRORP", 15, 1 },
|
|
{ "ERRORN", 14, 1 },
|
|
{ "TESTENA", 13, 1 },
|
|
{ "TUNEBIT", 10, 3 },
|
|
{ "DATAPOS", 8, 2 },
|
|
{ "SEGSEL", 3, 5 },
|
|
{ "TAPSEL", 1, 2 },
|
|
{ "DATASIGN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x331f0, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x331f4, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x331f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x331fc, 0 },
|
|
{ "SDOVRDEN", 15, 1 },
|
|
{ "BSOUTN", 7, 1 },
|
|
{ "BSOUTP", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x33400, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_RXLOOP", 5, 1 },
|
|
{ "T5_TX_ENFFE4", 4, 1 },
|
|
{ "T5_TX_BWSEL", 2, 2 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x33404, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "FRCERR", 10, 1 },
|
|
{ "ERROR", 9, 1 },
|
|
{ "SYNC", 8, 1 },
|
|
{ "P7CHK", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x33408, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "SASMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3340c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33410, 0 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33414, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33418, 0 },
|
|
{ "CALSSTN", 8, 6 },
|
|
{ "CALSSTP", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3341c, 0 },
|
|
{ "DRTOL", 2, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x33420, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x33424, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x33428, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT", 0x3342c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x33434, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33438, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "SASCMD", 10, 2 },
|
|
{ "C0UPDT", 6, 2 },
|
|
{ "C3UPDT", 4, 2 },
|
|
{ "C2UPDT", 2, 2 },
|
|
{ "C1UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3343c, 0 },
|
|
{ "C0STAT", 6, 2 },
|
|
{ "C3STAT", 4, 2 },
|
|
{ "C2STAT", 2, 2 },
|
|
{ "C1STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33440, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33444, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33448, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3344c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33450, 0 },
|
|
{ "ATUNEN", 8, 8 },
|
|
{ "ATUNEP", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33458, 0 },
|
|
{ "DCCCOMPINV", 8, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED", 0x33460, 0 },
|
|
{ "AS4X7", 14, 2 },
|
|
{ "AS4X6", 12, 2 },
|
|
{ "AS4X5", 10, 2 },
|
|
{ "AS4X4", 8, 2 },
|
|
{ "AS4X3", 6, 2 },
|
|
{ "AS4X2", 4, 2 },
|
|
{ "AS4X1", 2, 2 },
|
|
{ "AS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED", 0x33464, 0 },
|
|
{ "AS2X3", 6, 2 },
|
|
{ "AS2X2", 4, 2 },
|
|
{ "AS2X1", 2, 2 },
|
|
{ "AS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED", 0x33468, 0 },
|
|
{ "AS1X7", 14, 2 },
|
|
{ "AS1X6", 12, 2 },
|
|
{ "AS1X5", 10, 2 },
|
|
{ "AS1X4", 8, 2 },
|
|
{ "AS1X3", 6, 2 },
|
|
{ "AS1X2", 4, 2 },
|
|
{ "AS1X1", 2, 2 },
|
|
{ "AS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3346c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33470, 0 },
|
|
{ "AT2X", 8, 4 },
|
|
{ "AT4X", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33474, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33478, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3347c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33480, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33484, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33488, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3348c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3349c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x334a0, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 13, 2 },
|
|
{ "DCCLOCK", 11, 2 },
|
|
{ "DCCOFFSET", 8, 3 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x334a4, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x334a8, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x334ac, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE", 0x334c0, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x334c8, 0 },
|
|
{ "OS4X7", 14, 2 },
|
|
{ "OS4X6", 12, 2 },
|
|
{ "OS4X5", 10, 2 },
|
|
{ "OS4X4", 8, 2 },
|
|
{ "OS4X3", 6, 2 },
|
|
{ "OS4X2", 4, 2 },
|
|
{ "OS4X1", 2, 2 },
|
|
{ "OS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x334cc, 0 },
|
|
{ "OS2X3", 6, 2 },
|
|
{ "OS2X2", 4, 2 },
|
|
{ "OS2X1", 2, 2 },
|
|
{ "OS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x334d0, 0 },
|
|
{ "OS1X7", 14, 2 },
|
|
{ "OS1X6", 12, 2 },
|
|
{ "OS1X5", 10, 2 },
|
|
{ "OS1X4", 8, 2 },
|
|
{ "OS1X3", 6, 2 },
|
|
{ "OS1X2", 4, 2 },
|
|
{ "OS1X1", 2, 2 },
|
|
{ "OS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x334d8, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x334dc, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x334e0, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5", 0x334ec, 0 },
|
|
{ "ERRORP", 15, 1 },
|
|
{ "ERRORN", 14, 1 },
|
|
{ "TESTENA", 13, 1 },
|
|
{ "TUNEBIT", 10, 3 },
|
|
{ "DATAPOS", 8, 2 },
|
|
{ "SEGSEL", 3, 5 },
|
|
{ "TAPSEL", 1, 2 },
|
|
{ "DATASIGN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x334f0, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x334f4, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x334f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x334fc, 0 },
|
|
{ "SDOVRDEN", 15, 1 },
|
|
{ "BSOUTN", 7, 1 },
|
|
{ "BSOUTP", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x33500, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_RXLOOP", 5, 1 },
|
|
{ "T5_TX_ENFFE4", 4, 1 },
|
|
{ "T5_TX_BWSEL", 2, 2 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x33504, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "FRCERR", 10, 1 },
|
|
{ "ERROR", 9, 1 },
|
|
{ "SYNC", 8, 1 },
|
|
{ "P7CHK", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x33508, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "SASMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3350c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33510, 0 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33514, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33518, 0 },
|
|
{ "CALSSTN", 8, 6 },
|
|
{ "CALSSTP", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3351c, 0 },
|
|
{ "DRTOL", 2, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x33520, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x33524, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x33528, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT", 0x3352c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x33534, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33538, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "SASCMD", 10, 2 },
|
|
{ "C0UPDT", 6, 2 },
|
|
{ "C3UPDT", 4, 2 },
|
|
{ "C2UPDT", 2, 2 },
|
|
{ "C1UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3353c, 0 },
|
|
{ "C0STAT", 6, 2 },
|
|
{ "C3STAT", 4, 2 },
|
|
{ "C2STAT", 2, 2 },
|
|
{ "C1STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33540, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33544, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33548, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3354c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33550, 0 },
|
|
{ "ATUNEN", 8, 8 },
|
|
{ "ATUNEP", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33558, 0 },
|
|
{ "DCCCOMPINV", 8, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED", 0x33560, 0 },
|
|
{ "AS4X7", 14, 2 },
|
|
{ "AS4X6", 12, 2 },
|
|
{ "AS4X5", 10, 2 },
|
|
{ "AS4X4", 8, 2 },
|
|
{ "AS4X3", 6, 2 },
|
|
{ "AS4X2", 4, 2 },
|
|
{ "AS4X1", 2, 2 },
|
|
{ "AS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED", 0x33564, 0 },
|
|
{ "AS2X3", 6, 2 },
|
|
{ "AS2X2", 4, 2 },
|
|
{ "AS2X1", 2, 2 },
|
|
{ "AS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED", 0x33568, 0 },
|
|
{ "AS1X7", 14, 2 },
|
|
{ "AS1X6", 12, 2 },
|
|
{ "AS1X5", 10, 2 },
|
|
{ "AS1X4", 8, 2 },
|
|
{ "AS1X3", 6, 2 },
|
|
{ "AS1X2", 4, 2 },
|
|
{ "AS1X1", 2, 2 },
|
|
{ "AS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3356c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33570, 0 },
|
|
{ "AT2X", 8, 4 },
|
|
{ "AT4X", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33574, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33578, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3357c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33580, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33584, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33588, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3358c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3359c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x335a0, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 13, 2 },
|
|
{ "DCCLOCK", 11, 2 },
|
|
{ "DCCOFFSET", 8, 3 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x335a4, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x335a8, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x335ac, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE", 0x335c0, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x335c8, 0 },
|
|
{ "OS4X7", 14, 2 },
|
|
{ "OS4X6", 12, 2 },
|
|
{ "OS4X5", 10, 2 },
|
|
{ "OS4X4", 8, 2 },
|
|
{ "OS4X3", 6, 2 },
|
|
{ "OS4X2", 4, 2 },
|
|
{ "OS4X1", 2, 2 },
|
|
{ "OS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x335cc, 0 },
|
|
{ "OS2X3", 6, 2 },
|
|
{ "OS2X2", 4, 2 },
|
|
{ "OS2X1", 2, 2 },
|
|
{ "OS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x335d0, 0 },
|
|
{ "OS1X7", 14, 2 },
|
|
{ "OS1X6", 12, 2 },
|
|
{ "OS1X5", 10, 2 },
|
|
{ "OS1X4", 8, 2 },
|
|
{ "OS1X3", 6, 2 },
|
|
{ "OS1X2", 4, 2 },
|
|
{ "OS1X1", 2, 2 },
|
|
{ "OS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x335d8, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x335dc, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x335e0, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5", 0x335ec, 0 },
|
|
{ "ERRORP", 15, 1 },
|
|
{ "ERRORN", 14, 1 },
|
|
{ "TESTENA", 13, 1 },
|
|
{ "TUNEBIT", 10, 3 },
|
|
{ "DATAPOS", 8, 2 },
|
|
{ "SEGSEL", 3, 5 },
|
|
{ "TAPSEL", 1, 2 },
|
|
{ "DATASIGN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x335f0, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x335f4, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x335f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x335fc, 0 },
|
|
{ "SDOVRDEN", 15, 1 },
|
|
{ "BSOUTN", 7, 1 },
|
|
{ "BSOUTP", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x33900, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_RXLOOP", 5, 1 },
|
|
{ "T5_TX_ENFFE4", 4, 1 },
|
|
{ "T5_TX_BWSEL", 2, 2 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x33904, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "FRCERR", 10, 1 },
|
|
{ "ERROR", 9, 1 },
|
|
{ "SYNC", 8, 1 },
|
|
{ "P7CHK", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x33908, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "SASMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3390c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33910, 0 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33914, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33918, 0 },
|
|
{ "CALSSTN", 8, 6 },
|
|
{ "CALSSTP", 0, 6 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3391c, 0 },
|
|
{ "DRTOL", 2, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x33920, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x33924, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x33928, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT", 0x3392c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x33934, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33938, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "SASCMD", 10, 2 },
|
|
{ "C0UPDT", 6, 2 },
|
|
{ "C3UPDT", 4, 2 },
|
|
{ "C2UPDT", 2, 2 },
|
|
{ "C1UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3393c, 0 },
|
|
{ "C0STAT", 6, 2 },
|
|
{ "C3STAT", 4, 2 },
|
|
{ "C2STAT", 2, 2 },
|
|
{ "C1STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33940, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33944, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33948, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3394c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33950, 0 },
|
|
{ "ATUNEN", 8, 8 },
|
|
{ "ATUNEP", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33958, 0 },
|
|
{ "DCCCOMPINV", 8, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED", 0x33960, 0 },
|
|
{ "AS4X7", 14, 2 },
|
|
{ "AS4X6", 12, 2 },
|
|
{ "AS4X5", 10, 2 },
|
|
{ "AS4X4", 8, 2 },
|
|
{ "AS4X3", 6, 2 },
|
|
{ "AS4X2", 4, 2 },
|
|
{ "AS4X1", 2, 2 },
|
|
{ "AS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED", 0x33964, 0 },
|
|
{ "AS2X3", 6, 2 },
|
|
{ "AS2X2", 4, 2 },
|
|
{ "AS2X1", 2, 2 },
|
|
{ "AS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED", 0x33968, 0 },
|
|
{ "AS1X7", 14, 2 },
|
|
{ "AS1X6", 12, 2 },
|
|
{ "AS1X5", 10, 2 },
|
|
{ "AS1X4", 8, 2 },
|
|
{ "AS1X3", 6, 2 },
|
|
{ "AS1X2", 4, 2 },
|
|
{ "AS1X1", 2, 2 },
|
|
{ "AS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3396c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33970, 0 },
|
|
{ "AT2X", 8, 4 },
|
|
{ "AT4X", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33974, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33978, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3397c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33980, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33984, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33988, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3398c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3399c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x339a0, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 13, 2 },
|
|
{ "DCCLOCK", 11, 2 },
|
|
{ "DCCOFFSET", 8, 3 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x339a4, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x339a8, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x339ac, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE", 0x339c0, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x339c8, 0 },
|
|
{ "OS4X7", 14, 2 },
|
|
{ "OS4X6", 12, 2 },
|
|
{ "OS4X5", 10, 2 },
|
|
{ "OS4X4", 8, 2 },
|
|
{ "OS4X3", 6, 2 },
|
|
{ "OS4X2", 4, 2 },
|
|
{ "OS4X1", 2, 2 },
|
|
{ "OS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x339cc, 0 },
|
|
{ "OS2X3", 6, 2 },
|
|
{ "OS2X2", 4, 2 },
|
|
{ "OS2X1", 2, 2 },
|
|
{ "OS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x339d0, 0 },
|
|
{ "OS1X7", 14, 2 },
|
|
{ "OS1X6", 12, 2 },
|
|
{ "OS1X5", 10, 2 },
|
|
{ "OS1X4", 8, 2 },
|
|
{ "OS1X3", 6, 2 },
|
|
{ "OS1X2", 4, 2 },
|
|
{ "OS1X1", 2, 2 },
|
|
{ "OS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x339d8, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x339dc, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x339e0, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5", 0x339ec, 0 },
|
|
{ "ERRORP", 15, 1 },
|
|
{ "ERRORN", 14, 1 },
|
|
{ "TESTENA", 13, 1 },
|
|
{ "TUNEBIT", 10, 3 },
|
|
{ "DATAPOS", 8, 2 },
|
|
{ "SEGSEL", 3, 5 },
|
|
{ "TAPSEL", 1, 2 },
|
|
{ "DATASIGN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x339f0, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x339f4, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x339f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x339fc, 0 },
|
|
{ "SDOVRDEN", 15, 1 },
|
|
{ "BSOUTN", 7, 1 },
|
|
{ "BSOUTP", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x33200, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_MODE8023AZ", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x33204, 0 },
|
|
{ "APLYDCD", 15, 1 },
|
|
{ "PPOL", 13, 2 },
|
|
{ "PCLKSEL", 11, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x33208, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3320c, 0 },
|
|
{ "H1ANOFST", 12, 4 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "TMSCAL", 8, 2 },
|
|
{ "APADJ", 7, 1 },
|
|
{ "RSEL", 6, 1 },
|
|
{ "PHOFFS", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x33210, 0 },
|
|
{ "ROTA", 8, 6 },
|
|
{ "ROTD", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x33214, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROTE", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33218, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOFFF", 8, 4 },
|
|
{ "RAOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3321c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x33220, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 8, 4 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x33224, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x33228, 0 },
|
|
{ "REQWOV", 15, 1 },
|
|
{ "RASEL", 11, 3 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3322c, 0 },
|
|
{ "WRAPSEL", 15, 1 },
|
|
{ "ACTL", 14, 1 },
|
|
{ "PEAK", 9, 5 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x33230, 0 },
|
|
{ "FVOFFSKP", 15, 1 },
|
|
{ "FGAINCHK", 14, 1 },
|
|
{ "FH1ACAL", 13, 1 },
|
|
{ "FH1AFLTR", 11, 2 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "WGAIN", 8, 2 },
|
|
{ "GAIN_STAT", 7, 1 },
|
|
{ "T5VGAIN", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x33234, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33238, 0 },
|
|
{ "PMCFG", 6, 2 },
|
|
{ "PMOFFTIME", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1", 0x3323c, 0 },
|
|
{ "SELI", 9, 1 },
|
|
{ "SERVREF", 5, 3 },
|
|
{ "IQAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2", 0x33240, 0 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33244, 0 },
|
|
{ "SAVEADAC", 8, 1 },
|
|
{ "LOAD2", 7, 1 },
|
|
{ "LOAD1", 6, 1 },
|
|
{ "WRTACC2", 5, 1 },
|
|
{ "WRTACC1", 4, 1 },
|
|
{ "SELAPAN", 3, 1 },
|
|
{ "DASEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x33248, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN", 0x3324c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x33250, 0 },
|
|
{ "ADAC2", 8, 8 },
|
|
{ "ADAC1", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL", 0x33254, 0 },
|
|
{ "FACCPLDYN", 13, 1 },
|
|
{ "ACCPLGAIN", 10, 3 },
|
|
{ "ACCPLREF", 8, 2 },
|
|
{ "ACCPLSTEP", 6, 2 },
|
|
{ "ACCPLASTEP", 1, 5 },
|
|
{ "FACCPL", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE", 0x33258, 0 },
|
|
{ "ACCPLMEANS", 15, 1 },
|
|
{ "CDROVREN", 8, 1 },
|
|
{ "ACCPLBIAS", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET", 0x3325c, 0 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33260, 0 },
|
|
{ "H1OX", 8, 6 },
|
|
{ "H1EX", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR", 0x33264, 0 },
|
|
{ "PILOCK", 10, 1 },
|
|
{ "UNPKPKA", 2, 6 },
|
|
{ "UNPKVGA", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH", 0x33268, 0 },
|
|
{ "OVRAC", 15, 1 },
|
|
{ "OVRPK", 14, 1 },
|
|
{ "OVRTAILS", 12, 2 },
|
|
{ "OVRTAILV", 9, 3 },
|
|
{ "OVRCAP", 8, 1 },
|
|
{ "OVRDCDPRE", 7, 1 },
|
|
{ "OVRDCDPST", 6, 1 },
|
|
{ "DCVSCTMODE", 2, 1 },
|
|
{ "CDRANLGSW", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3326c, 0 },
|
|
{ "PFLAG", 5, 2 },
|
|
{ "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33270, 0 },
|
|
{ "DACCLIP", 15, 1 },
|
|
{ "DPCFRZ", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCLKNQ", 11, 1 },
|
|
{ "DPCWDFE", 10, 1 },
|
|
{ "DPCWPK", 9, 1 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x33274, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "VIEWSCAN", 4, 1 },
|
|
{ "ODEC", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x33278, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "ACCCMP", 11, 1 },
|
|
{ "DCCCMP", 10, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5IQCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3327c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x33280, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FDCCAL", 14, 1 },
|
|
{ "FROTCAL", 13, 1 },
|
|
{ "FIQAMP", 12, 1 },
|
|
{ "FRPTCALF", 11, 1 },
|
|
{ "FINTCALGS", 10, 1 },
|
|
{ "FDCC", 9, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FDCD", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FINTRCALDYN", 1, 1 },
|
|
{ "FQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL", 0x33284, 0 },
|
|
{ "QCCIND", 13, 1 },
|
|
{ "DCDIND", 10, 3 },
|
|
{ "DCCIND", 8, 2 },
|
|
{ "CFSEL", 5, 1 },
|
|
{ "LOFCH", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE", 0x33288, 0 },
|
|
{ "LOFU", 8, 7 },
|
|
{ "LOFL", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST", 0x3328c, 0 },
|
|
{ "HBISTMAN", 12, 1 },
|
|
{ "HBISTRES", 11, 1 },
|
|
{ "HBISTSP", 8, 3 },
|
|
{ "HBISTEN", 7, 1 },
|
|
{ "HBISTRST", 6, 1 },
|
|
{ "HCOMP", 5, 1 },
|
|
{ "HPASS", 4, 1 },
|
|
{ "HSEL", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST", 0x33290, 0 },
|
|
{ "ACCCMP", 13, 1 },
|
|
{ "ACCEN", 12, 1 },
|
|
{ "ACCRST", 11, 1 },
|
|
{ "ACCIND", 8, 3 },
|
|
{ "ACCRD", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER", 0x33298, 0 },
|
|
{ "LFREG", 15, 1 },
|
|
{ "LFRC", 14, 1 },
|
|
{ "LGIDLE", 13, 1 },
|
|
{ "LFTGT", 8, 5 },
|
|
{ "LGTGT", 7, 1 },
|
|
{ "LRDY", 6, 1 },
|
|
{ "LIDLE", 5, 1 },
|
|
{ "LCURR", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3329c, 0 },
|
|
{ "OFFSN", 13, 2 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x332a0, 0 },
|
|
{ "RX_OVRSUMPD", 15, 1 },
|
|
{ "RX_OVRKBPD", 14, 1 },
|
|
{ "RX_OVRDIVPD", 13, 1 },
|
|
{ "RX_OFFVGADIS", 12, 1 },
|
|
{ "RX_OFFACDIS", 11, 1 },
|
|
{ "RX_VTERM", 10, 1 },
|
|
{ "RX_DISSPY2D", 8, 1 },
|
|
{ "RX_OBSOVEN", 7, 1 },
|
|
{ "RX_LINKANLGSW", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x332a4, 0 },
|
|
{ "INTDACEGS", 13, 3 },
|
|
{ "INTDACE", 8, 5 },
|
|
{ "INTDACGS", 6, 2 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x332a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x332ac, 0 },
|
|
{ "SMQM", 13, 3 },
|
|
{ "SMQ", 5, 8 },
|
|
{ "EMMD", 3, 2 },
|
|
{ "EMBRDY", 2, 1 },
|
|
{ "EMBUMP", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x332b0, 0 },
|
|
{ "EMSF", 13, 1 },
|
|
{ "EMDATA59", 12, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x332b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x332b8, 0 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3", 0x332bc, 0 },
|
|
{ "FTIMEOUT", 15, 1 },
|
|
{ "FROTCAL4", 14, 1 },
|
|
{ "FDCD2", 13, 1 },
|
|
{ "FPRBSPOLTOG", 12, 1 },
|
|
{ "FPRBSOFF2", 11, 1 },
|
|
{ "FDDCAL2", 10, 1 },
|
|
{ "FDDCFLTR", 9, 1 },
|
|
{ "FDAC6", 8, 1 },
|
|
{ "FDDC5", 7, 1 },
|
|
{ "FDDC3456", 6, 1 },
|
|
{ "FSPY2DATA", 5, 1 },
|
|
{ "FPHSLOCK", 4, 1 },
|
|
{ "FCLKALGN", 3, 1 },
|
|
{ "FCLKALDYN", 2, 1 },
|
|
{ "FDFE", 1, 1 },
|
|
{ "FPRBSOFF", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_TAP_CONTROL", 0x332c0, 0 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_TAP", 0x332c4, 0 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2", 0x332e4, 0 },
|
|
{ "STNDBYSTAT", 15, 1 },
|
|
{ "CALSDONE", 14, 1 },
|
|
{ "ACISRCCMP", 5, 1 },
|
|
{ "PRBSOFFCMP", 4, 1 },
|
|
{ "CLKALGNCMP", 3, 1 },
|
|
{ "ROTFCMP", 2, 1 },
|
|
{ "DCDCMP", 1, 1 },
|
|
{ "QCCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x332e8, 0 },
|
|
{ "FCSADJ", 6, 1 },
|
|
{ "CSIND", 3, 2 },
|
|
{ "CSVAL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL", 0x332ec, 0 },
|
|
{ "DCDTMDOUT", 15, 1 },
|
|
{ "DCDTOEN", 14, 1 },
|
|
{ "DCDLOCK", 13, 1 },
|
|
{ "DCDSTEP", 11, 2 },
|
|
{ "DCDALTWPDIS", 10, 1 },
|
|
{ "DCDOVRDEN", 9, 1 },
|
|
{ "DCCAOVRDEN", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL", 0x332f0, 0 },
|
|
{ "PRBSMODE", 14, 2 },
|
|
{ "DCCSTEP", 10, 2 },
|
|
{ "DCCOVRDEN", 9, 1 },
|
|
{ "DCCLOCK", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL", 0x332f4, 0 },
|
|
{ "DCCQCCMODE", 15, 1 },
|
|
{ "DCCQCCDYN", 14, 1 },
|
|
{ "DCCQCCHOLD", 13, 1 },
|
|
{ "QCCSTEP", 10, 2 },
|
|
{ "QCCOVRDEN", 9, 1 },
|
|
{ "QCCLOCK", 8, 1 },
|
|
{ "QCCSIGN", 6, 2 },
|
|
{ "QCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x332f8, 0 },
|
|
{ "TSTCMP", 15, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x332fc, 0 },
|
|
{ "CALMODEEDGE", 14, 1 },
|
|
{ "TESTCAP", 13, 1 },
|
|
{ "SNAPEN", 12, 1 },
|
|
{ "ASYNCDIR", 11, 1 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x33300, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_MODE8023AZ", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x33304, 0 },
|
|
{ "APLYDCD", 15, 1 },
|
|
{ "PPOL", 13, 2 },
|
|
{ "PCLKSEL", 11, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x33308, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3330c, 0 },
|
|
{ "H1ANOFST", 12, 4 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "TMSCAL", 8, 2 },
|
|
{ "APADJ", 7, 1 },
|
|
{ "RSEL", 6, 1 },
|
|
{ "PHOFFS", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x33310, 0 },
|
|
{ "ROTA", 8, 6 },
|
|
{ "ROTD", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x33314, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROTE", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33318, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOFFF", 8, 4 },
|
|
{ "RAOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3331c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x33320, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 8, 4 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x33324, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x33328, 0 },
|
|
{ "REQWOV", 15, 1 },
|
|
{ "RASEL", 11, 3 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3332c, 0 },
|
|
{ "WRAPSEL", 15, 1 },
|
|
{ "ACTL", 14, 1 },
|
|
{ "PEAK", 9, 5 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x33330, 0 },
|
|
{ "FVOFFSKP", 15, 1 },
|
|
{ "FGAINCHK", 14, 1 },
|
|
{ "FH1ACAL", 13, 1 },
|
|
{ "FH1AFLTR", 11, 2 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "WGAIN", 8, 2 },
|
|
{ "GAIN_STAT", 7, 1 },
|
|
{ "T5VGAIN", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x33334, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33338, 0 },
|
|
{ "PMCFG", 6, 2 },
|
|
{ "PMOFFTIME", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1", 0x3333c, 0 },
|
|
{ "SELI", 9, 1 },
|
|
{ "SERVREF", 5, 3 },
|
|
{ "IQAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2", 0x33340, 0 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33344, 0 },
|
|
{ "SAVEADAC", 8, 1 },
|
|
{ "LOAD2", 7, 1 },
|
|
{ "LOAD1", 6, 1 },
|
|
{ "WRTACC2", 5, 1 },
|
|
{ "WRTACC1", 4, 1 },
|
|
{ "SELAPAN", 3, 1 },
|
|
{ "DASEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x33348, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN", 0x3334c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x33350, 0 },
|
|
{ "ADAC2", 8, 8 },
|
|
{ "ADAC1", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL", 0x33354, 0 },
|
|
{ "FACCPLDYN", 13, 1 },
|
|
{ "ACCPLGAIN", 10, 3 },
|
|
{ "ACCPLREF", 8, 2 },
|
|
{ "ACCPLSTEP", 6, 2 },
|
|
{ "ACCPLASTEP", 1, 5 },
|
|
{ "FACCPL", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE", 0x33358, 0 },
|
|
{ "ACCPLMEANS", 15, 1 },
|
|
{ "CDROVREN", 8, 1 },
|
|
{ "ACCPLBIAS", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET", 0x3335c, 0 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33360, 0 },
|
|
{ "H1OX", 8, 6 },
|
|
{ "H1EX", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR", 0x33364, 0 },
|
|
{ "PILOCK", 10, 1 },
|
|
{ "UNPKPKA", 2, 6 },
|
|
{ "UNPKVGA", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH", 0x33368, 0 },
|
|
{ "OVRAC", 15, 1 },
|
|
{ "OVRPK", 14, 1 },
|
|
{ "OVRTAILS", 12, 2 },
|
|
{ "OVRTAILV", 9, 3 },
|
|
{ "OVRCAP", 8, 1 },
|
|
{ "OVRDCDPRE", 7, 1 },
|
|
{ "OVRDCDPST", 6, 1 },
|
|
{ "DCVSCTMODE", 2, 1 },
|
|
{ "CDRANLGSW", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3336c, 0 },
|
|
{ "PFLAG", 5, 2 },
|
|
{ "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33370, 0 },
|
|
{ "DACCLIP", 15, 1 },
|
|
{ "DPCFRZ", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCLKNQ", 11, 1 },
|
|
{ "DPCWDFE", 10, 1 },
|
|
{ "DPCWPK", 9, 1 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x33374, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "VIEWSCAN", 4, 1 },
|
|
{ "ODEC", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x33378, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "ACCCMP", 11, 1 },
|
|
{ "DCCCMP", 10, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5IQCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3337c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x33380, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FDCCAL", 14, 1 },
|
|
{ "FROTCAL", 13, 1 },
|
|
{ "FIQAMP", 12, 1 },
|
|
{ "FRPTCALF", 11, 1 },
|
|
{ "FINTCALGS", 10, 1 },
|
|
{ "FDCC", 9, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FDCD", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FINTRCALDYN", 1, 1 },
|
|
{ "FQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL", 0x33384, 0 },
|
|
{ "QCCIND", 13, 1 },
|
|
{ "DCDIND", 10, 3 },
|
|
{ "DCCIND", 8, 2 },
|
|
{ "CFSEL", 5, 1 },
|
|
{ "LOFCH", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE", 0x33388, 0 },
|
|
{ "LOFU", 8, 7 },
|
|
{ "LOFL", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST", 0x3338c, 0 },
|
|
{ "HBISTMAN", 12, 1 },
|
|
{ "HBISTRES", 11, 1 },
|
|
{ "HBISTSP", 8, 3 },
|
|
{ "HBISTEN", 7, 1 },
|
|
{ "HBISTRST", 6, 1 },
|
|
{ "HCOMP", 5, 1 },
|
|
{ "HPASS", 4, 1 },
|
|
{ "HSEL", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST", 0x33390, 0 },
|
|
{ "ACCCMP", 13, 1 },
|
|
{ "ACCEN", 12, 1 },
|
|
{ "ACCRST", 11, 1 },
|
|
{ "ACCIND", 8, 3 },
|
|
{ "ACCRD", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER", 0x33398, 0 },
|
|
{ "LFREG", 15, 1 },
|
|
{ "LFRC", 14, 1 },
|
|
{ "LGIDLE", 13, 1 },
|
|
{ "LFTGT", 8, 5 },
|
|
{ "LGTGT", 7, 1 },
|
|
{ "LRDY", 6, 1 },
|
|
{ "LIDLE", 5, 1 },
|
|
{ "LCURR", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3339c, 0 },
|
|
{ "OFFSN", 13, 2 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x333a0, 0 },
|
|
{ "RX_OVRSUMPD", 15, 1 },
|
|
{ "RX_OVRKBPD", 14, 1 },
|
|
{ "RX_OVRDIVPD", 13, 1 },
|
|
{ "RX_OFFVGADIS", 12, 1 },
|
|
{ "RX_OFFACDIS", 11, 1 },
|
|
{ "RX_VTERM", 10, 1 },
|
|
{ "RX_DISSPY2D", 8, 1 },
|
|
{ "RX_OBSOVEN", 7, 1 },
|
|
{ "RX_LINKANLGSW", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x333a4, 0 },
|
|
{ "INTDACEGS", 13, 3 },
|
|
{ "INTDACE", 8, 5 },
|
|
{ "INTDACGS", 6, 2 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x333a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x333ac, 0 },
|
|
{ "SMQM", 13, 3 },
|
|
{ "SMQ", 5, 8 },
|
|
{ "EMMD", 3, 2 },
|
|
{ "EMBRDY", 2, 1 },
|
|
{ "EMBUMP", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x333b0, 0 },
|
|
{ "EMSF", 13, 1 },
|
|
{ "EMDATA59", 12, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x333b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x333b8, 0 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3", 0x333bc, 0 },
|
|
{ "FTIMEOUT", 15, 1 },
|
|
{ "FROTCAL4", 14, 1 },
|
|
{ "FDCD2", 13, 1 },
|
|
{ "FPRBSPOLTOG", 12, 1 },
|
|
{ "FPRBSOFF2", 11, 1 },
|
|
{ "FDDCAL2", 10, 1 },
|
|
{ "FDDCFLTR", 9, 1 },
|
|
{ "FDAC6", 8, 1 },
|
|
{ "FDDC5", 7, 1 },
|
|
{ "FDDC3456", 6, 1 },
|
|
{ "FSPY2DATA", 5, 1 },
|
|
{ "FPHSLOCK", 4, 1 },
|
|
{ "FCLKALGN", 3, 1 },
|
|
{ "FCLKALDYN", 2, 1 },
|
|
{ "FDFE", 1, 1 },
|
|
{ "FPRBSOFF", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_TAP_CONTROL", 0x333c0, 0 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_TAP", 0x333c4, 0 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2", 0x333e4, 0 },
|
|
{ "STNDBYSTAT", 15, 1 },
|
|
{ "CALSDONE", 14, 1 },
|
|
{ "ACISRCCMP", 5, 1 },
|
|
{ "PRBSOFFCMP", 4, 1 },
|
|
{ "CLKALGNCMP", 3, 1 },
|
|
{ "ROTFCMP", 2, 1 },
|
|
{ "DCDCMP", 1, 1 },
|
|
{ "QCCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x333e8, 0 },
|
|
{ "FCSADJ", 6, 1 },
|
|
{ "CSIND", 3, 2 },
|
|
{ "CSVAL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL", 0x333ec, 0 },
|
|
{ "DCDTMDOUT", 15, 1 },
|
|
{ "DCDTOEN", 14, 1 },
|
|
{ "DCDLOCK", 13, 1 },
|
|
{ "DCDSTEP", 11, 2 },
|
|
{ "DCDALTWPDIS", 10, 1 },
|
|
{ "DCDOVRDEN", 9, 1 },
|
|
{ "DCCAOVRDEN", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL", 0x333f0, 0 },
|
|
{ "PRBSMODE", 14, 2 },
|
|
{ "DCCSTEP", 10, 2 },
|
|
{ "DCCOVRDEN", 9, 1 },
|
|
{ "DCCLOCK", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL", 0x333f4, 0 },
|
|
{ "DCCQCCMODE", 15, 1 },
|
|
{ "DCCQCCDYN", 14, 1 },
|
|
{ "DCCQCCHOLD", 13, 1 },
|
|
{ "QCCSTEP", 10, 2 },
|
|
{ "QCCOVRDEN", 9, 1 },
|
|
{ "QCCLOCK", 8, 1 },
|
|
{ "QCCSIGN", 6, 2 },
|
|
{ "QCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x333f8, 0 },
|
|
{ "TSTCMP", 15, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x333fc, 0 },
|
|
{ "CALMODEEDGE", 14, 1 },
|
|
{ "TESTCAP", 13, 1 },
|
|
{ "SNAPEN", 12, 1 },
|
|
{ "ASYNCDIR", 11, 1 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x33600, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_MODE8023AZ", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x33604, 0 },
|
|
{ "APLYDCD", 15, 1 },
|
|
{ "PPOL", 13, 2 },
|
|
{ "PCLKSEL", 11, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x33608, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3360c, 0 },
|
|
{ "H1ANOFST", 12, 4 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "TMSCAL", 8, 2 },
|
|
{ "APADJ", 7, 1 },
|
|
{ "RSEL", 6, 1 },
|
|
{ "PHOFFS", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x33610, 0 },
|
|
{ "ROTA", 8, 6 },
|
|
{ "ROTD", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x33614, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROTE", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33618, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOFFF", 8, 4 },
|
|
{ "RAOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3361c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x33620, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 8, 4 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x33624, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x33628, 0 },
|
|
{ "REQWOV", 15, 1 },
|
|
{ "RASEL", 11, 3 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3362c, 0 },
|
|
{ "WRAPSEL", 15, 1 },
|
|
{ "ACTL", 14, 1 },
|
|
{ "PEAK", 9, 5 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x33630, 0 },
|
|
{ "FVOFFSKP", 15, 1 },
|
|
{ "FGAINCHK", 14, 1 },
|
|
{ "FH1ACAL", 13, 1 },
|
|
{ "FH1AFLTR", 11, 2 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "WGAIN", 8, 2 },
|
|
{ "GAIN_STAT", 7, 1 },
|
|
{ "T5VGAIN", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x33634, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33638, 0 },
|
|
{ "PMCFG", 6, 2 },
|
|
{ "PMOFFTIME", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1", 0x3363c, 0 },
|
|
{ "SELI", 9, 1 },
|
|
{ "SERVREF", 5, 3 },
|
|
{ "IQAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2", 0x33640, 0 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33644, 0 },
|
|
{ "SAVEADAC", 8, 1 },
|
|
{ "LOAD2", 7, 1 },
|
|
{ "LOAD1", 6, 1 },
|
|
{ "WRTACC2", 5, 1 },
|
|
{ "WRTACC1", 4, 1 },
|
|
{ "SELAPAN", 3, 1 },
|
|
{ "DASEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x33648, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN", 0x3364c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x33650, 0 },
|
|
{ "ADAC2", 8, 8 },
|
|
{ "ADAC1", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL", 0x33654, 0 },
|
|
{ "FACCPLDYN", 13, 1 },
|
|
{ "ACCPLGAIN", 10, 3 },
|
|
{ "ACCPLREF", 8, 2 },
|
|
{ "ACCPLSTEP", 6, 2 },
|
|
{ "ACCPLASTEP", 1, 5 },
|
|
{ "FACCPL", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE", 0x33658, 0 },
|
|
{ "ACCPLMEANS", 15, 1 },
|
|
{ "CDROVREN", 8, 1 },
|
|
{ "ACCPLBIAS", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET", 0x3365c, 0 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33660, 0 },
|
|
{ "H1OX", 8, 6 },
|
|
{ "H1EX", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR", 0x33664, 0 },
|
|
{ "PILOCK", 10, 1 },
|
|
{ "UNPKPKA", 2, 6 },
|
|
{ "UNPKVGA", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH", 0x33668, 0 },
|
|
{ "OVRAC", 15, 1 },
|
|
{ "OVRPK", 14, 1 },
|
|
{ "OVRTAILS", 12, 2 },
|
|
{ "OVRTAILV", 9, 3 },
|
|
{ "OVRCAP", 8, 1 },
|
|
{ "OVRDCDPRE", 7, 1 },
|
|
{ "OVRDCDPST", 6, 1 },
|
|
{ "DCVSCTMODE", 2, 1 },
|
|
{ "CDRANLGSW", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3366c, 0 },
|
|
{ "PFLAG", 5, 2 },
|
|
{ "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33670, 0 },
|
|
{ "DACCLIP", 15, 1 },
|
|
{ "DPCFRZ", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCLKNQ", 11, 1 },
|
|
{ "DPCWDFE", 10, 1 },
|
|
{ "DPCWPK", 9, 1 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x33674, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "VIEWSCAN", 4, 1 },
|
|
{ "ODEC", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x33678, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "ACCCMP", 11, 1 },
|
|
{ "DCCCMP", 10, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5IQCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3367c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x33680, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FDCCAL", 14, 1 },
|
|
{ "FROTCAL", 13, 1 },
|
|
{ "FIQAMP", 12, 1 },
|
|
{ "FRPTCALF", 11, 1 },
|
|
{ "FINTCALGS", 10, 1 },
|
|
{ "FDCC", 9, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FDCD", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FINTRCALDYN", 1, 1 },
|
|
{ "FQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL", 0x33684, 0 },
|
|
{ "QCCIND", 13, 1 },
|
|
{ "DCDIND", 10, 3 },
|
|
{ "DCCIND", 8, 2 },
|
|
{ "CFSEL", 5, 1 },
|
|
{ "LOFCH", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE", 0x33688, 0 },
|
|
{ "LOFU", 8, 7 },
|
|
{ "LOFL", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST", 0x3368c, 0 },
|
|
{ "HBISTMAN", 12, 1 },
|
|
{ "HBISTRES", 11, 1 },
|
|
{ "HBISTSP", 8, 3 },
|
|
{ "HBISTEN", 7, 1 },
|
|
{ "HBISTRST", 6, 1 },
|
|
{ "HCOMP", 5, 1 },
|
|
{ "HPASS", 4, 1 },
|
|
{ "HSEL", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST", 0x33690, 0 },
|
|
{ "ACCCMP", 13, 1 },
|
|
{ "ACCEN", 12, 1 },
|
|
{ "ACCRST", 11, 1 },
|
|
{ "ACCIND", 8, 3 },
|
|
{ "ACCRD", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER", 0x33698, 0 },
|
|
{ "LFREG", 15, 1 },
|
|
{ "LFRC", 14, 1 },
|
|
{ "LGIDLE", 13, 1 },
|
|
{ "LFTGT", 8, 5 },
|
|
{ "LGTGT", 7, 1 },
|
|
{ "LRDY", 6, 1 },
|
|
{ "LIDLE", 5, 1 },
|
|
{ "LCURR", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3369c, 0 },
|
|
{ "OFFSN", 13, 2 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x336a0, 0 },
|
|
{ "RX_OVRSUMPD", 15, 1 },
|
|
{ "RX_OVRKBPD", 14, 1 },
|
|
{ "RX_OVRDIVPD", 13, 1 },
|
|
{ "RX_OFFVGADIS", 12, 1 },
|
|
{ "RX_OFFACDIS", 11, 1 },
|
|
{ "RX_VTERM", 10, 1 },
|
|
{ "RX_DISSPY2D", 8, 1 },
|
|
{ "RX_OBSOVEN", 7, 1 },
|
|
{ "RX_LINKANLGSW", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x336a4, 0 },
|
|
{ "INTDACEGS", 13, 3 },
|
|
{ "INTDACE", 8, 5 },
|
|
{ "INTDACGS", 6, 2 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x336a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x336ac, 0 },
|
|
{ "SMQM", 13, 3 },
|
|
{ "SMQ", 5, 8 },
|
|
{ "EMMD", 3, 2 },
|
|
{ "EMBRDY", 2, 1 },
|
|
{ "EMBUMP", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x336b0, 0 },
|
|
{ "EMSF", 13, 1 },
|
|
{ "EMDATA59", 12, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x336b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x336b8, 0 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3", 0x336bc, 0 },
|
|
{ "FTIMEOUT", 15, 1 },
|
|
{ "FROTCAL4", 14, 1 },
|
|
{ "FDCD2", 13, 1 },
|
|
{ "FPRBSPOLTOG", 12, 1 },
|
|
{ "FPRBSOFF2", 11, 1 },
|
|
{ "FDDCAL2", 10, 1 },
|
|
{ "FDDCFLTR", 9, 1 },
|
|
{ "FDAC6", 8, 1 },
|
|
{ "FDDC5", 7, 1 },
|
|
{ "FDDC3456", 6, 1 },
|
|
{ "FSPY2DATA", 5, 1 },
|
|
{ "FPHSLOCK", 4, 1 },
|
|
{ "FCLKALGN", 3, 1 },
|
|
{ "FCLKALDYN", 2, 1 },
|
|
{ "FDFE", 1, 1 },
|
|
{ "FPRBSOFF", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_TAP_CONTROL", 0x336c0, 0 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_TAP", 0x336c4, 0 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2", 0x336e4, 0 },
|
|
{ "STNDBYSTAT", 15, 1 },
|
|
{ "CALSDONE", 14, 1 },
|
|
{ "ACISRCCMP", 5, 1 },
|
|
{ "PRBSOFFCMP", 4, 1 },
|
|
{ "CLKALGNCMP", 3, 1 },
|
|
{ "ROTFCMP", 2, 1 },
|
|
{ "DCDCMP", 1, 1 },
|
|
{ "QCCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x336e8, 0 },
|
|
{ "FCSADJ", 6, 1 },
|
|
{ "CSIND", 3, 2 },
|
|
{ "CSVAL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL", 0x336ec, 0 },
|
|
{ "DCDTMDOUT", 15, 1 },
|
|
{ "DCDTOEN", 14, 1 },
|
|
{ "DCDLOCK", 13, 1 },
|
|
{ "DCDSTEP", 11, 2 },
|
|
{ "DCDALTWPDIS", 10, 1 },
|
|
{ "DCDOVRDEN", 9, 1 },
|
|
{ "DCCAOVRDEN", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL", 0x336f0, 0 },
|
|
{ "PRBSMODE", 14, 2 },
|
|
{ "DCCSTEP", 10, 2 },
|
|
{ "DCCOVRDEN", 9, 1 },
|
|
{ "DCCLOCK", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL", 0x336f4, 0 },
|
|
{ "DCCQCCMODE", 15, 1 },
|
|
{ "DCCQCCDYN", 14, 1 },
|
|
{ "DCCQCCHOLD", 13, 1 },
|
|
{ "QCCSTEP", 10, 2 },
|
|
{ "QCCOVRDEN", 9, 1 },
|
|
{ "QCCLOCK", 8, 1 },
|
|
{ "QCCSIGN", 6, 2 },
|
|
{ "QCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x336f8, 0 },
|
|
{ "TSTCMP", 15, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x336fc, 0 },
|
|
{ "CALMODEEDGE", 14, 1 },
|
|
{ "TESTCAP", 13, 1 },
|
|
{ "SNAPEN", 12, 1 },
|
|
{ "ASYNCDIR", 11, 1 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x33700, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_MODE8023AZ", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x33704, 0 },
|
|
{ "APLYDCD", 15, 1 },
|
|
{ "PPOL", 13, 2 },
|
|
{ "PCLKSEL", 11, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x33708, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3370c, 0 },
|
|
{ "H1ANOFST", 12, 4 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "TMSCAL", 8, 2 },
|
|
{ "APADJ", 7, 1 },
|
|
{ "RSEL", 6, 1 },
|
|
{ "PHOFFS", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x33710, 0 },
|
|
{ "ROTA", 8, 6 },
|
|
{ "ROTD", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x33714, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROTE", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33718, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOFFF", 8, 4 },
|
|
{ "RAOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3371c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x33720, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 8, 4 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x33724, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x33728, 0 },
|
|
{ "REQWOV", 15, 1 },
|
|
{ "RASEL", 11, 3 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3372c, 0 },
|
|
{ "WRAPSEL", 15, 1 },
|
|
{ "ACTL", 14, 1 },
|
|
{ "PEAK", 9, 5 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x33730, 0 },
|
|
{ "FVOFFSKP", 15, 1 },
|
|
{ "FGAINCHK", 14, 1 },
|
|
{ "FH1ACAL", 13, 1 },
|
|
{ "FH1AFLTR", 11, 2 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "WGAIN", 8, 2 },
|
|
{ "GAIN_STAT", 7, 1 },
|
|
{ "T5VGAIN", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x33734, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33738, 0 },
|
|
{ "PMCFG", 6, 2 },
|
|
{ "PMOFFTIME", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1", 0x3373c, 0 },
|
|
{ "SELI", 9, 1 },
|
|
{ "SERVREF", 5, 3 },
|
|
{ "IQAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2", 0x33740, 0 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33744, 0 },
|
|
{ "SAVEADAC", 8, 1 },
|
|
{ "LOAD2", 7, 1 },
|
|
{ "LOAD1", 6, 1 },
|
|
{ "WRTACC2", 5, 1 },
|
|
{ "WRTACC1", 4, 1 },
|
|
{ "SELAPAN", 3, 1 },
|
|
{ "DASEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x33748, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN", 0x3374c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x33750, 0 },
|
|
{ "ADAC2", 8, 8 },
|
|
{ "ADAC1", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL", 0x33754, 0 },
|
|
{ "FACCPLDYN", 13, 1 },
|
|
{ "ACCPLGAIN", 10, 3 },
|
|
{ "ACCPLREF", 8, 2 },
|
|
{ "ACCPLSTEP", 6, 2 },
|
|
{ "ACCPLASTEP", 1, 5 },
|
|
{ "FACCPL", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE", 0x33758, 0 },
|
|
{ "ACCPLMEANS", 15, 1 },
|
|
{ "CDROVREN", 8, 1 },
|
|
{ "ACCPLBIAS", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET", 0x3375c, 0 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33760, 0 },
|
|
{ "H1OX", 8, 6 },
|
|
{ "H1EX", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR", 0x33764, 0 },
|
|
{ "PILOCK", 10, 1 },
|
|
{ "UNPKPKA", 2, 6 },
|
|
{ "UNPKVGA", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH", 0x33768, 0 },
|
|
{ "OVRAC", 15, 1 },
|
|
{ "OVRPK", 14, 1 },
|
|
{ "OVRTAILS", 12, 2 },
|
|
{ "OVRTAILV", 9, 3 },
|
|
{ "OVRCAP", 8, 1 },
|
|
{ "OVRDCDPRE", 7, 1 },
|
|
{ "OVRDCDPST", 6, 1 },
|
|
{ "DCVSCTMODE", 2, 1 },
|
|
{ "CDRANLGSW", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3376c, 0 },
|
|
{ "PFLAG", 5, 2 },
|
|
{ "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33770, 0 },
|
|
{ "DACCLIP", 15, 1 },
|
|
{ "DPCFRZ", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCLKNQ", 11, 1 },
|
|
{ "DPCWDFE", 10, 1 },
|
|
{ "DPCWPK", 9, 1 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x33774, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "VIEWSCAN", 4, 1 },
|
|
{ "ODEC", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x33778, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "ACCCMP", 11, 1 },
|
|
{ "DCCCMP", 10, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5IQCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3377c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x33780, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FDCCAL", 14, 1 },
|
|
{ "FROTCAL", 13, 1 },
|
|
{ "FIQAMP", 12, 1 },
|
|
{ "FRPTCALF", 11, 1 },
|
|
{ "FINTCALGS", 10, 1 },
|
|
{ "FDCC", 9, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FDCD", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FINTRCALDYN", 1, 1 },
|
|
{ "FQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL", 0x33784, 0 },
|
|
{ "QCCIND", 13, 1 },
|
|
{ "DCDIND", 10, 3 },
|
|
{ "DCCIND", 8, 2 },
|
|
{ "CFSEL", 5, 1 },
|
|
{ "LOFCH", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE", 0x33788, 0 },
|
|
{ "LOFU", 8, 7 },
|
|
{ "LOFL", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST", 0x3378c, 0 },
|
|
{ "HBISTMAN", 12, 1 },
|
|
{ "HBISTRES", 11, 1 },
|
|
{ "HBISTSP", 8, 3 },
|
|
{ "HBISTEN", 7, 1 },
|
|
{ "HBISTRST", 6, 1 },
|
|
{ "HCOMP", 5, 1 },
|
|
{ "HPASS", 4, 1 },
|
|
{ "HSEL", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST", 0x33790, 0 },
|
|
{ "ACCCMP", 13, 1 },
|
|
{ "ACCEN", 12, 1 },
|
|
{ "ACCRST", 11, 1 },
|
|
{ "ACCIND", 8, 3 },
|
|
{ "ACCRD", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER", 0x33798, 0 },
|
|
{ "LFREG", 15, 1 },
|
|
{ "LFRC", 14, 1 },
|
|
{ "LGIDLE", 13, 1 },
|
|
{ "LFTGT", 8, 5 },
|
|
{ "LGTGT", 7, 1 },
|
|
{ "LRDY", 6, 1 },
|
|
{ "LIDLE", 5, 1 },
|
|
{ "LCURR", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3379c, 0 },
|
|
{ "OFFSN", 13, 2 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x337a0, 0 },
|
|
{ "RX_OVRSUMPD", 15, 1 },
|
|
{ "RX_OVRKBPD", 14, 1 },
|
|
{ "RX_OVRDIVPD", 13, 1 },
|
|
{ "RX_OFFVGADIS", 12, 1 },
|
|
{ "RX_OFFACDIS", 11, 1 },
|
|
{ "RX_VTERM", 10, 1 },
|
|
{ "RX_DISSPY2D", 8, 1 },
|
|
{ "RX_OBSOVEN", 7, 1 },
|
|
{ "RX_LINKANLGSW", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x337a4, 0 },
|
|
{ "INTDACEGS", 13, 3 },
|
|
{ "INTDACE", 8, 5 },
|
|
{ "INTDACGS", 6, 2 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x337a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x337ac, 0 },
|
|
{ "SMQM", 13, 3 },
|
|
{ "SMQ", 5, 8 },
|
|
{ "EMMD", 3, 2 },
|
|
{ "EMBRDY", 2, 1 },
|
|
{ "EMBUMP", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x337b0, 0 },
|
|
{ "EMSF", 13, 1 },
|
|
{ "EMDATA59", 12, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x337b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x337b8, 0 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3", 0x337bc, 0 },
|
|
{ "FTIMEOUT", 15, 1 },
|
|
{ "FROTCAL4", 14, 1 },
|
|
{ "FDCD2", 13, 1 },
|
|
{ "FPRBSPOLTOG", 12, 1 },
|
|
{ "FPRBSOFF2", 11, 1 },
|
|
{ "FDDCAL2", 10, 1 },
|
|
{ "FDDCFLTR", 9, 1 },
|
|
{ "FDAC6", 8, 1 },
|
|
{ "FDDC5", 7, 1 },
|
|
{ "FDDC3456", 6, 1 },
|
|
{ "FSPY2DATA", 5, 1 },
|
|
{ "FPHSLOCK", 4, 1 },
|
|
{ "FCLKALGN", 3, 1 },
|
|
{ "FCLKALDYN", 2, 1 },
|
|
{ "FDFE", 1, 1 },
|
|
{ "FPRBSOFF", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_TAP_CONTROL", 0x337c0, 0 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_TAP", 0x337c4, 0 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2", 0x337e4, 0 },
|
|
{ "STNDBYSTAT", 15, 1 },
|
|
{ "CALSDONE", 14, 1 },
|
|
{ "ACISRCCMP", 5, 1 },
|
|
{ "PRBSOFFCMP", 4, 1 },
|
|
{ "CLKALGNCMP", 3, 1 },
|
|
{ "ROTFCMP", 2, 1 },
|
|
{ "DCDCMP", 1, 1 },
|
|
{ "QCCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x337e8, 0 },
|
|
{ "FCSADJ", 6, 1 },
|
|
{ "CSIND", 3, 2 },
|
|
{ "CSVAL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL", 0x337ec, 0 },
|
|
{ "DCDTMDOUT", 15, 1 },
|
|
{ "DCDTOEN", 14, 1 },
|
|
{ "DCDLOCK", 13, 1 },
|
|
{ "DCDSTEP", 11, 2 },
|
|
{ "DCDALTWPDIS", 10, 1 },
|
|
{ "DCDOVRDEN", 9, 1 },
|
|
{ "DCCAOVRDEN", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL", 0x337f0, 0 },
|
|
{ "PRBSMODE", 14, 2 },
|
|
{ "DCCSTEP", 10, 2 },
|
|
{ "DCCOVRDEN", 9, 1 },
|
|
{ "DCCLOCK", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL", 0x337f4, 0 },
|
|
{ "DCCQCCMODE", 15, 1 },
|
|
{ "DCCQCCDYN", 14, 1 },
|
|
{ "DCCQCCHOLD", 13, 1 },
|
|
{ "QCCSTEP", 10, 2 },
|
|
{ "QCCOVRDEN", 9, 1 },
|
|
{ "QCCLOCK", 8, 1 },
|
|
{ "QCCSIGN", 6, 2 },
|
|
{ "QCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x337f8, 0 },
|
|
{ "TSTCMP", 15, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x337fc, 0 },
|
|
{ "CALMODEEDGE", 14, 1 },
|
|
{ "TESTCAP", 13, 1 },
|
|
{ "SNAPEN", 12, 1 },
|
|
{ "ASYNCDIR", 11, 1 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x33a00, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_MODE8023AZ", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x33a04, 0 },
|
|
{ "APLYDCD", 15, 1 },
|
|
{ "PPOL", 13, 2 },
|
|
{ "PCLKSEL", 11, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x33a08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x33a0c, 0 },
|
|
{ "H1ANOFST", 12, 4 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "TMSCAL", 8, 2 },
|
|
{ "APADJ", 7, 1 },
|
|
{ "RSEL", 6, 1 },
|
|
{ "PHOFFS", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x33a10, 0 },
|
|
{ "ROTA", 8, 6 },
|
|
{ "ROTD", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x33a14, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROTE", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33a18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOFFF", 8, 4 },
|
|
{ "RAOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x33a1c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x33a20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 8, 4 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x33a24, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x33a28, 0 },
|
|
{ "REQWOV", 15, 1 },
|
|
{ "RASEL", 11, 3 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x33a2c, 0 },
|
|
{ "WRAPSEL", 15, 1 },
|
|
{ "ACTL", 14, 1 },
|
|
{ "PEAK", 9, 5 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x33a30, 0 },
|
|
{ "FVOFFSKP", 15, 1 },
|
|
{ "FGAINCHK", 14, 1 },
|
|
{ "FH1ACAL", 13, 1 },
|
|
{ "FH1AFLTR", 11, 2 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "WGAIN", 8, 2 },
|
|
{ "GAIN_STAT", 7, 1 },
|
|
{ "T5VGAIN", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x33a34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33a38, 0 },
|
|
{ "PMCFG", 6, 2 },
|
|
{ "PMOFFTIME", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1", 0x33a3c, 0 },
|
|
{ "SELI", 9, 1 },
|
|
{ "SERVREF", 5, 3 },
|
|
{ "IQAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2", 0x33a40, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33a44, 0 },
|
|
{ "SAVEADAC", 8, 1 },
|
|
{ "LOAD2", 7, 1 },
|
|
{ "LOAD1", 6, 1 },
|
|
{ "WRTACC2", 5, 1 },
|
|
{ "WRTACC1", 4, 1 },
|
|
{ "SELAPAN", 3, 1 },
|
|
{ "DASEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x33a48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN", 0x33a4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x33a50, 0 },
|
|
{ "ADAC2", 8, 8 },
|
|
{ "ADAC1", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL", 0x33a54, 0 },
|
|
{ "FACCPLDYN", 13, 1 },
|
|
{ "ACCPLGAIN", 10, 3 },
|
|
{ "ACCPLREF", 8, 2 },
|
|
{ "ACCPLSTEP", 6, 2 },
|
|
{ "ACCPLASTEP", 1, 5 },
|
|
{ "FACCPL", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE", 0x33a58, 0 },
|
|
{ "ACCPLMEANS", 15, 1 },
|
|
{ "CDROVREN", 8, 1 },
|
|
{ "ACCPLBIAS", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET", 0x33a5c, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33a60, 0 },
|
|
{ "H1OX", 8, 6 },
|
|
{ "H1EX", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR", 0x33a64, 0 },
|
|
{ "PILOCK", 10, 1 },
|
|
{ "UNPKPKA", 2, 6 },
|
|
{ "UNPKVGA", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH", 0x33a68, 0 },
|
|
{ "OVRAC", 15, 1 },
|
|
{ "OVRPK", 14, 1 },
|
|
{ "OVRTAILS", 12, 2 },
|
|
{ "OVRTAILV", 9, 3 },
|
|
{ "OVRCAP", 8, 1 },
|
|
{ "OVRDCDPRE", 7, 1 },
|
|
{ "OVRDCDPST", 6, 1 },
|
|
{ "DCVSCTMODE", 2, 1 },
|
|
{ "CDRANLGSW", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x33a6c, 0 },
|
|
{ "PFLAG", 5, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33a70, 0 },
|
|
{ "DACCLIP", 15, 1 },
|
|
{ "DPCFRZ", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCLKNQ", 11, 1 },
|
|
{ "DPCWDFE", 10, 1 },
|
|
{ "DPCWPK", 9, 1 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x33a74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "VIEWSCAN", 4, 1 },
|
|
{ "ODEC", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x33a78, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "ACCCMP", 11, 1 },
|
|
{ "DCCCMP", 10, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5IQCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x33a7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x33a80, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FDCCAL", 14, 1 },
|
|
{ "FROTCAL", 13, 1 },
|
|
{ "FIQAMP", 12, 1 },
|
|
{ "FRPTCALF", 11, 1 },
|
|
{ "FINTCALGS", 10, 1 },
|
|
{ "FDCC", 9, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FDCD", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FINTRCALDYN", 1, 1 },
|
|
{ "FQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL", 0x33a84, 0 },
|
|
{ "QCCIND", 13, 1 },
|
|
{ "DCDIND", 10, 3 },
|
|
{ "DCCIND", 8, 2 },
|
|
{ "CFSEL", 5, 1 },
|
|
{ "LOFCH", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE", 0x33a88, 0 },
|
|
{ "LOFU", 8, 7 },
|
|
{ "LOFL", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST", 0x33a8c, 0 },
|
|
{ "HBISTMAN", 12, 1 },
|
|
{ "HBISTRES", 11, 1 },
|
|
{ "HBISTSP", 8, 3 },
|
|
{ "HBISTEN", 7, 1 },
|
|
{ "HBISTRST", 6, 1 },
|
|
{ "HCOMP", 5, 1 },
|
|
{ "HPASS", 4, 1 },
|
|
{ "HSEL", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST", 0x33a90, 0 },
|
|
{ "ACCCMP", 13, 1 },
|
|
{ "ACCEN", 12, 1 },
|
|
{ "ACCRST", 11, 1 },
|
|
{ "ACCIND", 8, 3 },
|
|
{ "ACCRD", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER", 0x33a98, 0 },
|
|
{ "LFREG", 15, 1 },
|
|
{ "LFRC", 14, 1 },
|
|
{ "LGIDLE", 13, 1 },
|
|
{ "LFTGT", 8, 5 },
|
|
{ "LGTGT", 7, 1 },
|
|
{ "LRDY", 6, 1 },
|
|
{ "LIDLE", 5, 1 },
|
|
{ "LCURR", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x33a9c, 0 },
|
|
{ "OFFSN", 13, 2 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x33aa0, 0 },
|
|
{ "RX_OVRSUMPD", 15, 1 },
|
|
{ "RX_OVRKBPD", 14, 1 },
|
|
{ "RX_OVRDIVPD", 13, 1 },
|
|
{ "RX_OFFVGADIS", 12, 1 },
|
|
{ "RX_OFFACDIS", 11, 1 },
|
|
{ "RX_VTERM", 10, 1 },
|
|
{ "RX_DISSPY2D", 8, 1 },
|
|
{ "RX_OBSOVEN", 7, 1 },
|
|
{ "RX_LINKANLGSW", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x33aa4, 0 },
|
|
{ "INTDACEGS", 13, 3 },
|
|
{ "INTDACE", 8, 5 },
|
|
{ "INTDACGS", 6, 2 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x33aa8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x33aac, 0 },
|
|
{ "SMQM", 13, 3 },
|
|
{ "SMQ", 5, 8 },
|
|
{ "EMMD", 3, 2 },
|
|
{ "EMBRDY", 2, 1 },
|
|
{ "EMBUMP", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x33ab0, 0 },
|
|
{ "EMSF", 13, 1 },
|
|
{ "EMDATA59", 12, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x33ab4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x33ab8, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3", 0x33abc, 0 },
|
|
{ "FTIMEOUT", 15, 1 },
|
|
{ "FROTCAL4", 14, 1 },
|
|
{ "FDCD2", 13, 1 },
|
|
{ "FPRBSPOLTOG", 12, 1 },
|
|
{ "FPRBSOFF2", 11, 1 },
|
|
{ "FDDCAL2", 10, 1 },
|
|
{ "FDDCFLTR", 9, 1 },
|
|
{ "FDAC6", 8, 1 },
|
|
{ "FDDC5", 7, 1 },
|
|
{ "FDDC3456", 6, 1 },
|
|
{ "FSPY2DATA", 5, 1 },
|
|
{ "FPHSLOCK", 4, 1 },
|
|
{ "FCLKALGN", 3, 1 },
|
|
{ "FCLKALDYN", 2, 1 },
|
|
{ "FDFE", 1, 1 },
|
|
{ "FPRBSOFF", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL", 0x33ac0, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_TAP", 0x33ac4, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2", 0x33ae4, 0 },
|
|
{ "STNDBYSTAT", 15, 1 },
|
|
{ "CALSDONE", 14, 1 },
|
|
{ "ACISRCCMP", 5, 1 },
|
|
{ "PRBSOFFCMP", 4, 1 },
|
|
{ "CLKALGNCMP", 3, 1 },
|
|
{ "ROTFCMP", 2, 1 },
|
|
{ "DCDCMP", 1, 1 },
|
|
{ "QCCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x33ae8, 0 },
|
|
{ "FCSADJ", 6, 1 },
|
|
{ "CSIND", 3, 2 },
|
|
{ "CSVAL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL", 0x33aec, 0 },
|
|
{ "DCDTMDOUT", 15, 1 },
|
|
{ "DCDTOEN", 14, 1 },
|
|
{ "DCDLOCK", 13, 1 },
|
|
{ "DCDSTEP", 11, 2 },
|
|
{ "DCDALTWPDIS", 10, 1 },
|
|
{ "DCDOVRDEN", 9, 1 },
|
|
{ "DCCAOVRDEN", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL", 0x33af0, 0 },
|
|
{ "PRBSMODE", 14, 2 },
|
|
{ "DCCSTEP", 10, 2 },
|
|
{ "DCCOVRDEN", 9, 1 },
|
|
{ "DCCLOCK", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL", 0x33af4, 0 },
|
|
{ "DCCQCCMODE", 15, 1 },
|
|
{ "DCCQCCDYN", 14, 1 },
|
|
{ "DCCQCCHOLD", 13, 1 },
|
|
{ "QCCSTEP", 10, 2 },
|
|
{ "QCCOVRDEN", 9, 1 },
|
|
{ "QCCLOCK", 8, 1 },
|
|
{ "QCCSIGN", 6, 2 },
|
|
{ "QCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x33af8, 0 },
|
|
{ "TSTCMP", 15, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x33afc, 0 },
|
|
{ "CALMODEEDGE", 14, 1 },
|
|
{ "TESTCAP", 13, 1 },
|
|
{ "SNAPEN", 12, 1 },
|
|
{ "ASYNCDIR", 11, 1 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_CFG", 0x34800, 0 },
|
|
{ "MAC_Clk_Sel", 29, 3 },
|
|
{ "Ena_err_rsp", 28, 1 },
|
|
{ "SinkTx", 27, 1 },
|
|
{ "SinkTxOnLinkDown", 26, 1 },
|
|
{ "debug_clr", 25, 1 },
|
|
{ "LoopNoFwd", 24, 1 },
|
|
{ "pll_sel", 23, 1 },
|
|
{ "port_map", 20, 3 },
|
|
{ "Smux_Rx_Loop", 19, 1 },
|
|
{ "Rx_Lane_Swap", 18, 1 },
|
|
{ "Tx_Lane_Swap", 17, 1 },
|
|
{ "Aec_pat_data", 15, 1 },
|
|
{ "Signal_Det", 14, 1 },
|
|
{ "macclk_sel", 13, 1 },
|
|
{ "xgmii_sel", 12, 1 },
|
|
{ "debug_port_sel", 10, 2 },
|
|
{ "SmuxTxSel", 9, 1 },
|
|
{ "SmuxRxSel", 8, 1 },
|
|
{ "Enable_25G", 7, 1 },
|
|
{ "Enable_50G", 6, 1 },
|
|
{ "PortSpeed", 4, 2 },
|
|
{ "Rx_Byte_Swap", 3, 1 },
|
|
{ "Tx_Byte_Swap", 2, 1 },
|
|
{ "debug_tx_rx_sel", 1, 1 },
|
|
{ "Port_Sel", 0, 1 },
|
|
{ "MAC_PORT_RESET_CTRL", 0x34804, 0 },
|
|
{ "TWGDSK_HSSC16B", 31, 1 },
|
|
{ "EEE_RESET", 30, 1 },
|
|
{ "PTP_TIMER", 29, 1 },
|
|
{ "MtipRefReset", 28, 1 },
|
|
{ "MAC100G40G_RESET", 27, 1 },
|
|
{ "MAC10G1G_RESET", 26, 1 },
|
|
{ "MtipRegReset", 25, 1 },
|
|
{ "PCS1G_RESET", 24, 1 },
|
|
{ "AEC3Reset", 23, 1 },
|
|
{ "AEC2Reset", 22, 1 },
|
|
{ "AEC1Reset", 21, 1 },
|
|
{ "AEC0Reset", 20, 1 },
|
|
{ "AET3Reset", 19, 1 },
|
|
{ "AET2Reset", 18, 1 },
|
|
{ "AET1Reset", 17, 1 },
|
|
{ "AET0Reset", 16, 1 },
|
|
{ "PCS10G_RESET", 15, 1 },
|
|
{ "PCS40G_RESET", 14, 1 },
|
|
{ "PCS100G_RESET", 13, 1 },
|
|
{ "TXIF_Reset", 12, 1 },
|
|
{ "RXIF_Reset", 11, 1 },
|
|
{ "AuxExt_Reset", 10, 1 },
|
|
{ "MtipSd3TxRst", 9, 1 },
|
|
{ "MtipSd2TxRst", 8, 1 },
|
|
{ "MtipSd1TxRst", 7, 1 },
|
|
{ "MtipSd0TxRst", 6, 1 },
|
|
{ "MtipSd3RxRst", 5, 1 },
|
|
{ "MtipSd2RxRst", 4, 1 },
|
|
{ "MtipSd1RxRst", 3, 1 },
|
|
{ "WOL_Reset", 2, 1 },
|
|
{ "MtipSd0RxRst", 1, 1 },
|
|
{ "HSS_Reset", 0, 1 },
|
|
{ "MAC_PORT_LED_CFG", 0x34808, 0 },
|
|
{ "Led1_Cfg1", 14, 2 },
|
|
{ "Led0_Cfg1", 12, 2 },
|
|
{ "Led1_tlo", 11, 1 },
|
|
{ "Led1_thi", 10, 1 },
|
|
{ "Led0_tlo", 9, 1 },
|
|
{ "Led0_thi", 8, 1 },
|
|
{ "Led1_Cfg", 5, 3 },
|
|
{ "Led1_Polarity_Inv", 4, 1 },
|
|
{ "Led0_Cfg", 1, 3 },
|
|
{ "Led0_Polarity_Inv", 0, 1 },
|
|
{ "MAC_PORT_LED_COUNTHI", 0x3480c, 0 },
|
|
{ "MAC_PORT_LED_COUNTLO", 0x34810, 0 },
|
|
{ "MAC_PORT_CFG3", 0x34814, 0 },
|
|
{ "REF_Clk_Sel", 30, 2 },
|
|
{ "sgmii_sd_sig_det", 29, 1 },
|
|
{ "sgmii_sgpcs_ena", 28, 1 },
|
|
{ "FPGA_PTP_PORT", 26, 2 },
|
|
{ "FCSDisCtrl", 25, 1 },
|
|
{ "SigDetCtrl", 24, 1 },
|
|
{ "tx_lane", 23, 1 },
|
|
{ "rx_lane", 22, 1 },
|
|
{ "se_clr", 21, 1 },
|
|
{ "an_ena", 17, 4 },
|
|
{ "sd_rx_clk_ena", 13, 4 },
|
|
{ "sd_tx_clk_ena", 9, 4 },
|
|
{ "SGMIISEL", 8, 1 },
|
|
{ "HSSPLLSEL", 4, 4 },
|
|
{ "HSSC16C20SEL", 0, 4 },
|
|
{ "MAC_PORT_CFG2", 0x34818, 0 },
|
|
{ "Rx_Polarity_Inv", 28, 4 },
|
|
{ "Tx_Polarity_Inv", 24, 4 },
|
|
{ "InstanceNum", 22, 2 },
|
|
{ "StopOnPerr", 21, 1 },
|
|
{ "an_data_ctl", 19, 1 },
|
|
{ "PatEn", 18, 1 },
|
|
{ "MagicEn", 17, 1 },
|
|
{ "T5_AEC_PMA_TX_READY", 4, 4 },
|
|
{ "T5_AEC_PMA_RX_READY", 0, 4 },
|
|
{ "MAC_PORT_PKT_COUNT", 0x3481c, 0 },
|
|
{ "tx_sop_count", 24, 8 },
|
|
{ "tx_eop_count", 16, 8 },
|
|
{ "rx_sop_count", 8, 8 },
|
|
{ "rx_eop_count", 0, 8 },
|
|
{ "MAC_PORT_CFG4", 0x34820, 0 },
|
|
{ "AEC3_RX_WIDTH", 14, 2 },
|
|
{ "AEC2_RX_WIDTH", 12, 2 },
|
|
{ "AEC1_RX_WIDTH", 10, 2 },
|
|
{ "AEC0_RX_WIDTH", 8, 2 },
|
|
{ "AEC3_TX_WIDTH", 6, 2 },
|
|
{ "AEC2_TX_WIDTH", 4, 2 },
|
|
{ "AEC1_TX_WIDTH", 2, 2 },
|
|
{ "AEC0_TX_WIDTH", 0, 2 },
|
|
{ "MAC_PORT_MAGIC_MACID_LO", 0x34824, 0 },
|
|
{ "MAC_PORT_MAGIC_MACID_HI", 0x34828, 0 },
|
|
{ "MAC_PORT_MTIP_RESET_CTRL", 0x3482c, 0 },
|
|
{ "an_reset_sd_tx_clk", 31, 1 },
|
|
{ "an_reset_sd_rx_clk", 30, 1 },
|
|
{ "sgmii_reset_tx_clk", 29, 1 },
|
|
{ "sgmii_reset_rx_clk", 28, 1 },
|
|
{ "sgmii_reset_ref_clk", 27, 1 },
|
|
{ "pcs10g_reset_xfi_rxclk", 26, 1 },
|
|
{ "pcs10g_reset_xfi_txclk", 25, 1 },
|
|
{ "pcs10g_reset_sd_tx_clk", 24, 1 },
|
|
{ "pcs10g_reset_sd_rx_clk", 23, 1 },
|
|
{ "pcs40g_reset_rxclk", 22, 1 },
|
|
{ "pcs40g_reset_sd_tx_clk", 21, 1 },
|
|
{ "pcs40g_reset_sd0_rx_clk", 20, 1 },
|
|
{ "pcs40g_reset_sd1_rx_clk", 19, 1 },
|
|
{ "pcs40g_reset_sd2_rx_clk", 18, 1 },
|
|
{ "pcs40g_reset_sd3_rx_clk", 17, 1 },
|
|
{ "pcs100g_reset_cgmii_rxclk", 16, 1 },
|
|
{ "pcs100g_reset_cgmii_txclk", 15, 1 },
|
|
{ "pcs100g_reset_tx_clk", 14, 1 },
|
|
{ "pcs100g_reset_sd0_rx_clk", 13, 1 },
|
|
{ "pcs100g_reset_sd1_rx_clk", 12, 1 },
|
|
{ "pcs100g_reset_sd2_rx_clk", 11, 1 },
|
|
{ "pcs100g_reset_sd3_rx_clk", 10, 1 },
|
|
{ "mac40g100g_reset_txclk", 9, 1 },
|
|
{ "mac40g100g_reset_rxclk", 8, 1 },
|
|
{ "mac40g100g_reset_ff_tx_clk", 7, 1 },
|
|
{ "mac40g100g_reset_ff_rx_clk", 6, 1 },
|
|
{ "mac40g100g_reset_ts_clk", 5, 1 },
|
|
{ "mac1g10g_reset_rxclk", 4, 1 },
|
|
{ "mac1g10g_reset_txclk", 3, 1 },
|
|
{ "mac1g10g_reset_ff_rx_clk", 2, 1 },
|
|
{ "mac1g10g_reset_ff_tx_clk", 1, 1 },
|
|
{ "xgmii_clk_reset", 0, 1 },
|
|
{ "MAC_PORT_MTIP_GATE_CTRL", 0x34830, 0 },
|
|
{ "an_gate_sd_tx_clk", 31, 1 },
|
|
{ "an_gate_sd_rx_clk", 30, 1 },
|
|
{ "sgmii_gate_tx_clk", 29, 1 },
|
|
{ "sgmii_gate_rx_clk", 28, 1 },
|
|
{ "sgmii_gate_ref_clk", 27, 1 },
|
|
{ "pcs10g_gate_xfi_rxclk", 26, 1 },
|
|
{ "pcs10g_gate_xfi_txclk", 25, 1 },
|
|
{ "pcs10g_gate_sd_tx_clk", 24, 1 },
|
|
{ "pcs10g_gate_sd_rx_clk", 23, 1 },
|
|
{ "pcs40g_gate_rxclk", 22, 1 },
|
|
{ "pcs40g_gate_sd_tx_clk", 21, 1 },
|
|
{ "pcs40g_gate_sd_rx_clk", 20, 1 },
|
|
{ "pcs100g_gate_cgmii_rxclk", 19, 1 },
|
|
{ "pcs100g_gate_cgmii_txclk", 18, 1 },
|
|
{ "pcs100g_gate_tx_clk", 17, 1 },
|
|
{ "pcs100g_gate_sd_rx_clk", 16, 1 },
|
|
{ "mac40g100g_gate_txclk", 15, 1 },
|
|
{ "mac40g100g_gate_rxclk", 14, 1 },
|
|
{ "mac40g100g_gate_ff_tx_clk", 13, 1 },
|
|
{ "mac40g100g_gate_ff_rx_clk", 12, 1 },
|
|
{ "mac40g100g_ts_clk", 11, 1 },
|
|
{ "mac1g10g_gate_rxclk", 10, 1 },
|
|
{ "mac1g10g_gate_txclk", 9, 1 },
|
|
{ "mac1g10g_gate_ff_rx_clk", 8, 1 },
|
|
{ "mac1g10g_gate_ff_tx_clk", 7, 1 },
|
|
{ "aec_rx", 6, 1 },
|
|
{ "aec_tx", 5, 1 },
|
|
{ "pcs100g_clk_enable", 4, 1 },
|
|
{ "pcs40g_clk_enable", 3, 1 },
|
|
{ "pcs10g_clk_enable", 2, 1 },
|
|
{ "pcs1g_clk_enable", 1, 1 },
|
|
{ "an_clk_enable", 0, 1 },
|
|
{ "MAC_PORT_LINK_STATUS", 0x34834, 0 },
|
|
{ "hi_ber", 7, 1 },
|
|
{ "an_done", 6, 1 },
|
|
{ "align_done", 5, 1 },
|
|
{ "block_lock", 4, 1 },
|
|
{ "remflt", 3, 1 },
|
|
{ "locflt", 2, 1 },
|
|
{ "linkup", 1, 1 },
|
|
{ "linkdn", 0, 1 },
|
|
{ "MAC_PORT_AEC_ADD_CTL_STAT_0", 0x34838, 0 },
|
|
{ "AEC_SYS_LANE_TYPE_3", 11, 1 },
|
|
{ "AEC_SYS_LANE_TYPE_2", 10, 1 },
|
|
{ "AEC_SYS_LANE_TYPE_1", 9, 1 },
|
|
{ "AEC_SYS_LANE_TYPE_0", 8, 1 },
|
|
{ "AEC_SYS_LANE_SELECT_3", 6, 2 },
|
|
{ "AEC_SYS_LANE_SELECT_2", 4, 2 },
|
|
{ "AEC_SYS_LANE_SELECT_1", 2, 2 },
|
|
{ "AEC_SYS_LANE_SELECT_O", 0, 2 },
|
|
{ "MAC_PORT_AEC_ADD_CTL_STAT_1", 0x3483c, 0 },
|
|
{ "AEC_RX_UNKNOWN_LANE_3", 11, 1 },
|
|
{ "AEC_RX_UNKNOWN_LANE_2", 10, 1 },
|
|
{ "AEC_RX_UNKNOWN_LANE_1", 9, 1 },
|
|
{ "AEC_RX_UNKNOWN_LANE_0", 8, 1 },
|
|
{ "AEC_RX_LANE_ID_3", 6, 2 },
|
|
{ "AEC_RX_LANE_ID_2", 4, 2 },
|
|
{ "AEC_RX_LANE_ID_1", 2, 2 },
|
|
{ "AEC_RX_LANE_ID_O", 0, 2 },
|
|
{ "MAC_PORT_AEC_XGMII_TIMER_LO_40G", 0x34840, 0 },
|
|
{ "MAC_PORT_AEC_XGMII_TIMER_HI_40G", 0x34844, 0 },
|
|
{ "MAC_PORT_AEC_XGMII_TIMER_LO_100G", 0x34848, 0 },
|
|
{ "MAC_PORT_AEC_XGMII_TIMER_HI_100G", 0x3484c, 0 },
|
|
{ "MAC_PORT_AEC_DEBUG_LO_0", 0x34850, 0 },
|
|
{ "CTL_FSM_CUR_STATE", 28, 3 },
|
|
{ "CIN_FSM_CUR_STATE", 26, 2 },
|
|
{ "CRI_FSM_CUR_STATE", 23, 3 },
|
|
{ "CU_C3_ACK_VALUE", 21, 2 },
|
|
{ "CU_C2_ACK_VALUE", 19, 2 },
|
|
{ "CU_C1_ACK_VALUE", 17, 2 },
|
|
{ "CU_C0_ACK_VALUE", 15, 2 },
|
|
{ "CX_INIT", 13, 1 },
|
|
{ "CX_PRESET", 12, 1 },
|
|
{ "CUF_C3_UPDATE", 9, 2 },
|
|
{ "CUF_C2_UPDATE", 7, 2 },
|
|
{ "CUF_C1_UPDATE", 5, 2 },
|
|
{ "CUF_C0_UPDATE", 3, 2 },
|
|
{ "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
|
|
{ "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
|
|
{ "REG_MAN_DEC_REQ", 0, 1 },
|
|
{ "MAC_PORT_AEC_DEBUG_HI_0", 0x34854, 0 },
|
|
{ "FC_LSNA_", 12, 1 },
|
|
{ "CUF_C0_FSM_DEBUG", 9, 3 },
|
|
{ "CUF_C1_FSM_DEBUG", 6, 3 },
|
|
{ "CUF_C2_FSM_DEBUG", 3, 3 },
|
|
{ "LCK_FSM_CUR_STATE", 0, 3 },
|
|
{ "MAC_PORT_AEC_DEBUG_LO_1", 0x34858, 0 },
|
|
{ "CTL_FSM_CUR_STATE", 28, 3 },
|
|
{ "CIN_FSM_CUR_STATE", 26, 2 },
|
|
{ "CRI_FSM_CUR_STATE", 23, 3 },
|
|
{ "CU_C3_ACK_VALUE", 21, 2 },
|
|
{ "CU_C2_ACK_VALUE", 19, 2 },
|
|
{ "CU_C1_ACK_VALUE", 17, 2 },
|
|
{ "CU_C0_ACK_VALUE", 15, 2 },
|
|
{ "CX_INIT", 13, 1 },
|
|
{ "CX_PRESET", 12, 1 },
|
|
{ "CUF_C3_UPDATE", 9, 2 },
|
|
{ "CUF_C2_UPDATE", 7, 2 },
|
|
{ "CUF_C1_UPDATE", 5, 2 },
|
|
{ "CUF_C0_UPDATE", 3, 2 },
|
|
{ "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
|
|
{ "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
|
|
{ "REG_MAN_DEC_REQ", 0, 1 },
|
|
{ "MAC_PORT_AEC_DEBUG_HI_1", 0x3485c, 0 },
|
|
{ "FC_LSNA_", 12, 1 },
|
|
{ "CUF_C0_FSM_DEBUG", 9, 3 },
|
|
{ "CUF_C1_FSM_DEBUG", 6, 3 },
|
|
{ "CUF_C2_FSM_DEBUG", 3, 3 },
|
|
{ "LCK_FSM_CUR_STATE", 0, 3 },
|
|
{ "MAC_PORT_AEC_DEBUG_LO_2", 0x34860, 0 },
|
|
{ "CTL_FSM_CUR_STATE", 28, 3 },
|
|
{ "CIN_FSM_CUR_STATE", 26, 2 },
|
|
{ "CRI_FSM_CUR_STATE", 23, 3 },
|
|
{ "CU_C3_ACK_VALUE", 21, 2 },
|
|
{ "CU_C2_ACK_VALUE", 19, 2 },
|
|
{ "CU_C1_ACK_VALUE", 17, 2 },
|
|
{ "CU_C0_ACK_VALUE", 15, 2 },
|
|
{ "CX_INIT", 13, 1 },
|
|
{ "CX_PRESET", 12, 1 },
|
|
{ "CUF_C3_UPDATE", 9, 2 },
|
|
{ "CUF_C2_UPDATE", 7, 2 },
|
|
{ "CUF_C1_UPDATE", 5, 2 },
|
|
{ "CUF_C0_UPDATE", 3, 2 },
|
|
{ "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
|
|
{ "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
|
|
{ "REG_MAN_DEC_REQ", 0, 1 },
|
|
{ "MAC_PORT_AEC_DEBUG_HI_2", 0x34864, 0 },
|
|
{ "FC_LSNA_", 12, 1 },
|
|
{ "CUF_C0_FSM_DEBUG", 9, 3 },
|
|
{ "CUF_C1_FSM_DEBUG", 6, 3 },
|
|
{ "CUF_C2_FSM_DEBUG", 3, 3 },
|
|
{ "LCK_FSM_CUR_STATE", 0, 3 },
|
|
{ "MAC_PORT_AEC_DEBUG_LO_3", 0x34868, 0 },
|
|
{ "CTL_FSM_CUR_STATE", 28, 3 },
|
|
{ "CIN_FSM_CUR_STATE", 26, 2 },
|
|
{ "CRI_FSM_CUR_STATE", 23, 3 },
|
|
{ "CU_C3_ACK_VALUE", 21, 2 },
|
|
{ "CU_C2_ACK_VALUE", 19, 2 },
|
|
{ "CU_C1_ACK_VALUE", 17, 2 },
|
|
{ "CU_C0_ACK_VALUE", 15, 2 },
|
|
{ "CX_INIT", 13, 1 },
|
|
{ "CX_PRESET", 12, 1 },
|
|
{ "CUF_C3_UPDATE", 9, 2 },
|
|
{ "CUF_C2_UPDATE", 7, 2 },
|
|
{ "CUF_C1_UPDATE", 5, 2 },
|
|
{ "CUF_C0_UPDATE", 3, 2 },
|
|
{ "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
|
|
{ "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
|
|
{ "REG_MAN_DEC_REQ", 0, 1 },
|
|
{ "MAC_PORT_AEC_DEBUG_HI_3", 0x3486c, 0 },
|
|
{ "FC_LSNA_", 12, 1 },
|
|
{ "CUF_C0_FSM_DEBUG", 9, 3 },
|
|
{ "CUF_C1_FSM_DEBUG", 6, 3 },
|
|
{ "CUF_C2_FSM_DEBUG", 3, 3 },
|
|
{ "LCK_FSM_CUR_STATE", 0, 3 },
|
|
{ "MAC_PORT_MAC_DEBUG_RO", 0x34870, 0 },
|
|
{ "mac40g100g_tx_underflow", 13, 1 },
|
|
{ "mac1g10g_magic_ind", 12, 1 },
|
|
{ "mac1g10g_ff_rx_empty", 11, 1 },
|
|
{ "mac1g10g_ff_tx_ovr_err", 10, 1 },
|
|
{ "mac1g10g_if_mode_ena", 8, 2 },
|
|
{ "mac1g10g_mii_ena_10", 7, 1 },
|
|
{ "mac1g10g_pause_on", 6, 1 },
|
|
{ "mac1g10g_pfc_mode", 5, 1 },
|
|
{ "mac1g10g_rx_sfd_o", 4, 1 },
|
|
{ "mac1g10g_tx_empty", 3, 1 },
|
|
{ "mac1g10g_tx_sfd_o", 2, 1 },
|
|
{ "mac1g10g_tx_ts_frm_out", 1, 1 },
|
|
{ "mac1g10g_tx_underflow", 0, 1 },
|
|
{ "MAC_PORT_MAC_CTRL_RW", 0x34874, 0 },
|
|
{ "mac40g100g_ff_tx_pfc_xoff", 17, 8 },
|
|
{ "mac40g100g_tx_loc_fault", 16, 1 },
|
|
{ "mac40g100g_tx_rem_fault", 15, 1 },
|
|
{ "mac40g_loop_bck", 14, 1 },
|
|
{ "mac1g10g_magic_ena", 13, 1 },
|
|
{ "mac1g10g_if_mode_set", 11, 2 },
|
|
{ "mac1g10g_tx_loc_fault", 10, 1 },
|
|
{ "mac1g10g_tx_rem_fault", 9, 1 },
|
|
{ "mac1g10g_xoff_gen", 1, 8 },
|
|
{ "mac1g_loop_bck", 0, 1 },
|
|
{ "MAC_PORT_PCS_DEBUG0_RO", 0x34878, 0 },
|
|
{ "fpga_lock", 26, 4 },
|
|
{ "an_done", 25, 1 },
|
|
{ "an_int", 24, 1 },
|
|
{ "an_pcs_rx_clk_ena", 23, 1 },
|
|
{ "an_pcs_tx_clk_ena", 22, 1 },
|
|
{ "an_select", 17, 5 },
|
|
{ "an_prog", 16, 1 },
|
|
{ "pcs40g_block_lock", 12, 4 },
|
|
{ "pcs40g_ber_timer_done", 11, 1 },
|
|
{ "pcs10g_fec_locked", 10, 1 },
|
|
{ "pcs10g_block_lock", 9, 1 },
|
|
{ "sgmii_gmii_col", 8, 1 },
|
|
{ "sgmii_gmii_crs", 7, 1 },
|
|
{ "sgmii_sd_loopback", 6, 1 },
|
|
{ "sgmii_sg_an_done", 5, 1 },
|
|
{ "sgmii_sg_hd", 4, 1 },
|
|
{ "sgmii_sg_page_rx", 3, 1 },
|
|
{ "sgmii_sg_rx_sync", 2, 1 },
|
|
{ "sgmii_sg_speed", 0, 2 },
|
|
{ "MAC_PORT_PCS_CTRL_RW", 0x3487c, 0 },
|
|
{ "tx_li_fault", 31, 1 },
|
|
{ "pad", 30, 1 },
|
|
{ "blk_stb_val", 22, 8 },
|
|
{ "debug_sel", 18, 4 },
|
|
{ "sgmii_loop", 15, 3 },
|
|
{ "an_dis_timer", 14, 1 },
|
|
{ "pcs100g_ber_timer_short", 13, 1 },
|
|
{ "pcs100g_tx_lane_thresh", 9, 4 },
|
|
{ "pcs100g_vl_intvl", 8, 1 },
|
|
{ "sgmii_tx_lane_ckmult", 4, 3 },
|
|
{ "sgmii_tx_lane_thresh", 0, 4 },
|
|
{ "MAC_PORT_PCS_DEBUG1_RO", 0x34880, 0 },
|
|
{ "pcs100g_align_lock", 21, 1 },
|
|
{ "pcs100g_ber_timer_done", 20, 1 },
|
|
{ "pcs100g_block_lock", 0, 20 },
|
|
{ "MAC_PORT_PERR_INT_EN_100G", 0x34884, 0 },
|
|
{ "Perr_rx_fec100g_dly", 29, 1 },
|
|
{ "Perr_rx_fec100g", 28, 1 },
|
|
{ "Perr_rx3_fec100g_dk", 27, 1 },
|
|
{ "Perr_rx2_fec100g_dk", 26, 1 },
|
|
{ "Perr_rx1_fec100g_dk", 25, 1 },
|
|
{ "Perr_rx0_fec100g_dk", 24, 1 },
|
|
{ "Perr_tx3_pcs100g", 23, 1 },
|
|
{ "Perr_tx2_pcs100g", 22, 1 },
|
|
{ "Perr_tx1_pcs100g", 21, 1 },
|
|
{ "Perr_tx0_pcs100g", 20, 1 },
|
|
{ "Perr_rx19_pcs100g", 19, 1 },
|
|
{ "Perr_rx18_pcs100g", 18, 1 },
|
|
{ "Perr_rx17_pcs100g", 17, 1 },
|
|
{ "Perr_rx16_pcs100g", 16, 1 },
|
|
{ "Perr_rx15_pcs100g", 15, 1 },
|
|
{ "Perr_rx14_pcs100g", 14, 1 },
|
|
{ "Perr_rx13_pcs100g", 13, 1 },
|
|
{ "Perr_rx12_pcs100g", 12, 1 },
|
|
{ "Perr_rx11_pcs100g", 11, 1 },
|
|
{ "Perr_rx10_pcs100g", 10, 1 },
|
|
{ "Perr_rx9_pcs100g", 9, 1 },
|
|
{ "Perr_rx8_pcs100g", 8, 1 },
|
|
{ "Perr_rx7_pcs100g", 7, 1 },
|
|
{ "Perr_rx6_pcs100g", 6, 1 },
|
|
{ "Perr_rx5_pcs100g", 5, 1 },
|
|
{ "Perr_rx4_pcs100g", 4, 1 },
|
|
{ "Perr_rx3_pcs100g", 3, 1 },
|
|
{ "Perr_rx2_pcs100g", 2, 1 },
|
|
{ "Perr_rx1_pcs100g", 1, 1 },
|
|
{ "Perr_rx0_pcs100g", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_CAUSE_100G", 0x34888, 0 },
|
|
{ "Perr_rx_fec100g_dly", 29, 1 },
|
|
{ "Perr_rx_fec100g", 28, 1 },
|
|
{ "Perr_rx3_fec100g_dk", 27, 1 },
|
|
{ "Perr_rx2_fec100g_dk", 26, 1 },
|
|
{ "Perr_rx1_fec100g_dk", 25, 1 },
|
|
{ "Perr_rx0_fec100g_dk", 24, 1 },
|
|
{ "Perr_tx3_pcs100g", 23, 1 },
|
|
{ "Perr_tx2_pcs100g", 22, 1 },
|
|
{ "Perr_tx1_pcs100g", 21, 1 },
|
|
{ "Perr_tx0_pcs100g", 20, 1 },
|
|
{ "Perr_rx19_pcs100g", 19, 1 },
|
|
{ "Perr_rx18_pcs100g", 18, 1 },
|
|
{ "Perr_rx17_pcs100g", 17, 1 },
|
|
{ "Perr_rx16_pcs100g", 16, 1 },
|
|
{ "Perr_rx15_pcs100g", 15, 1 },
|
|
{ "Perr_rx14_pcs100g", 14, 1 },
|
|
{ "Perr_rx13_pcs100g", 13, 1 },
|
|
{ "Perr_rx12_pcs100g", 12, 1 },
|
|
{ "Perr_rx11_pcs100g", 11, 1 },
|
|
{ "Perr_rx10_pcs100g", 10, 1 },
|
|
{ "Perr_rx9_pcs100g", 9, 1 },
|
|
{ "Perr_rx8_pcs100g", 8, 1 },
|
|
{ "Perr_rx7_pcs100g", 7, 1 },
|
|
{ "Perr_rx6_pcs100g", 6, 1 },
|
|
{ "Perr_rx5_pcs100g", 5, 1 },
|
|
{ "Perr_rx4_pcs100g", 4, 1 },
|
|
{ "Perr_rx3_pcs100g", 3, 1 },
|
|
{ "Perr_rx2_pcs100g", 2, 1 },
|
|
{ "Perr_rx1_pcs100g", 1, 1 },
|
|
{ "Perr_rx0_pcs100g", 0, 1 },
|
|
{ "MAC_PORT_PERR_ENABLE_100G", 0x3488c, 0 },
|
|
{ "Perr_rx_fec100g_dly", 29, 1 },
|
|
{ "Perr_rx_fec100g", 28, 1 },
|
|
{ "Perr_rx3_fec100g_dk", 27, 1 },
|
|
{ "Perr_rx2_fec100g_dk", 26, 1 },
|
|
{ "Perr_rx1_fec100g_dk", 25, 1 },
|
|
{ "Perr_rx0_fec100g_dk", 24, 1 },
|
|
{ "Perr_tx3_pcs100g", 23, 1 },
|
|
{ "Perr_tx2_pcs100g", 22, 1 },
|
|
{ "Perr_tx1_pcs100g", 21, 1 },
|
|
{ "Perr_tx0_pcs100g", 20, 1 },
|
|
{ "Perr_rx19_pcs100g", 19, 1 },
|
|
{ "Perr_rx18_pcs100g", 18, 1 },
|
|
{ "Perr_rx17_pcs100g", 17, 1 },
|
|
{ "Perr_rx16_pcs100g", 16, 1 },
|
|
{ "Perr_rx15_pcs100g", 15, 1 },
|
|
{ "Perr_rx14_pcs100g", 14, 1 },
|
|
{ "Perr_rx13_pcs100g", 13, 1 },
|
|
{ "Perr_rx12_pcs100g", 12, 1 },
|
|
{ "Perr_rx11_pcs100g", 11, 1 },
|
|
{ "Perr_rx10_pcs100g", 10, 1 },
|
|
{ "Perr_rx9_pcs100g", 9, 1 },
|
|
{ "Perr_rx8_pcs100g", 8, 1 },
|
|
{ "Perr_rx7_pcs100g", 7, 1 },
|
|
{ "Perr_rx6_pcs100g", 6, 1 },
|
|
{ "Perr_rx5_pcs100g", 5, 1 },
|
|
{ "Perr_rx4_pcs100g", 4, 1 },
|
|
{ "Perr_rx3_pcs100g", 3, 1 },
|
|
{ "Perr_rx2_pcs100g", 2, 1 },
|
|
{ "Perr_rx1_pcs100g", 1, 1 },
|
|
{ "Perr_rx0_pcs100g", 0, 1 },
|
|
{ "MAC_PORT_MAC_STAT_DEBUG", 0x34890, 0 },
|
|
{ "MAC_PORT_MAC_25G_50G_AM0", 0x34894, 0 },
|
|
{ "MAC_PORT_MAC_25G_50G_AM1", 0x34898, 0 },
|
|
{ "MAC_PORT_MAC_25G_50G_AM2", 0x3489c, 0 },
|
|
{ "MAC_PORT_MAC_25G_50G_AM3", 0x348a0, 0 },
|
|
{ "MAC_PORT_MAC_AN_STATE_STATUS", 0x348a4, 0 },
|
|
{ "MAC_PORT_EPIO_DATA0", 0x348c0, 0 },
|
|
{ "MAC_PORT_EPIO_DATA1", 0x348c4, 0 },
|
|
{ "MAC_PORT_EPIO_DATA2", 0x348c8, 0 },
|
|
{ "MAC_PORT_EPIO_DATA3", 0x348cc, 0 },
|
|
{ "MAC_PORT_EPIO_OP", 0x348d0, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Write", 8, 1 },
|
|
{ "Address", 0, 8 },
|
|
{ "MAC_PORT_WOL_STATUS", 0x348d4, 0 },
|
|
{ "MagicDetected", 31, 1 },
|
|
{ "PatDetected", 30, 1 },
|
|
{ "ClearMagic", 4, 1 },
|
|
{ "ClearMatch", 3, 1 },
|
|
{ "MatchedFilter", 0, 3 },
|
|
{ "MAC_PORT_INT_EN", 0x348d8, 0 },
|
|
{ "pps", 30, 1 },
|
|
{ "tx_ts_avail", 29, 1 },
|
|
{ "single_alarm", 28, 1 },
|
|
{ "periodic_alarm", 27, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "an_page_rcvd", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "MAC_PORT_INT_CAUSE", 0x348dc, 0 },
|
|
{ "pps", 30, 1 },
|
|
{ "tx_ts_avail", 29, 1 },
|
|
{ "single_alarm", 28, 1 },
|
|
{ "periodic_alarm", 27, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "an_page_rcvd", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_EN", 0x348e0, 0 },
|
|
{ "Perr_pkt_ram", 31, 1 },
|
|
{ "Perr_mask_ram", 30, 1 },
|
|
{ "Perr_crc_ram", 29, 1 },
|
|
{ "rx_mac40g", 28, 1 },
|
|
{ "tx_mac40g", 27, 1 },
|
|
{ "rx_st_mac40g", 26, 1 },
|
|
{ "tx_st_mac40g", 25, 1 },
|
|
{ "tx_mac1g10g", 24, 1 },
|
|
{ "rx_mac1g10g", 23, 1 },
|
|
{ "rx_status_mac1g10g", 22, 1 },
|
|
{ "rx_st_mac1g10g", 21, 1 },
|
|
{ "tx_st_mac1g10g", 20, 1 },
|
|
{ "Perr_tx0_pcs40g", 19, 1 },
|
|
{ "Perr_tx1_pcs40g", 18, 1 },
|
|
{ "Perr_tx2_pcs40g", 17, 1 },
|
|
{ "Perr_tx3_pcs40g", 16, 1 },
|
|
{ "Perr_tx0_fec40g", 15, 1 },
|
|
{ "Perr_tx1_fec40g", 14, 1 },
|
|
{ "Perr_tx2_fec40g", 13, 1 },
|
|
{ "Perr_tx3_fec40g", 12, 1 },
|
|
{ "Perr_rx0_pcs40g", 11, 1 },
|
|
{ "Perr_rx1_pcs40g", 10, 1 },
|
|
{ "Perr_rx2_pcs40g", 9, 1 },
|
|
{ "Perr_rx3_pcs40g", 8, 1 },
|
|
{ "Perr_rx0_fec40g", 7, 1 },
|
|
{ "Perr_rx1_fec40g", 6, 1 },
|
|
{ "Perr_rx2_fec40g", 5, 1 },
|
|
{ "Perr_rx3_fec40g", 4, 1 },
|
|
{ "Perr_rx_pcs10g_lpbk", 3, 1 },
|
|
{ "Perr_rx_pcs10g", 2, 1 },
|
|
{ "Perr_rx_pcs1g", 1, 1 },
|
|
{ "Perr_tx_pcs1g", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_CAUSE", 0x348e4, 0 },
|
|
{ "Perr_pkt_ram", 31, 1 },
|
|
{ "Perr_mask_ram", 30, 1 },
|
|
{ "Perr_crc_ram", 29, 1 },
|
|
{ "rx_mac40g", 28, 1 },
|
|
{ "tx_mac40g", 27, 1 },
|
|
{ "rx_st_mac40g", 26, 1 },
|
|
{ "tx_st_mac40g", 25, 1 },
|
|
{ "tx_mac1g10g", 24, 1 },
|
|
{ "rx_mac1g10g", 23, 1 },
|
|
{ "rx_status_mac1g10g", 22, 1 },
|
|
{ "rx_st_mac1g10g", 21, 1 },
|
|
{ "tx_st_mac1g10g", 20, 1 },
|
|
{ "Perr_tx0_pcs40g", 19, 1 },
|
|
{ "Perr_tx1_pcs40g", 18, 1 },
|
|
{ "Perr_tx2_pcs40g", 17, 1 },
|
|
{ "Perr_tx3_pcs40g", 16, 1 },
|
|
{ "Perr_tx0_fec40g", 15, 1 },
|
|
{ "Perr_tx1_fec40g", 14, 1 },
|
|
{ "Perr_tx2_fec40g", 13, 1 },
|
|
{ "Perr_tx3_fec40g", 12, 1 },
|
|
{ "Perr_rx0_pcs40g", 11, 1 },
|
|
{ "Perr_rx1_pcs40g", 10, 1 },
|
|
{ "Perr_rx2_pcs40g", 9, 1 },
|
|
{ "Perr_rx3_pcs40g", 8, 1 },
|
|
{ "Perr_rx0_fec40g", 7, 1 },
|
|
{ "Perr_rx1_fec40g", 6, 1 },
|
|
{ "Perr_rx2_fec40g", 5, 1 },
|
|
{ "Perr_rx3_fec40g", 4, 1 },
|
|
{ "Perr_rx_pcs10g_lpbk", 3, 1 },
|
|
{ "Perr_rx_pcs10g", 2, 1 },
|
|
{ "Perr_rx_pcs1g", 1, 1 },
|
|
{ "Perr_tx_pcs1g", 0, 1 },
|
|
{ "MAC_PORT_PERR_ENABLE", 0x348e8, 0 },
|
|
{ "Perr_pkt_ram", 31, 1 },
|
|
{ "Perr_mask_ram", 30, 1 },
|
|
{ "Perr_crc_ram", 29, 1 },
|
|
{ "rx_mac40g", 28, 1 },
|
|
{ "tx_mac40g", 27, 1 },
|
|
{ "rx_st_mac40g", 26, 1 },
|
|
{ "tx_st_mac40g", 25, 1 },
|
|
{ "tx_mac1g10g", 24, 1 },
|
|
{ "rx_mac1g10g", 23, 1 },
|
|
{ "rx_status_mac1g10g", 22, 1 },
|
|
{ "rx_st_mac1g10g", 21, 1 },
|
|
{ "tx_st_mac1g10g", 20, 1 },
|
|
{ "Perr_tx0_pcs40g", 19, 1 },
|
|
{ "Perr_tx1_pcs40g", 18, 1 },
|
|
{ "Perr_tx2_pcs40g", 17, 1 },
|
|
{ "Perr_tx3_pcs40g", 16, 1 },
|
|
{ "Perr_tx0_fec40g", 15, 1 },
|
|
{ "Perr_tx1_fec40g", 14, 1 },
|
|
{ "Perr_tx2_fec40g", 13, 1 },
|
|
{ "Perr_tx3_fec40g", 12, 1 },
|
|
{ "Perr_rx0_pcs40g", 11, 1 },
|
|
{ "Perr_rx1_pcs40g", 10, 1 },
|
|
{ "Perr_rx2_pcs40g", 9, 1 },
|
|
{ "Perr_rx3_pcs40g", 8, 1 },
|
|
{ "Perr_rx0_fec40g", 7, 1 },
|
|
{ "Perr_rx1_fec40g", 6, 1 },
|
|
{ "Perr_rx2_fec40g", 5, 1 },
|
|
{ "Perr_rx3_fec40g", 4, 1 },
|
|
{ "Perr_rx_pcs10g_lpbk", 3, 1 },
|
|
{ "Perr_rx_pcs10g", 2, 1 },
|
|
{ "Perr_rx_pcs1g", 1, 1 },
|
|
{ "Perr_tx_pcs1g", 0, 1 },
|
|
{ "MAC_PORT_PERR_INJECT", 0x348ec, 0 },
|
|
{ "MemSel", 1, 6 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG0", 0x348f0, 0 },
|
|
{ "TXDTS", 31, 1 },
|
|
{ "TXCTS", 30, 1 },
|
|
{ "TXBTS", 29, 1 },
|
|
{ "TXATS", 28, 1 },
|
|
{ "TXDOBS", 27, 1 },
|
|
{ "TXCOBS", 26, 1 },
|
|
{ "TXBOBS", 25, 1 },
|
|
{ "TXAOBS", 24, 1 },
|
|
{ "HSSREFCLKVALIDA", 20, 1 },
|
|
{ "HSSREFCLKVALIDB", 19, 1 },
|
|
{ "HSSRESYNCA", 18, 1 },
|
|
{ "HSSAVDHI", 17, 1 },
|
|
{ "HSSRESYNCB", 16, 1 },
|
|
{ "HSSRECCALA", 15, 1 },
|
|
{ "HSSRXACMODE", 14, 1 },
|
|
{ "HSSRECCALB", 13, 1 },
|
|
{ "HSSPLLBYPA", 12, 1 },
|
|
{ "HSSPLLBYPB", 11, 1 },
|
|
{ "HSSPDWNPLLA", 10, 1 },
|
|
{ "HSSPDWNPLLB", 9, 1 },
|
|
{ "HSSVCOSELA", 8, 1 },
|
|
{ "HSSVCOSELB", 7, 1 },
|
|
{ "HSSCALCOMP", 6, 1 },
|
|
{ "HSSCALENAB", 5, 1 },
|
|
{ "HSSEXTC16SEL", 4, 1 },
|
|
{ "MAC_PORT_HSS_CFG1", 0x348f4, 0 },
|
|
{ "RXACONFIGSEL", 30, 2 },
|
|
{ "RXAQUIET", 29, 1 },
|
|
{ "RXAREFRESH", 28, 1 },
|
|
{ "RXBCONFIGSEL", 26, 2 },
|
|
{ "RXBQUIET", 25, 1 },
|
|
{ "RXBREFRESH", 24, 1 },
|
|
{ "RXCCONFIGSEL", 22, 2 },
|
|
{ "RXCQUIET", 21, 1 },
|
|
{ "RXCREFRESH", 20, 1 },
|
|
{ "RXDCONFIGSEL", 18, 2 },
|
|
{ "RXDQUIET", 17, 1 },
|
|
{ "RXDREFRESH", 16, 1 },
|
|
{ "TXACONFIGSEL", 14, 2 },
|
|
{ "TXAQUIET", 13, 1 },
|
|
{ "TXAREFRESH", 12, 1 },
|
|
{ "TXBCONFIGSEL", 10, 2 },
|
|
{ "TXBQUIET", 9, 1 },
|
|
{ "TXBREFRESH", 8, 1 },
|
|
{ "TXCCONFIGSEL", 6, 2 },
|
|
{ "TXCQUIET", 5, 1 },
|
|
{ "TXCREFRESH", 4, 1 },
|
|
{ "TXDCONFIGSEL", 2, 2 },
|
|
{ "TXDQUIET", 1, 1 },
|
|
{ "TXDREFRESH", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG2", 0x348f8, 0 },
|
|
{ "RXAASSTCLK", 31, 1 },
|
|
{ "T5RXAPRBSRST", 30, 1 },
|
|
{ "RXBASSTCLK", 29, 1 },
|
|
{ "T5RXBPRBSRST", 28, 1 },
|
|
{ "RXCASSTCLK", 27, 1 },
|
|
{ "T5RXCPRBSRST", 26, 1 },
|
|
{ "RXDASSTCLK", 25, 1 },
|
|
{ "T5RXDPRBSRST", 24, 1 },
|
|
{ "RXDDATASYNC", 23, 1 },
|
|
{ "RXCDATASYNC", 22, 1 },
|
|
{ "RXBDATASYNC", 21, 1 },
|
|
{ "RXADATASYNC", 20, 1 },
|
|
{ "RXDEARLYIN", 19, 1 },
|
|
{ "RXDLATEIN", 18, 1 },
|
|
{ "RXDPHSLOCK", 17, 1 },
|
|
{ "RXDPHSDNIN", 16, 1 },
|
|
{ "RXDPHSUPIN", 15, 1 },
|
|
{ "RXCEARLYIN", 14, 1 },
|
|
{ "RXCLATEIN", 13, 1 },
|
|
{ "RXCPHSLOCK", 12, 1 },
|
|
{ "RXCPHSDNIN", 11, 1 },
|
|
{ "RXCPHSUPIN", 10, 1 },
|
|
{ "RXBEARLYIN", 9, 1 },
|
|
{ "RXBLATEIN", 8, 1 },
|
|
{ "RXBPHSLOCK", 7, 1 },
|
|
{ "RXBPHSDNIN", 6, 1 },
|
|
{ "RXBPHSUPIN", 5, 1 },
|
|
{ "RXAEARLYIN", 4, 1 },
|
|
{ "RXALATEIN", 3, 1 },
|
|
{ "RXAPHSLOCK", 2, 1 },
|
|
{ "RXAPHSDNIN", 1, 1 },
|
|
{ "RXAPHSUPIN", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG3", 0x348fc, 0 },
|
|
{ "HSSCALSSTN", 22, 6 },
|
|
{ "HSSCALSSTP", 16, 6 },
|
|
{ "HSSPLLCONFIGB", 8, 8 },
|
|
{ "HSSPLLCONFIGA", 0, 8 },
|
|
{ "MAC_PORT_HSS_CFG4", 0x34900, 0 },
|
|
{ "HSSREFDIVA", 24, 4 },
|
|
{ "HSSREFDIVB", 20, 4 },
|
|
{ "HSSPLLDIV2B", 19, 1 },
|
|
{ "HSSPLLDIV2A", 18, 1 },
|
|
{ "HSSDIVSELA", 9, 9 },
|
|
{ "HSSDIVSELB", 0, 9 },
|
|
{ "MAC_PORT_HSS_STATUS", 0x34904, 0 },
|
|
{ "RXDERROFLOW", 19, 1 },
|
|
{ "RXCERROFLOW", 18, 1 },
|
|
{ "RXBERROFLOW", 17, 1 },
|
|
{ "RXAERROFLOW", 16, 1 },
|
|
{ "RXDPRBSSYNC", 15, 1 },
|
|
{ "RXCPRBSSYNC", 14, 1 },
|
|
{ "RXBPRBSSYNC", 13, 1 },
|
|
{ "RXAPRBSSYNC", 12, 1 },
|
|
{ "RXDPRBSERR", 11, 1 },
|
|
{ "RXCPRBSERR", 10, 1 },
|
|
{ "RXBPRBSERR", 9, 1 },
|
|
{ "RXAPRBSERR", 8, 1 },
|
|
{ "RXDSIGDET", 7, 1 },
|
|
{ "RXCSIGDET", 6, 1 },
|
|
{ "RXBSIGDET", 5, 1 },
|
|
{ "RXASIGDET", 4, 1 },
|
|
{ "HSSPLLLOCKB", 3, 1 },
|
|
{ "HSSPLLLOCKA", 2, 1 },
|
|
{ "HSSPRTREADYB", 1, 1 },
|
|
{ "HSSPRTREADYA", 0, 1 },
|
|
{ "MAC_PORT_HSS_EEE_STATUS", 0x34908, 0 },
|
|
{ "RXAQUIET_STATUS", 15, 1 },
|
|
{ "RXAREFRESH_STATUS", 14, 1 },
|
|
{ "RXBQUIET_STATUS", 13, 1 },
|
|
{ "RXBREFRESH_STATUS", 12, 1 },
|
|
{ "RXCQUIET_STATUS", 11, 1 },
|
|
{ "RXCREFRESH_STATUS", 10, 1 },
|
|
{ "RXDQUIET_STATUS", 9, 1 },
|
|
{ "RXDREFRESH_STATUS", 8, 1 },
|
|
{ "TXAQUIET_STATUS", 7, 1 },
|
|
{ "TXAREFRESH_STATUS", 6, 1 },
|
|
{ "TXBQUIET_STATUS", 5, 1 },
|
|
{ "TXBREFRESH_STATUS", 4, 1 },
|
|
{ "TXCQUIET_STATUS", 3, 1 },
|
|
{ "TXCREFRESH_STATUS", 2, 1 },
|
|
{ "TXDQUIET_STATUS", 1, 1 },
|
|
{ "TXDREFRESH_STATUS", 0, 1 },
|
|
{ "MAC_PORT_HSS_SIGDET_STATUS", 0x3490c, 0 },
|
|
{ "MAC_PORT_HSS_PL_CTL", 0x34910, 0 },
|
|
{ "TOV", 16, 8 },
|
|
{ "TSU", 8, 8 },
|
|
{ "IPW", 0, 8 },
|
|
{ "MAC_PORT_RUNT_FRAME", 0x34914, 0 },
|
|
{ "runtclear", 16, 1 },
|
|
{ "runt", 0, 16 },
|
|
{ "MAC_PORT_EEE_STATUS", 0x34918, 0 },
|
|
{ "eee_tx_10g_state", 10, 2 },
|
|
{ "eee_rx_10g_state", 8, 2 },
|
|
{ "eee_tx_1g_state", 6, 2 },
|
|
{ "eee_rx_1g_state", 4, 2 },
|
|
{ "pma_rx_refresh", 3, 1 },
|
|
{ "pma_rx_quiet", 2, 1 },
|
|
{ "pma_tx_refresh", 1, 1 },
|
|
{ "pma_tx_quiet", 0, 1 },
|
|
{ "MAC_PORT_CGEN", 0x3491c, 0 },
|
|
{ "CGEN", 8, 1 },
|
|
{ "sd7_CGEN", 7, 1 },
|
|
{ "sd6_CGEN", 6, 1 },
|
|
{ "sd5_CGEN", 5, 1 },
|
|
{ "sd4_CGEN", 4, 1 },
|
|
{ "sd3_CGEN", 3, 1 },
|
|
{ "sd2_CGEN", 2, 1 },
|
|
{ "sd1_CGEN", 1, 1 },
|
|
{ "sd0_CGEN", 0, 1 },
|
|
{ "MAC_PORT_CGEN_MTIP", 0x34920, 0 },
|
|
{ "MACSEG5_CGEN", 11, 1 },
|
|
{ "PCSSEG5_CGEN", 10, 1 },
|
|
{ "MACSEG4_CGEN", 9, 1 },
|
|
{ "PCSSEG4_CGEN", 8, 1 },
|
|
{ "MACSEG3_CGEN", 7, 1 },
|
|
{ "PCSSEG3_CGEN", 6, 1 },
|
|
{ "MACSEG2_CGEN", 5, 1 },
|
|
{ "PCSSEG2_CGEN", 4, 1 },
|
|
{ "MACSEG1_CGEN", 3, 1 },
|
|
{ "PCSSEG1_CGEN", 2, 1 },
|
|
{ "MACSEG0_CGEN", 1, 1 },
|
|
{ "PCSSEG0_CGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_TS_ID", 0x34924, 0 },
|
|
{ "MAC_PORT_TX_TS_VAL_LO", 0x34928, 0 },
|
|
{ "MAC_PORT_TX_TS_VAL_HI", 0x3492c, 0 },
|
|
{ "MAC_PORT_EEE_CTL", 0x34930, 0 },
|
|
{ "EEE_CTRL", 2, 30 },
|
|
{ "TICK_START", 1, 1 },
|
|
{ "En", 0, 1 },
|
|
{ "MAC_PORT_EEE_TX_CTL", 0x34934, 0 },
|
|
{ "WAKE_TIMER", 16, 16 },
|
|
{ "HSS_TIMER", 5, 4 },
|
|
{ "HSS_CTL", 4, 1 },
|
|
{ "LPI_ACTIVE", 3, 1 },
|
|
{ "LPI_TXHOLD", 2, 1 },
|
|
{ "LPI_REQ", 1, 1 },
|
|
{ "EEE_TX_RESET", 0, 1 },
|
|
{ "MAC_PORT_EEE_RX_CTL", 0x34938, 0 },
|
|
{ "WAKE_TIMER", 16, 16 },
|
|
{ "HSS_TIMER", 5, 4 },
|
|
{ "HSS_CTL", 4, 1 },
|
|
{ "LPI_IND", 1, 1 },
|
|
{ "EEE_RX_RESET", 0, 1 },
|
|
{ "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3493c, 0 },
|
|
{ "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x34940, 0 },
|
|
{ "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x34944, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x34948, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3494c, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x34950, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x34954, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x34958, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3495c, 0 },
|
|
{ "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x34960, 0 },
|
|
{ "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x34964, 0 },
|
|
{ "MAC_PORT_EEE_WF_COUNT", 0x34968, 0 },
|
|
{ "wake_cnt_clr", 16, 1 },
|
|
{ "wake_cnt", 0, 16 },
|
|
{ "MAC_PORT_PTP_TIMER_RD0_LO", 0x3496c, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD0_HI", 0x34970, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD1_LO", 0x34974, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD1_HI", 0x34978, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_WR_LO", 0x3497c, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_WR_HI", 0x34980, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_0", 0x34984, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_1", 0x34988, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3498c, 0 },
|
|
{ "MAC_PORT_PTP_SUM_LO", 0x34990, 0 },
|
|
{ "MAC_PORT_PTP_SUM_HI", 0x34994, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_INCR0", 0x34998, 0 },
|
|
{ "Y", 16, 16 },
|
|
{ "X", 0, 16 },
|
|
{ "MAC_PORT_PTP_TIMER_INCR1", 0x3499c, 0 },
|
|
{ "Y_TICK", 16, 16 },
|
|
{ "X_TICK", 0, 16 },
|
|
{ "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x349a0, 0 },
|
|
{ "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x349a4, 0 },
|
|
{ "B", 16, 16 },
|
|
{ "A", 0, 16 },
|
|
{ "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x349a8, 0 },
|
|
{ "MAC_PORT_PTP_CFG", 0x349ac, 0 },
|
|
{ "ALARM_EN", 21, 1 },
|
|
{ "ALARM_START", 20, 1 },
|
|
{ "PPS_EN", 19, 1 },
|
|
{ "FRZ", 18, 1 },
|
|
{ "OFFSER_ADJUST_SIGN", 17, 1 },
|
|
{ "ADD_OFFSET", 16, 1 },
|
|
{ "CYCLE1", 8, 8 },
|
|
{ "Q", 0, 8 },
|
|
{ "MAC_PORT_PTP_PPS", 0x349b0, 0 },
|
|
{ "MAC_PORT_PTP_SINGLE_ALARM", 0x349b4, 0 },
|
|
{ "MAC_PORT_PTP_PERIODIC_ALARM", 0x349b8, 0 },
|
|
{ "MAC_PORT_PTP_STATUS", 0x349bc, 0 },
|
|
{ "MAC_PORT_MTIP_REVISION", 0x34a00, 0 },
|
|
{ "CUSTREV", 16, 16 },
|
|
{ "VER", 8, 8 },
|
|
{ "REV", 0, 8 },
|
|
{ "MAC_PORT_MTIP_SCRATCH", 0x34a04, 0 },
|
|
{ "MAC_PORT_MTIP_COMMAND_CONFIG", 0x34a08, 0 },
|
|
{ "TX_FLUSH", 22, 1 },
|
|
{ "RX_SFD_ANY", 21, 1 },
|
|
{ "PAUSE_PFC_COMP", 20, 1 },
|
|
{ "PFC_MODE", 19, 1 },
|
|
{ "RS_COL_CNT_EXT", 18, 1 },
|
|
{ "NO_LGTH_CHECK", 17, 1 },
|
|
{ "SEND_IDLE", 16, 1 },
|
|
{ "PHY_TXENA", 15, 1 },
|
|
{ "RX_ERR_DISC", 14, 1 },
|
|
{ "CMD_FRAME_ENA", 13, 1 },
|
|
{ "SW_RESET", 12, 1 },
|
|
{ "TX_PAD_EN", 11, 1 },
|
|
{ "LOOPBACK_EN", 10, 1 },
|
|
{ "TX_ADDR_INS", 9, 1 },
|
|
{ "PAUSE_IGNORE", 8, 1 },
|
|
{ "PAUSE_FWD", 7, 1 },
|
|
{ "CRC_FWD", 6, 1 },
|
|
{ "PAD_EN", 5, 1 },
|
|
{ "PROMIS_EN", 4, 1 },
|
|
{ "WAN_MODE", 3, 1 },
|
|
{ "RX_ENA", 1, 1 },
|
|
{ "TX_ENA", 0, 1 },
|
|
{ "MAC_PORT_MTIP_MAC_ADDR_0", 0x34a0c, 0 },
|
|
{ "MAC_PORT_MTIP_MAC_ADDR_1", 0x34a10, 0 },
|
|
{ "MAC_PORT_MTIP_FRM_LENGTH", 0x34a14, 0 },
|
|
{ "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x34a1c, 0 },
|
|
{ "AVAIL", 16, 16 },
|
|
{ "EMPTY", 0, 16 },
|
|
{ "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x34a20, 0 },
|
|
{ "AVAIL", 16, 16 },
|
|
{ "EMPTY", 0, 16 },
|
|
{ "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x34a24, 0 },
|
|
{ "AlmstFull", 16, 16 },
|
|
{ "AlmstEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x34a28, 0 },
|
|
{ "AlmstFull", 16, 16 },
|
|
{ "AlmstEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x34a2c, 0 },
|
|
{ "ENABLE", 8, 1 },
|
|
{ "ADDR", 0, 6 },
|
|
{ "MAC_PORT_MTIP_MAC_STATUS", 0x34a40, 0 },
|
|
{ "TS_AVAIL", 3, 1 },
|
|
{ "PHY_LOS", 2, 1 },
|
|
{ "RX_REM_FAULT", 1, 1 },
|
|
{ "RX_LOC_FAULT", 0, 1 },
|
|
{ "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x34a44, 0 },
|
|
{ "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x34a48, 0 },
|
|
{ "MAC_PORT_MTIP_INIT_CREDIT", 0x34a4c, 0 },
|
|
{ "MAC_PORT_MTIP_CURRENT_CREDIT", 0x34a50, 0 },
|
|
{ "MAC_PORT_RX_PAUSE_STATUS", 0x34a74, 0 },
|
|
{ "MAC_PORT_MTIP_TS_TIMESTAMP", 0x34a7c, 0 },
|
|
{ "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x34a80, 0 },
|
|
{ "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x34a84, 0 },
|
|
{ "MAC_PORT_AFRAMESRECEIVEDOK", 0x34a88, 0 },
|
|
{ "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x34a8c, 0 },
|
|
{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x34a90, 0 },
|
|
{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x34a94, 0 },
|
|
{ "MAC_PORT_AALIGNMENTERRORS", 0x34a98, 0 },
|
|
{ "MAC_PORT_AALIGNMENTERRORSHI", 0x34a9c, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x34aa0, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x34aa4, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x34aa8, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x34aac, 0 },
|
|
{ "MAC_PORT_AFRAMETOOLONGERRORS", 0x34ab0, 0 },
|
|
{ "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x34ab4, 0 },
|
|
{ "MAC_PORT_AINRANGELENGTHERRORS", 0x34ab8, 0 },
|
|
{ "MAC_PORT_AINRANGELENGTHERRORSHI", 0x34abc, 0 },
|
|
{ "MAC_PORT_VLANTRANSMITTEDOK", 0x34ac0, 0 },
|
|
{ "MAC_PORT_VLANTRANSMITTEDOKHI", 0x34ac4, 0 },
|
|
{ "MAC_PORT_VLANRECEIVEDOK", 0x34ac8, 0 },
|
|
{ "MAC_PORT_VLANRECEIVEDOKHI", 0x34acc, 0 },
|
|
{ "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x34ad0, 0 },
|
|
{ "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x34ad4, 0 },
|
|
{ "MAC_PORT_AOCTETSRECEIVEDOK", 0x34ad8, 0 },
|
|
{ "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x34adc, 0 },
|
|
{ "MAC_PORT_IFINUCASTPKTS", 0x34ae0, 0 },
|
|
{ "MAC_PORT_IFINUCASTPKTSHI", 0x34ae4, 0 },
|
|
{ "MAC_PORT_IFINMULTICASTPKTS", 0x34ae8, 0 },
|
|
{ "MAC_PORT_IFINMULTICASTPKTSHI", 0x34aec, 0 },
|
|
{ "MAC_PORT_IFINBROADCASTPKTS", 0x34af0, 0 },
|
|
{ "MAC_PORT_IFINBROADCASTPKTSHI", 0x34af4, 0 },
|
|
{ "MAC_PORT_IFOUTERRORS", 0x34af8, 0 },
|
|
{ "MAC_PORT_IFOUTERRORSHI", 0x34afc, 0 },
|
|
{ "MAC_PORT_IFOUTUCASTPKTS", 0x34b08, 0 },
|
|
{ "MAC_PORT_IFOUTUCASTPKTSHI", 0x34b0c, 0 },
|
|
{ "MAC_PORT_IFOUTMULTICASTPKTS", 0x34b10, 0 },
|
|
{ "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x34b14, 0 },
|
|
{ "MAC_PORT_IFOUTBROADCASTPKTS", 0x34b18, 0 },
|
|
{ "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x34b1c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSDROPEVENTS", 0x34b20, 0 },
|
|
{ "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x34b24, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOCTETS", 0x34b28, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOCTETSHI", 0x34b2c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS", 0x34b30, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTSHI", 0x34b34, 0 },
|
|
{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x34b38, 0 },
|
|
{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x34b3c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x34b40, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x34b44, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x34b48, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x34b4c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x34b50, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x34b54, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x34b58, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x34b5c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x34b60, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x34b64, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x34b68, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x34b6c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x34b70, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x34b74, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x34b78, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x34b7c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSJABBERS", 0x34b80, 0 },
|
|
{ "MAC_PORT_ETHERSTATSJABBERSHI", 0x34b84, 0 },
|
|
{ "MAC_PORT_ETHERSTATSFRAGMENTS", 0x34b88, 0 },
|
|
{ "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x34b8c, 0 },
|
|
{ "MAC_PORT_IFINERRORS", 0x34b90, 0 },
|
|
{ "MAC_PORT_IFINERRORSHI", 0x34b94, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x34b98, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x34b9c, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x34ba0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x34ba4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x34ba8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x34bac, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x34bb0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x34bb4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x34bb8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x34bbc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x34bc0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x34bc4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x34bc8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x34bcc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x34bd0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x34bd4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x34bd8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x34bdc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x34be0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x34be4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x34be8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x34bec, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x34bf0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x34bf4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x34bf8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x34bfc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x34c00, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x34c04, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x34c08, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x34c0c, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x34c10, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x34c14, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x34c18, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x34c1c, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x34c20, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x34c24, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_REVISION", 0x34d00, 0 },
|
|
{ "CUSTREV", 16, 16 },
|
|
{ "VER", 8, 8 },
|
|
{ "REV", 0, 8 },
|
|
{ "MAC_PORT_MTIP_1G10G_SCRATCH", 0x34d04, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_COMMAND_CONFIG", 0x34d08, 0 },
|
|
{ "SHORT_DISCARD", 25, 1 },
|
|
{ "REG_LOWP_RXEMPTY", 24, 1 },
|
|
{ "TX_LOWP_ENA", 23, 1 },
|
|
{ "TX_FLUSH", 22, 1 },
|
|
{ "SFD_ANY", 21, 1 },
|
|
{ "PAUSE_PFC_COMP", 20, 1 },
|
|
{ "PFC_MODE", 19, 1 },
|
|
{ "COL_CNT_ExT", 18, 1 },
|
|
{ "NO_LGTH_CHECK", 17, 1 },
|
|
{ "FORCE_SEND_IDLE", 16, 1 },
|
|
{ "PHY_TXENA", 15, 1 },
|
|
{ "RX_ERR_DISC", 14, 1 },
|
|
{ "CNTL_FRM_ENA", 13, 1 },
|
|
{ "SW_RESET", 12, 1 },
|
|
{ "TX_PAD_EN", 11, 1 },
|
|
{ "LOOP_ENA", 10, 1 },
|
|
{ "TX_ADDR_INS", 9, 1 },
|
|
{ "PAUSE_IGNORE", 8, 1 },
|
|
{ "PAUSE_FWD", 7, 1 },
|
|
{ "CRC_FWD", 6, 1 },
|
|
{ "PAD_EN", 5, 1 },
|
|
{ "PROMIS_EN", 4, 1 },
|
|
{ "WAN_MODE", 3, 1 },
|
|
{ "RX_ENAMAC", 1, 1 },
|
|
{ "TX_ENAMAC", 0, 1 },
|
|
{ "MAC_PORT_MTIP_1G10G_MAC_ADDR_0", 0x34d0c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_MAC_ADDR_1", 0x34d10, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU", 0x34d14, 0 },
|
|
{ "SET_LEN", 16, 16 },
|
|
{ "FRM_LEN_SET", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS", 0x34d1c, 0 },
|
|
{ "EMPTY", 16, 16 },
|
|
{ "AVAIL", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS", 0x34d20, 0 },
|
|
{ "EMPTY", 16, 16 },
|
|
{ "AVAIL", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E", 0x34d24, 0 },
|
|
{ "AlmostFull", 16, 16 },
|
|
{ "AlmostEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E", 0x34d28, 0 },
|
|
{ "AlmostFull", 16, 16 },
|
|
{ "AlmostEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD", 0x34d2c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS", 0x34d30, 0 },
|
|
{ "Clk_divisor", 7, 9 },
|
|
{ "ENA_CLAUSE", 6, 1 },
|
|
{ "PREAMBLE_DISABLE", 5, 1 },
|
|
{ "Hold_time_setting", 2, 3 },
|
|
{ "MDIO_read_error", 1, 1 },
|
|
{ "MDIO_Busy", 0, 1 },
|
|
{ "MAC_PORT_MTIP_1G10G_MDIO_COMMAND", 0x34d34, 0 },
|
|
{ "READ_MODE", 15, 1 },
|
|
{ "POST_INCR_READ", 14, 1 },
|
|
{ "Port_PHY_Addr", 5, 5 },
|
|
{ "Device_Reg_Addr", 0, 5 },
|
|
{ "MAC_PORT_MTIP_1G10G_MDIO_DATA", 0x34d38, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_MDIO_REGADDR", 0x34d3c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_STATUS", 0x34d40, 0 },
|
|
{ "RX_LINT_FAULT", 7, 1 },
|
|
{ "RX_EMPTY", 6, 1 },
|
|
{ "TX_EMPTY", 5, 1 },
|
|
{ "RX_LOWP", 4, 1 },
|
|
{ "TS_AVAIL", 3, 1 },
|
|
{ "PHY_LOS", 2, 1 },
|
|
{ "RX_REM_FAULT", 1, 1 },
|
|
{ "RX_LOC_FAULT", 0, 1 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH", 0x34d44, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER", 0x34d48, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_INIT_CREDIT", 0x34d4c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA", 0x34d54, 0 },
|
|
{ "CL1_PAUSE_QUANTA", 16, 16 },
|
|
{ "CL0_PAUSE_QUANTA", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA", 0x34d58, 0 },
|
|
{ "CL3_PAUSE_QUANTA", 16, 16 },
|
|
{ "CL2_PAUSE_QUANTA", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA", 0x34d5c, 0 },
|
|
{ "CL5_PAUSE_QUANTA", 16, 16 },
|
|
{ "CL4_PAUSE_QUANTA", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA", 0x34d60, 0 },
|
|
{ "CL7_PAUSE_QUANTA", 16, 16 },
|
|
{ "CL6_PAUSE_QUANTA", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH", 0x34d64, 0 },
|
|
{ "CL1_QUANTA_THRESH", 16, 16 },
|
|
{ "CL0_QUANTA_THRESH", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH", 0x34d68, 0 },
|
|
{ "CL3_QUANTA_THRESH", 16, 16 },
|
|
{ "CL2_QUANTA_THRESH", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH", 0x34d6c, 0 },
|
|
{ "CL5_QUANTA_THRESH", 16, 16 },
|
|
{ "CL4_QUANTA_THRESH", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH", 0x34d70, 0 },
|
|
{ "CL7_QUANTA_THRESH", 16, 16 },
|
|
{ "CL6_QUANTA_THRESH", 0, 16 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS", 0x34d74, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TS_TIMESTAMP", 0x34d7c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_STATN_CONFIG", 0x34de0, 0 },
|
|
{ "CLEAR", 2, 1 },
|
|
{ "CLEAR_ON_READ", 1, 1 },
|
|
{ "SATURATE", 0, 1 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS", 0x34e00, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI", 0x34e04, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_OCTETSOK", 0x34e08, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI", 0x34e0c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS", 0x34e10, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI", 0x34e14, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES", 0x34e18, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI", 0x34e1c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_FRAMESOK", 0x34e20, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI", 0x34e24, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_CRCERRORS", 0x34e28, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI", 0x34e2c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_VLANOK", 0x34e30, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_VLANOKHI", 0x34e34, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINERRORS", 0x34e38, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI", 0x34e3c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS", 0x34e40, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI", 0x34e44, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS", 0x34e48, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI", 0x34e4c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS", 0x34e50, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI", 0x34e54, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS", 0x34e58, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI", 0x34e5c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS", 0x34e60, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI", 0x34e64, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS", 0x34e68, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI", 0x34e6c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS", 0x34e70, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI", 0x34e74, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS", 0x34e78, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI", 0x34e7c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS", 0x34e80, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI", 0x34e84, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS", 0x34e88, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI", 0x34e8c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS", 0x34e90, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI", 0x34e94, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS", 0x34e98, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x34e9c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX", 0x34ea0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI", 0x34ea4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS", 0x34ea8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI", 0x34eac, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS", 0x34eb0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI", 0x34eb4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS", 0x34eb8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI", 0x34ebc, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED", 0x34ec0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI", 0x34ec4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG", 0x34ec8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI", 0x34ecc, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS", 0x34ed0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI", 0x34ed4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS", 0x34f00, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI", 0x34f04, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_OCTETSOK", 0x34f08, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI", 0x34f0c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS", 0x34f10, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI", 0x34f14, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES", 0x34f18, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI", 0x34f1c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_FRAMESOK", 0x34f20, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI", 0x34f24, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_CRCERRORS", 0x34f28, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI", 0x34f2c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_VLANOK", 0x34f30, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_VLANOKHI", 0x34f34, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS", 0x34f38, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI", 0x34f3c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS", 0x34f40, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI", 0x34f44, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS", 0x34f48, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI", 0x34f4c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS", 0x34f50, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI", 0x34f54, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS", 0x34f58, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI", 0x34f5c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS", 0x34f60, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI", 0x34f64, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS", 0x34f68, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI", 0x34f6c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS", 0x34f70, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI", 0x34f74, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS", 0x34f78, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI", 0x34f7c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS", 0x34f80, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI", 0x34f84, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS", 0x34f88, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI", 0x34f8c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS", 0x34f90, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI", 0x34f94, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS", 0x34f98, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x34f9c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU", 0x34fa0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI", 0x34fa4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES", 0x34fc0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI", 0x34fc4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_IF_MODE", 0x35000, 0 },
|
|
{ "MII_ENA_10", 4, 1 },
|
|
{ "IF_MODE", 0, 2 },
|
|
{ "MAC_PORT_MTIP_1G10G_IF_STATUS", 0x35004, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0", 0x35080, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI", 0x35084, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1", 0x35088, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI", 0x3508c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2", 0x35090, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI", 0x35094, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3", 0x35098, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI", 0x3509c, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4", 0x350a0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI", 0x350a4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5", 0x350a8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI", 0x350ac, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6", 0x350b0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI", 0x350b4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7", 0x350b8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI", 0x350bc, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0", 0x350c0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI", 0x350c4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1", 0x350c8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI", 0x350cc, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2", 0x350d0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI", 0x350d4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3", 0x350d8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI", 0x350dc, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4", 0x350e0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI", 0x350e4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5", 0x350e8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI", 0x350ec, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6", 0x350f0, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI", 0x350f4, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7", 0x350f8, 0 },
|
|
{ "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI", 0x350fc, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_CONTROL", 0x35200, 0 },
|
|
{ "Reset", 15, 1 },
|
|
{ "Loopback", 14, 1 },
|
|
{ "Speed_Sel", 13, 1 },
|
|
{ "AN_EN", 12, 1 },
|
|
{ "PWR_DWN", 11, 1 },
|
|
{ "Isolate", 10, 1 },
|
|
{ "AN_RESTART", 9, 1 },
|
|
{ "DUPLEx_MODE", 8, 1 },
|
|
{ "Collision_Test", 7, 1 },
|
|
{ "Speed_Sel1", 6, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_STATUS", 0x35204, 0 },
|
|
{ "100BaseT4", 15, 1 },
|
|
{ "100BasexFullDplx", 14, 1 },
|
|
{ "100BasexHalfDplx", 13, 1 },
|
|
{ "10MbpsFullDplx", 12, 1 },
|
|
{ "10MbpsHalfDplx", 11, 1 },
|
|
{ "100BaseT2FullDplx", 10, 1 },
|
|
{ "100BaseT2HalfDplx", 9, 1 },
|
|
{ "ExtdStatus", 8, 1 },
|
|
{ "AN_Complete", 5, 1 },
|
|
{ "REM_FAULT", 4, 1 },
|
|
{ "AN_Ability", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "JabberDetect", 1, 1 },
|
|
{ "ExtdCapability", 0, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x35208, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x3520c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x35210, 0 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "RF2", 13, 1 },
|
|
{ "RF1", 12, 1 },
|
|
{ "PS2", 8, 1 },
|
|
{ "PS1", 7, 1 },
|
|
{ "HD", 6, 1 },
|
|
{ "FD", 5, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x35214, 0 },
|
|
{ "CuLinkStatus", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "CuDplxStatus", 12, 1 },
|
|
{ "CuSpeed", 10, 2 },
|
|
{ "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x35218, 0 },
|
|
{ "Next_Page_Able", 2, 1 },
|
|
{ "PAGE_RECEIVE", 1, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_NP_TX", 0x3521c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_LP_NP_RX", 0x35220, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x3523c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_SCRATCH", 0x35240, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_REV", 0x35244, 0 },
|
|
{ "CUSTREV", 16, 16 },
|
|
{ "VER", 8, 8 },
|
|
{ "REV", 0, 8 },
|
|
{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x35248, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x3524c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_IF_MODE", 0x35250, 0 },
|
|
{ "SGMII_DUPLEx", 4, 1 },
|
|
{ "SGMII_SPEED", 2, 2 },
|
|
{ "USE_SGMII_AN", 1, 1 },
|
|
{ "SGMII_ENA", 0, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_DECODE_ERROR", 0x35254, 0 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_CONTROL_1", 0x35300, 0 },
|
|
{ "Reset", 15, 1 },
|
|
{ "Loopback", 14, 1 },
|
|
{ "Speed_SEL", 13, 1 },
|
|
{ "Low_Power", 11, 1 },
|
|
{ "Speed_SEL1", 6, 1 },
|
|
{ "Speed_SEL2", 2, 4 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_STATUS_1", 0x35304, 0 },
|
|
{ "TX_LPI", 11, 1 },
|
|
{ "RX_LPI", 10, 1 },
|
|
{ "TX_LPI_ACTIVE", 9, 1 },
|
|
{ "RX_LPI_ACTIVE", 8, 1 },
|
|
{ "Fault", 7, 1 },
|
|
{ "PCS_RX_Link_STAT", 2, 1 },
|
|
{ "Low_power_Ability", 1, 1 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1", 0x35308, 0 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2", 0x3530c, 0 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY", 0x35310, 0 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO", 0x35314, 0 },
|
|
{ "Auto_Negotiation_Present", 7, 1 },
|
|
{ "DTE_xS_present", 5, 1 },
|
|
{ "PHY_xS_present", 4, 1 },
|
|
{ "PCS_present", 3, 1 },
|
|
{ "WIS_present", 2, 1 },
|
|
{ "PMD_PMA_Present", 1, 1 },
|
|
{ "Clause_22_Reg_Present", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI", 0x35318, 0 },
|
|
{ "Auto_Negotiation_Present", 7, 1 },
|
|
{ "DTE_xS_present", 5, 1 },
|
|
{ "PHY_xS_present", 4, 1 },
|
|
{ "PCS_present", 3, 1 },
|
|
{ "WIS_present", 2, 1 },
|
|
{ "PMD_PMA_Present", 1, 1 },
|
|
{ "Clause_22_Reg_Present", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_CONTROL_2", 0x3531c, 0 },
|
|
{ "MAC_PORT_MTIP_KR_PCS_STATUS_2", 0x35320, 0 },
|
|
{ "Device_Present", 14, 2 },
|
|
{ "Transmit_Fault", 11, 1 },
|
|
{ "Receive_Fault", 10, 1 },
|
|
{ "10GBASE_W_Capable", 2, 1 },
|
|
{ "10GBASE_x_Capable", 1, 1 },
|
|
{ "10GBASE_R_Capable", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO", 0x35338, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI", 0x3533c, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1", 0x35380, 0 },
|
|
{ "10GBASE_R_RX_Link_Status", 12, 1 },
|
|
{ "PRBS9_Pttrn_Tstng_Ability", 3, 1 },
|
|
{ "PRBS31_Pttrn_Tstng_Ability", 2, 1 },
|
|
{ "10GBASE_R_PCS_High_BER", 1, 1 },
|
|
{ "10GBASE_R_PCS_Block_Lock", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2", 0x35384, 0 },
|
|
{ "Latched_Block_Lock", 15, 1 },
|
|
{ "Latched_High_BER", 14, 1 },
|
|
{ "BERBER_Counter", 8, 6 },
|
|
{ "ErrBlkCnt", 0, 8 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0", 0x35388, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1", 0x3538c, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2", 0x35390, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3", 0x35394, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0", 0x35398, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1", 0x3539c, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2", 0x353a0, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3", 0x353a4, 0 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL", 0x353a8, 0 },
|
|
{ "PRBS9_TX_Tst_Pttrn_En", 6, 1 },
|
|
{ "PRBS31_RX_Tst_Pttrn_En", 5, 1 },
|
|
{ "PRBS31_TX_Tst_Pttrn_En", 4, 1 },
|
|
{ "TX_Test_Pattern_En", 3, 1 },
|
|
{ "RX_Test_Pattern_En", 2, 1 },
|
|
{ "Test_Pattern_Select", 1, 1 },
|
|
{ "Data_Pattern_Select", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER", 0x353ac, 0 },
|
|
{ "MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS", 0x353b4, 0 },
|
|
{ "Transmit_FIFO_Fault", 1, 1 },
|
|
{ "Receive_FIFO_Fault", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_CONTROL_1", 0x35400, 0 },
|
|
{ "RESET", 15, 1 },
|
|
{ "Loopback", 14, 1 },
|
|
{ "Speed_selection", 13, 1 },
|
|
{ "Low_power", 11, 1 },
|
|
{ "Speed_selection1", 6, 1 },
|
|
{ "Speed_selection2", 2, 4 },
|
|
{ "MAC_PORT_MTIP_KR4_STATUS_1", 0x35404, 0 },
|
|
{ "Fault", 7, 1 },
|
|
{ "Receive_link_STAT", 2, 1 },
|
|
{ "Low_power_ability", 1, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_DEVICE_ID0", 0x35408, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_DEVICE_ID1", 0x3540c, 0 },
|
|
{ "DEVICE_ID1", 16, 16 },
|
|
{ "MAC_PORT_MTIP_KR4_SPEED_ABILITY", 0x35410, 0 },
|
|
{ "100G_capable", 3, 1 },
|
|
{ "40G_capable", 2, 1 },
|
|
{ "10PASS_TS_2Base_TL_capable", 1, 1 },
|
|
{ "10G_capable", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1", 0x35414, 0 },
|
|
{ "TC_present", 6, 1 },
|
|
{ "DTE_xS_present", 5, 1 },
|
|
{ "PHY_xS_present", 4, 1 },
|
|
{ "PCS_present", 3, 1 },
|
|
{ "WIS_present", 2, 1 },
|
|
{ "PMD_PMA_present", 1, 1 },
|
|
{ "Clause_22_reg", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2", 0x35418, 0 },
|
|
{ "Vendor_specific_device", 15, 1 },
|
|
{ "Vendor_specific_device1", 14, 1 },
|
|
{ "Clause_22_ExT", 13, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_CONTROL_2", 0x3541c, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_STATUS_2", 0x35420, 0 },
|
|
{ "Device_present", 14, 2 },
|
|
{ "Transmit_fault", 11, 1 },
|
|
{ "Receive_fault", 10, 1 },
|
|
{ "100GBase_R_capable", 5, 1 },
|
|
{ "40GBase_R_capable", 4, 1 },
|
|
{ "10GBase_T_capable", 3, 1 },
|
|
{ "10GBase_W_capable", 2, 1 },
|
|
{ "10GBase_x_capable", 1, 1 },
|
|
{ "10GBase_R_capable", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_PKG_ID0", 0x35438, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_PKG_ID1", 0x3543c, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_BASE_R_STATUS_1", 0x35480, 0 },
|
|
{ "RX_link_status", 12, 1 },
|
|
{ "High_BER", 1, 1 },
|
|
{ "Block_lock", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_BASE_R_STATUS_2", 0x35484, 0 },
|
|
{ "Latched_bl_lk", 15, 1 },
|
|
{ "Latched_hg_br", 14, 1 },
|
|
{ "Ber_cnt", 8, 6 },
|
|
{ "Err_bl_cnt", 0, 8 },
|
|
{ "MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL", 0x354a8, 0 },
|
|
{ "TX_TP_EN", 3, 1 },
|
|
{ "RX_TP_EN", 2, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT", 0x354ac, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT", 0x354b0, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT", 0x354b4, 0 },
|
|
{ "HI_ORDER_CNT_EN", 15, 1 },
|
|
{ "ERR_BLK_CNTR", 0, 14 },
|
|
{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1", 0x354c8, 0 },
|
|
{ "LANE_ALIGN_STATUS", 12, 1 },
|
|
{ "LANE_3_BLK_LCK", 3, 1 },
|
|
{ "LANE_2_BLK_LC32_6431K", 2, 1 },
|
|
{ "LANE_1_BLK_LCK", 1, 1 },
|
|
{ "LANE_0_BLK_LCK", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2", 0x354cc, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3", 0x354d0, 0 },
|
|
{ "LANE_3_ALIGN_MRKR_LCK", 3, 1 },
|
|
{ "LANE_2_ALIGN_MRKR_LCK", 2, 1 },
|
|
{ "LANE_1_ALIGN_MRKR_LCK", 1, 1 },
|
|
{ "LANE_0_ALIGN_MRKR_LCK", 0, 1 },
|
|
{ "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4", 0x354d4, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0", 0x35720, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1", 0x35724, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2", 0x35728, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3", 0x3572c, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_LANE_0_MAPPING", 0x35a40, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_LANE_1_MAPPING", 0x35a44, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_LANE_2_MAPPING", 0x35a48, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_LANE_3_MAPPING", 0x35a4c, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_SCRATCH", 0x35af0, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_CORE_REVISION", 0x35af4, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_VL_INTVL", 0x35af8, 0 },
|
|
{ "MAC_PORT_MTIP_KR4_TX_LANE_THRESH", 0x35afc, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_CONTROL_1", 0x35b00, 0 },
|
|
{ "Reset", 15, 1 },
|
|
{ "Loopback", 14, 1 },
|
|
{ "Speed_selection", 13, 1 },
|
|
{ "Low_power", 11, 1 },
|
|
{ "Speed_selection1", 6, 1 },
|
|
{ "Speed_selection2", 2, 4 },
|
|
{ "MAC_PORT_MTIP_CR4_STATUS_1", 0x35b04, 0 },
|
|
{ "Fault", 7, 1 },
|
|
{ "RX_Link_Status", 2, 1 },
|
|
{ "Low_power_ability", 1, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_DEVICE_ID0", 0x35b08, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_DEVICE_ID1", 0x35b0c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_SPEED_ABILITY", 0x35b10, 0 },
|
|
{ "100G_capable", 8, 1 },
|
|
{ "40G_capable", 7, 1 },
|
|
{ "10PASS_TS_2Base_TL_capable", 1, 1 },
|
|
{ "10G_capable", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1", 0x35b14, 0 },
|
|
{ "TC_present", 6, 1 },
|
|
{ "DTE_xS_present", 5, 1 },
|
|
{ "PHY_xS_present", 4, 1 },
|
|
{ "PCS_present", 3, 1 },
|
|
{ "WIS_present", 2, 1 },
|
|
{ "PMD_PMA_present", 1, 1 },
|
|
{ "Clause22reg_present", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2", 0x35b18, 0 },
|
|
{ "VSD_2_PRESENT", 15, 1 },
|
|
{ "VSD_1_PRESENT", 14, 1 },
|
|
{ "Clause22_ExT_Present", 13, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_CONTROL_2", 0x35b1c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_STATUS_2", 0x35b20, 0 },
|
|
{ "Device_present", 14, 2 },
|
|
{ "Transmit_fault", 11, 1 },
|
|
{ "Receive_fault", 10, 1 },
|
|
{ "100GBase_R_capable", 5, 1 },
|
|
{ "40GBase_R_capable", 4, 1 },
|
|
{ "10GBase_T_capable", 3, 1 },
|
|
{ "10GBase_W_capable", 2, 1 },
|
|
{ "10GBase_x_capable", 1, 1 },
|
|
{ "10GBase_R_capable", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_PKG_ID0", 0x35b38, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_PKG_ID1", 0x35b3c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BASE_R_STATUS_1", 0x35b80, 0 },
|
|
{ "RX_Link_STAT", 12, 1 },
|
|
{ "High_BER", 1, 1 },
|
|
{ "Block_Lock", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_BASE_R_STATUS_2", 0x35b84, 0 },
|
|
{ "Latched_block_lock", 15, 1 },
|
|
{ "Latched_high_BER", 14, 1 },
|
|
{ "BER_counter", 8, 6 },
|
|
{ "Errored_blocks_cntr", 0, 8 },
|
|
{ "MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL", 0x35ba8, 0 },
|
|
{ "Scrambled_ID_TP_EN", 7, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT", 0x35bac, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT", 0x35bb0, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT", 0x35bb4, 0 },
|
|
{ "Hi_ORDER_CNT_Present", 15, 1 },
|
|
{ "ERR_BLKS_CNTR", 0, 14 },
|
|
{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1", 0x35bc8, 0 },
|
|
{ "LANE_ALIGN_STAT", 12, 1 },
|
|
{ "Lane_7_blck_lck", 7, 1 },
|
|
{ "Lane_6_blck_lck", 6, 1 },
|
|
{ "Lane_5_blck_lck", 5, 1 },
|
|
{ "Lane_4_blck_lck", 4, 1 },
|
|
{ "Lane_3_blck_lck", 3, 1 },
|
|
{ "Lane_2_blck_lck", 2, 1 },
|
|
{ "Lane_1_blck_lck", 1, 1 },
|
|
{ "Lane_0_blck_lck", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2", 0x35bcc, 0 },
|
|
{ "Lane_19_blck_lck", 11, 1 },
|
|
{ "Lane_18_blck_lck", 10, 1 },
|
|
{ "Lane_17_blck_lck", 9, 1 },
|
|
{ "Lane_16_blck_lck", 8, 1 },
|
|
{ "Lane_15_blck_lck", 7, 1 },
|
|
{ "Lane_14_blck_lck", 6, 1 },
|
|
{ "Lane_13_blck_lck", 5, 1 },
|
|
{ "Lane_12_blck_lck", 4, 1 },
|
|
{ "Lane_11_blck_lck", 3, 1 },
|
|
{ "Lane_10_blck_lck", 2, 1 },
|
|
{ "Lane_9_blck_lck", 1, 1 },
|
|
{ "Lane_8_blck_lck", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3", 0x35bd0, 0 },
|
|
{ "Lane7_algn_mrkr_lck", 7, 1 },
|
|
{ "Lane6_algn_mrkr_lck", 6, 1 },
|
|
{ "Lane5_algn_mrkr_lck", 5, 1 },
|
|
{ "Lane4_algn_mrkr_lck", 4, 1 },
|
|
{ "Lane3_algn_mrkr_lck", 3, 1 },
|
|
{ "Lane2_algn_mrkr_lck", 2, 1 },
|
|
{ "Lane1_algn_mrkr_lck", 1, 1 },
|
|
{ "Lane0_algn_mrkr_lck", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4", 0x35bd4, 0 },
|
|
{ "Lane19_algn_mrkr_lck", 11, 1 },
|
|
{ "Lane18_algn_mrkr_lck", 10, 1 },
|
|
{ "Lane17_algn_mrkr_lck", 9, 1 },
|
|
{ "Lane16_algn_mrkr_lck", 8, 1 },
|
|
{ "Lane15_algn_mrkr_lck", 7, 1 },
|
|
{ "Lane14_algn_mrkr_lck", 6, 1 },
|
|
{ "Lane13_algn_mrkr_lck", 5, 1 },
|
|
{ "Lane12_algn_mrkr_lck", 4, 1 },
|
|
{ "Lane11_algn_mrkr_lck", 3, 1 },
|
|
{ "Lane10_algn_mrkr_lck", 2, 1 },
|
|
{ "Lane9_algn_mrkr_lck", 1, 1 },
|
|
{ "Lane8_algn_mrkr_lck", 0, 1 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0", 0x35e20, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1", 0x35e24, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2", 0x35e28, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3", 0x35e2c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4", 0x35e30, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5", 0x35e34, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6", 0x35e38, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7", 0x35e3c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8", 0x35e40, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9", 0x35e44, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10", 0x35e48, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11", 0x35e4c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12", 0x35e50, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13", 0x35e54, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14", 0x35e58, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15", 0x35e5c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16", 0x35e60, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17", 0x35e64, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18", 0x35e68, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19", 0x35e6c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_0_MAPPING", 0x36140, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_1_MAPPING", 0x36144, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_2_MAPPING", 0x36148, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_3_MAPPING", 0x3614c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_4_MAPPING", 0x36150, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_5_MAPPING", 0x36154, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_6_MAPPING", 0x36158, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_7_MAPPING", 0x3615c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_8_MAPPING", 0x36160, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_9_MAPPING", 0x36164, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_10_MAPPING", 0x36168, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_11_MAPPING", 0x3616c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_12_MAPPING", 0x36170, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_13_MAPPING", 0x36174, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_14_MAPPING", 0x36178, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_15_MAPPING", 0x3617c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_16_MAPPING", 0x36180, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_17_MAPPING", 0x36184, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_18_MAPPING", 0x36188, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_LANE_19_MAPPING", 0x3618c, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_SCRATCH", 0x361f0, 0 },
|
|
{ "MAC_PORT_MTIP_CR4_CORE_REVISION", 0x361f4, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_CONTROL", 0x36200, 0 },
|
|
{ "RS_FEC_Bypass_Error_Indication", 1, 1 },
|
|
{ "RS_FEC_Bypass_Correction", 0, 1 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_STATUS", 0x36204, 0 },
|
|
{ "RS_FEC_PCS_align_status", 15, 1 },
|
|
{ "fec_align_status", 14, 1 },
|
|
{ "RS_FEC_high_SER", 2, 1 },
|
|
{ "RS_FEC_bypass_error_indication_ability", 1, 1 },
|
|
{ "RS_FEC_bypass_correction_ability", 0, 1 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_CCW_LO", 0x36208, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_CCW_HI", 0x3620c, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_NCCW_LO", 0x36210, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_NCCW_HI", 0x36214, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI", 0x36218, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO", 0x36228, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI", 0x3622c, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO", 0x36230, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI", 0x36234, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO", 0x36238, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI", 0x3623c, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO", 0x36240, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI", 0x36244, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL", 0x36400, 0 },
|
|
{ "RS_FEC_enabled_status", 15, 1 },
|
|
{ "RS_FEC_Enable", 2, 1 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1", 0x36404, 0 },
|
|
{ "deskew_empty", 12, 4 },
|
|
{ "fec_align_status_lh", 10, 1 },
|
|
{ "tx_dp_overflow", 9, 1 },
|
|
{ "rx_dp_overflow", 8, 1 },
|
|
{ "tx_datapath_restart", 7, 1 },
|
|
{ "rx_datapath_restart", 6, 1 },
|
|
{ "marker_check_restart", 5, 1 },
|
|
{ "fec_align_status_ll", 4, 1 },
|
|
{ "amps_lock", 0, 4 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2", 0x36408, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION", 0x3640c, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY", 0x36410, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS", 0x36414, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN", 0x36418, 0 },
|
|
{ "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER", 0x3641c, 0 },
|
|
{ "MAC_PORT_MTIP_FEC_ABILITY", 0x36618, 0 },
|
|
{ "BASE_R_FEC_Error_Indication_Ability", 1, 1 },
|
|
{ "BASE_R_FEC_Ability", 0, 1 },
|
|
{ "MAC_PORT_FEC_CONTROL", 0x3661c, 0 },
|
|
{ "fec_en_err_ind", 1, 1 },
|
|
{ "fec_en", 0, 1 },
|
|
{ "MAC_PORT_FEC_STATUS", 0x36620, 0 },
|
|
{ "FEC_LOCKED0", 1, 4 },
|
|
{ "FEC_LOCKED", 0, 1 },
|
|
{ "MAC_PORT_MTIP_FEC0_CERR_CNT_0", 0x36624, 0 },
|
|
{ "MAC_PORT_MTIP_FEC0_CERR_CNT_1", 0x36628, 0 },
|
|
{ "MAC_PORT_MTIP_FEC0_NCERR_CNT_0", 0x3662c, 0 },
|
|
{ "MAC_PORT_MTIP_FEC0_NCERR_CNT_1", 0x36630, 0 },
|
|
{ "MAC_PORT_MTIP_FEC_STATUS1", 0x36664, 0 },
|
|
{ "FEC_LOCKED0", 1, 4 },
|
|
{ "FEC_LOCKED", 0, 1 },
|
|
{ "MAC_PORT_MTIP_FEC1_CERR_CNT_0", 0x36668, 0 },
|
|
{ "MAC_PORT_MTIP_FEC1_CERR_CNT_1", 0x3666c, 0 },
|
|
{ "MAC_PORT_MTIP_FEC1_NCERR_CNT_0", 0x36670, 0 },
|
|
{ "MAC_PORT_MTIP_FEC1_NCERR_CNT_1", 0x36674, 0 },
|
|
{ "MAC_PORT_MTIP_FEC_STATUS2", 0x366a8, 0 },
|
|
{ "FEC_LOCKED0", 1, 4 },
|
|
{ "FEC_LOCKED", 0, 1 },
|
|
{ "MAC_PORT_MTIP_FEC2_CERR_CNT_0", 0x366ac, 0 },
|
|
{ "MAC_PORT_MTIP_FEC2_CERR_CNT_1", 0x366b0, 0 },
|
|
{ "MAC_PORT_MTIP_FEC2_NCERR_CNT_0", 0x366b4, 0 },
|
|
{ "MAC_PORT_MTIP_FEC2_NCERR_CNT_1", 0x366b8, 0 },
|
|
{ "MAC_PORT_MTIP_FEC_STATUS3", 0x366ec, 0 },
|
|
{ "FEC_LOCKED0", 1, 4 },
|
|
{ "FEC_LOCKED", 0, 1 },
|
|
{ "MAC_PORT_MTIP_FEC3_CERR_CNT_0", 0x366f0, 0 },
|
|
{ "MAC_PORT_MTIP_FEC3_CERR_CNT_1", 0x366f4, 0 },
|
|
{ "MAC_PORT_MTIP_FEC3_NCERR_CNT_0", 0x366f8, 0 },
|
|
{ "MAC_PORT_MTIP_FEC3_NCERR_CNT_1", 0x366fc, 0 },
|
|
{ "MAC_PORT_BEAN_CTL", 0x36c00, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS", 0x36c04, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0", 0x36c08, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1", 0x36c0c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2", 0x36c10, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0", 0x36c14, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1", 0x36c18, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2", 0x36c1c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT", 0x36c20, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0", 0x36c24, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1", 0x36c28, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2", 0x36c2c, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0", 0x36c30, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1", 0x36c34, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2", 0x36c38, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS", 0x36c3c, 0 },
|
|
{ "100GCR4", 11, 1 },
|
|
{ "100GKR4", 10, 1 },
|
|
{ "100GKP4", 9, 1 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ", 0x36a00, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C3", 6, 2 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT", 0x36a04, 0 },
|
|
{ "T5_AE0_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE0_RXSTAT_LSNA", 14, 1 },
|
|
{ "T5_AE0_RXSTAT_FEC", 13, 1 },
|
|
{ "T5_AE0_RXSTAT_TF", 12, 1 },
|
|
{ "T5_AE0_RXSTAT_C3", 6, 2 },
|
|
{ "T5_AE0_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE0_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE0_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ", 0x36a08, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "TXREQ_FEC", 11, 1 },
|
|
{ "T5_TXREQ_C3", 6, 2 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT", 0x36a0c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C3", 6, 2 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE", 0x36a10, 0 },
|
|
{ "SET_WAIT_TIMER", 13, 2 },
|
|
{ "C2_C3_STATE_SEL", 12, 1 },
|
|
{ "FFE4_EN", 11, 1 },
|
|
{ "FEC_REQUEST", 10, 1 },
|
|
{ "FEC_SUPPORTED", 9, 1 },
|
|
{ "TX_FIXED", 8, 1 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL", 0x36a14, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL", 0x36a18, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE", 0x36a1c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_1", 0x36a20, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C3", 6, 2 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_1", 0x36a24, 0 },
|
|
{ "T5_AE1_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE1_RXSTAT_LSNA", 14, 1 },
|
|
{ "T5_AE1_RXSTAT_FEC", 13, 1 },
|
|
{ "T5_AE1_RXSTAT_TF", 12, 1 },
|
|
{ "T5_AE1_RXSTAT_C3", 6, 2 },
|
|
{ "T5_AE1_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE1_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE1_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_1", 0x36a28, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "TXREQ_FEC", 11, 1 },
|
|
{ "T5_TXREQ_C3", 6, 2 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_1", 0x36a2c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C3", 6, 2 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_1", 0x36a30, 0 },
|
|
{ "SET_WAIT_TIMER", 13, 2 },
|
|
{ "C2_C3_STATE_SEL", 12, 1 },
|
|
{ "FFE4_EN", 11, 1 },
|
|
{ "FEC_REQUEST", 10, 1 },
|
|
{ "FEC_SUPPORTED", 9, 1 },
|
|
{ "TX_FIXED", 8, 1 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_1", 0x36a34, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_1", 0x36a38, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_1", 0x36a3c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_2", 0x36a40, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C3", 6, 2 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_2", 0x36a44, 0 },
|
|
{ "T5_AE2_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE2_RXSTAT_LSNA", 14, 1 },
|
|
{ "T5_AE2_RXSTAT_FEC", 13, 1 },
|
|
{ "T5_AE2_RXSTAT_TF", 12, 1 },
|
|
{ "T5_AE2_RXSTAT_C3", 6, 2 },
|
|
{ "T5_AE2_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE2_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE2_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_2", 0x36a48, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "TXREQ_FEC", 11, 1 },
|
|
{ "T5_TXREQ_C3", 6, 2 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_2", 0x36a4c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C3", 6, 2 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_2", 0x36a50, 0 },
|
|
{ "SET_WAIT_TIMER", 13, 2 },
|
|
{ "C2_C3_STATE_SEL", 12, 1 },
|
|
{ "FFE4_EN", 11, 1 },
|
|
{ "FEC_REQUEST", 10, 1 },
|
|
{ "FEC_SUPPORTED", 9, 1 },
|
|
{ "TX_FIXED", 8, 1 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_2", 0x36a54, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_2", 0x36a58, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_2", 0x36a5c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_3", 0x36a60, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C3", 6, 2 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_3", 0x36a64, 0 },
|
|
{ "T5_AE3_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE3_RXSTAT_LSNA", 14, 1 },
|
|
{ "T5_AE3_RXSTAT_FEC", 13, 1 },
|
|
{ "T5_AE3_RXSTAT_TF", 12, 1 },
|
|
{ "T5_AE3_RXSTAT_C3", 6, 2 },
|
|
{ "T5_AE3_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE3_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE3_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_3", 0x36a68, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "TXREQ_FEC", 11, 1 },
|
|
{ "T5_TXREQ_C3", 6, 2 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_3", 0x36a6c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C3", 6, 2 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_3", 0x36a70, 0 },
|
|
{ "SET_WAIT_TIMER", 13, 2 },
|
|
{ "C2_C3_STATE_SEL", 12, 1 },
|
|
{ "FFE4_EN", 11, 1 },
|
|
{ "FEC_REQUEST", 10, 1 },
|
|
{ "FEC_SUPPORTED", 9, 1 },
|
|
{ "TX_FIXED", 8, 1 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_3", 0x36a74, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_3", 0x36a78, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_3", 0x36a7c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_TX_DIS", 0x36a80, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL", 0x36a84, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET", 0x36a88, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS", 0x36a8c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_1", 0x36a90, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_1", 0x36a94, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_1", 0x36a98, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_1", 0x36a9c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_2", 0x36aa0, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_2", 0x36aa4, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_2", 0x36aa8, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_2", 0x36aac, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_3", 0x36ab0, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_3", 0x36ab4, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_3", 0x36ab8, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_3", 0x36abc, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x36b00, 0 },
|
|
{ "INIT_METH", 12, 4 },
|
|
{ "INIT_CNT", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_N0", 5, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x36b04, 0 },
|
|
{ "FEC_CNV", 15, 1 },
|
|
{ "EN_RETRY", 14, 1 },
|
|
{ "DPC_METH", 12, 2 },
|
|
{ "EN_P2", 11, 1 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_0", 0x36b08, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x36b0c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT5", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_0", 0x36b10, 0 },
|
|
{ "CTRL_STAT", 8, 5 },
|
|
{ "NEU_STATE", 4, 4 },
|
|
{ "CTRL_STATE", 0, 4 },
|
|
{ "MAC_PORT_AET_STATUS_20", 0x36b14, 0 },
|
|
{ "MAC_PORT_AET_LIMITS0", 0x36b18, 0 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x36b20, 0 },
|
|
{ "INIT_METH", 12, 4 },
|
|
{ "INIT_CNT", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_N0", 5, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x36b24, 0 },
|
|
{ "FEC_CNV", 15, 1 },
|
|
{ "EN_RETRY", 14, 1 },
|
|
{ "DPC_METH", 12, 2 },
|
|
{ "EN_P2", 11, 1 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_1", 0x36b28, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x36b2c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT5", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_1", 0x36b30, 0 },
|
|
{ "CTRL_STAT", 8, 5 },
|
|
{ "NEU_STATE", 4, 4 },
|
|
{ "CTRL_STATE", 0, 4 },
|
|
{ "MAC_PORT_AET_STATUS_21", 0x36b34, 0 },
|
|
{ "MAC_PORT_AET_LIMITS1", 0x36b38, 0 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x36b40, 0 },
|
|
{ "INIT_METH", 12, 4 },
|
|
{ "INIT_CNT", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_N0", 5, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x36b44, 0 },
|
|
{ "FEC_CNV", 15, 1 },
|
|
{ "EN_RETRY", 14, 1 },
|
|
{ "DPC_METH", 12, 2 },
|
|
{ "EN_P2", 11, 1 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_2", 0x36b48, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x36b4c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT5", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_2", 0x36b50, 0 },
|
|
{ "CTRL_STAT", 8, 5 },
|
|
{ "NEU_STATE", 4, 4 },
|
|
{ "CTRL_STATE", 0, 4 },
|
|
{ "MAC_PORT_AET_STATUS_22", 0x36b54, 0 },
|
|
{ "MAC_PORT_AET_LIMITS2", 0x36b58, 0 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x36b60, 0 },
|
|
{ "INIT_METH", 12, 4 },
|
|
{ "INIT_CNT", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_N0", 5, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x36b64, 0 },
|
|
{ "FEC_CNV", 15, 1 },
|
|
{ "EN_RETRY", 14, 1 },
|
|
{ "DPC_METH", 12, 2 },
|
|
{ "EN_P2", 11, 1 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_3", 0x36b68, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x36b6c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT5", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_3", 0x36b70, 0 },
|
|
{ "CTRL_STAT", 8, 5 },
|
|
{ "NEU_STATE", 4, 4 },
|
|
{ "CTRL_STATE", 0, 4 },
|
|
{ "MAC_PORT_AET_STATUS_23", 0x36b74, 0 },
|
|
{ "MAC_PORT_AET_LIMITS3", 0x36b78, 0 },
|
|
{ "MAC_PORT_ANALOG_TEST_MUX", 0x37814, 0 },
|
|
{ "MAC_PORT_PLLREFSEL_CONTROL", 0x37854, 0 },
|
|
{ "MAC_PORT_REFISINK_CONTROL", 0x37858, 0 },
|
|
{ "MAC_PORT_REFISRC_CONTROL", 0x3785c, 0 },
|
|
{ "MAC_PORT_REFVREG_CONTROL", 0x37860, 0 },
|
|
{ "MAC_PORT_VBGENDOC_CONTROL", 0x37864, 0 },
|
|
{ "BGCLKSEL", 2, 1 },
|
|
{ "VBGENDOC", 0, 2 },
|
|
{ "MAC_PORT_VREFTUNE_CONTROL", 0x37868, 0 },
|
|
{ "MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL", 0x37880, 0 },
|
|
{ "FRCCAL_COMP", 6, 1 },
|
|
{ "FRCERR", 5, 1 },
|
|
{ "CAL_BISTENAB", 4, 1 },
|
|
{ "RCAL_RESET", 0, 1 },
|
|
{ "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1", 0x37884, 0 },
|
|
{ "RCALBENAB", 3, 1 },
|
|
{ "RCALBUSY", 2, 1 },
|
|
{ "RCALERR", 1, 1 },
|
|
{ "RCALCOMP", 0, 1 },
|
|
{ "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2", 0x37888, 0 },
|
|
{ "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3", 0x3788c, 0 },
|
|
{ "MAC_PORT_INEQUALITY_CONTROL_AND_RESULT", 0x378c0, 0 },
|
|
{ "ISGT", 7, 1 },
|
|
{ "ISLT", 6, 1 },
|
|
{ "ISEQ", 5, 1 },
|
|
{ "ISVAL", 3, 2 },
|
|
{ "GTORLT", 1, 2 },
|
|
{ "INEQ", 0, 1 },
|
|
{ "MAC_PORT_INEQUALITY_LOW_LIMIT", 0x378c4, 0 },
|
|
{ "MAC_PORT_INEQUALITY_LOW_LIMIT_MASK", 0x378c8, 0 },
|
|
{ "MAC_PORT_INEQUALITY_HIGH_LIMIT", 0x378cc, 0 },
|
|
{ "MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK", 0x378d0, 0 },
|
|
{ "MAC_PORT_MACRO_TEST_CONTROL_6", 0x378e8, 0 },
|
|
{ "JTAGMD", 3, 1 },
|
|
{ "RXACMODE", 2, 1 },
|
|
{ "HSSACJPC", 1, 1 },
|
|
{ "HSSACJAC", 0, 1 },
|
|
{ "MAC_PORT_MACRO_TEST_CONTROL_5", 0x378ec, 0 },
|
|
{ "REFVALIDD", 6, 1 },
|
|
{ "REFVALIDC", 5, 1 },
|
|
{ "REFVALIDB", 4, 1 },
|
|
{ "REFVALIDA", 3, 1 },
|
|
{ "REFSELRESET", 2, 1 },
|
|
{ "SOFTRESET", 1, 1 },
|
|
{ "MACROTEST", 0, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x37b00, 0 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x37b04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x37b08, 0 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x37b0c, 0 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x37b10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "MAC_PORT_PLLA_POWER_CONTROL", 0x37b24, 0 },
|
|
{ "SPWRENA", 1, 1 },
|
|
{ "NPWRENA", 0, 1 },
|
|
{ "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x37b28, 0 },
|
|
{ "MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL", 0x37b38, 0 },
|
|
{ "MAC_PORT_PLLA_PCLK_CONTROL", 0x37b3c, 0 },
|
|
{ "SPEDIV", 3, 5 },
|
|
{ "PCKSEL", 0, 3 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x37b40, 0 },
|
|
{ "EMIL", 2, 1 },
|
|
{ "EMID", 1, 1 },
|
|
{ "EMIS", 0, 1 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x37b44, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x37b48, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x37b4c, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x37b50, 0 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x37bf0, 0 },
|
|
{ "PLLDIVA", 4, 1 },
|
|
{ "REFDIV", 0, 4 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x37bf4, 0 },
|
|
{ "RESYNC", 6, 1 },
|
|
{ "RXCLKSEL", 5, 1 },
|
|
{ "FRCBAND", 4, 1 },
|
|
{ "PLLBYP", 3, 1 },
|
|
{ "VCOSEL", 1, 1 },
|
|
{ "DIVSEL8", 0, 1 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x37bf8, 0 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x37bfc, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x37c00, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x37c04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x37c08, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x37c0c, 0 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x37c10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "MAC_PORT_PLLB_POWER_CONTROL", 0x37c24, 0 },
|
|
{ "SPWRENA", 1, 1 },
|
|
{ "NPWRENA", 0, 1 },
|
|
{ "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x37c28, 0 },
|
|
{ "MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL", 0x37c38, 0 },
|
|
{ "MAC_PORT_PLLB_PCLK_CONTROL", 0x37c3c, 0 },
|
|
{ "SPEDIV", 3, 5 },
|
|
{ "PCKSEL", 0, 3 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x37c40, 0 },
|
|
{ "EMIL", 2, 1 },
|
|
{ "EMID", 1, 1 },
|
|
{ "EMIS", 0, 1 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x37c44, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x37c48, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x37c4c, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x37c50, 0 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x37cf0, 0 },
|
|
{ "PLLDIVA", 4, 1 },
|
|
{ "REFDIV", 0, 4 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x37cf4, 0 },
|
|
{ "RESYNC", 6, 1 },
|
|
{ "RXCLKSEL", 5, 1 },
|
|
{ "FRCBAND", 4, 1 },
|
|
{ "PLLBYP", 3, 1 },
|
|
{ "VCOSEL", 1, 1 },
|
|
{ "DIVSEL8", 0, 1 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x37cf8, 0 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x37cfc, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x37000, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_RXLOOP", 5, 1 },
|
|
{ "T5_TX_ENFFE4", 4, 1 },
|
|
{ "T5_TX_BWSEL", 2, 2 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x37004, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "FRCERR", 10, 1 },
|
|
{ "ERROR", 9, 1 },
|
|
{ "SYNC", 8, 1 },
|
|
{ "P7CHK", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x37008, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "SASMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3700c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37010, 0 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37014, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37018, 0 },
|
|
{ "CALSSTN", 8, 6 },
|
|
{ "CALSSTP", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3701c, 0 },
|
|
{ "DRTOL", 2, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x37020, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x37024, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x37028, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT", 0x3702c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x37034, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37038, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "SASCMD", 10, 2 },
|
|
{ "C0UPDT", 6, 2 },
|
|
{ "C3UPDT", 4, 2 },
|
|
{ "C2UPDT", 2, 2 },
|
|
{ "C1UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3703c, 0 },
|
|
{ "C0STAT", 6, 2 },
|
|
{ "C3STAT", 4, 2 },
|
|
{ "C2STAT", 2, 2 },
|
|
{ "C1STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37040, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37044, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37048, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3704c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37050, 0 },
|
|
{ "ATUNEN", 8, 8 },
|
|
{ "ATUNEP", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37058, 0 },
|
|
{ "DCCCOMPINV", 8, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED", 0x37060, 0 },
|
|
{ "AS4X7", 14, 2 },
|
|
{ "AS4X6", 12, 2 },
|
|
{ "AS4X5", 10, 2 },
|
|
{ "AS4X4", 8, 2 },
|
|
{ "AS4X3", 6, 2 },
|
|
{ "AS4X2", 4, 2 },
|
|
{ "AS4X1", 2, 2 },
|
|
{ "AS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED", 0x37064, 0 },
|
|
{ "AS2X3", 6, 2 },
|
|
{ "AS2X2", 4, 2 },
|
|
{ "AS2X1", 2, 2 },
|
|
{ "AS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED", 0x37068, 0 },
|
|
{ "AS1X7", 14, 2 },
|
|
{ "AS1X6", 12, 2 },
|
|
{ "AS1X5", 10, 2 },
|
|
{ "AS1X4", 8, 2 },
|
|
{ "AS1X3", 6, 2 },
|
|
{ "AS1X2", 4, 2 },
|
|
{ "AS1X1", 2, 2 },
|
|
{ "AS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3706c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37070, 0 },
|
|
{ "AT2X", 8, 4 },
|
|
{ "AT4X", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37074, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37078, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3707c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37080, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37084, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37088, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3708c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3709c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x370a0, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 13, 2 },
|
|
{ "DCCLOCK", 11, 2 },
|
|
{ "DCCOFFSET", 8, 3 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x370a4, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x370a8, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x370ac, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE", 0x370c0, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x370c8, 0 },
|
|
{ "OS4X7", 14, 2 },
|
|
{ "OS4X6", 12, 2 },
|
|
{ "OS4X5", 10, 2 },
|
|
{ "OS4X4", 8, 2 },
|
|
{ "OS4X3", 6, 2 },
|
|
{ "OS4X2", 4, 2 },
|
|
{ "OS4X1", 2, 2 },
|
|
{ "OS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x370cc, 0 },
|
|
{ "OS2X3", 6, 2 },
|
|
{ "OS2X2", 4, 2 },
|
|
{ "OS2X1", 2, 2 },
|
|
{ "OS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x370d0, 0 },
|
|
{ "OS1X7", 14, 2 },
|
|
{ "OS1X6", 12, 2 },
|
|
{ "OS1X5", 10, 2 },
|
|
{ "OS1X4", 8, 2 },
|
|
{ "OS1X3", 6, 2 },
|
|
{ "OS1X2", 4, 2 },
|
|
{ "OS1X1", 2, 2 },
|
|
{ "OS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x370d8, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x370dc, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x370e0, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5", 0x370ec, 0 },
|
|
{ "ERRORP", 15, 1 },
|
|
{ "ERRORN", 14, 1 },
|
|
{ "TESTENA", 13, 1 },
|
|
{ "TUNEBIT", 10, 3 },
|
|
{ "DATAPOS", 8, 2 },
|
|
{ "SEGSEL", 3, 5 },
|
|
{ "TAPSEL", 1, 2 },
|
|
{ "DATASIGN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x370f0, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x370f4, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x370f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x370fc, 0 },
|
|
{ "SDOVRDEN", 15, 1 },
|
|
{ "BSOUTN", 7, 1 },
|
|
{ "BSOUTP", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x37100, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_RXLOOP", 5, 1 },
|
|
{ "T5_TX_ENFFE4", 4, 1 },
|
|
{ "T5_TX_BWSEL", 2, 2 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x37104, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "FRCERR", 10, 1 },
|
|
{ "ERROR", 9, 1 },
|
|
{ "SYNC", 8, 1 },
|
|
{ "P7CHK", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x37108, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "SASMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3710c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37110, 0 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37114, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37118, 0 },
|
|
{ "CALSSTN", 8, 6 },
|
|
{ "CALSSTP", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3711c, 0 },
|
|
{ "DRTOL", 2, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x37120, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x37124, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x37128, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT", 0x3712c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x37134, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37138, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "SASCMD", 10, 2 },
|
|
{ "C0UPDT", 6, 2 },
|
|
{ "C3UPDT", 4, 2 },
|
|
{ "C2UPDT", 2, 2 },
|
|
{ "C1UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3713c, 0 },
|
|
{ "C0STAT", 6, 2 },
|
|
{ "C3STAT", 4, 2 },
|
|
{ "C2STAT", 2, 2 },
|
|
{ "C1STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37140, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37144, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37148, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3714c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37150, 0 },
|
|
{ "ATUNEN", 8, 8 },
|
|
{ "ATUNEP", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37158, 0 },
|
|
{ "DCCCOMPINV", 8, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED", 0x37160, 0 },
|
|
{ "AS4X7", 14, 2 },
|
|
{ "AS4X6", 12, 2 },
|
|
{ "AS4X5", 10, 2 },
|
|
{ "AS4X4", 8, 2 },
|
|
{ "AS4X3", 6, 2 },
|
|
{ "AS4X2", 4, 2 },
|
|
{ "AS4X1", 2, 2 },
|
|
{ "AS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED", 0x37164, 0 },
|
|
{ "AS2X3", 6, 2 },
|
|
{ "AS2X2", 4, 2 },
|
|
{ "AS2X1", 2, 2 },
|
|
{ "AS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED", 0x37168, 0 },
|
|
{ "AS1X7", 14, 2 },
|
|
{ "AS1X6", 12, 2 },
|
|
{ "AS1X5", 10, 2 },
|
|
{ "AS1X4", 8, 2 },
|
|
{ "AS1X3", 6, 2 },
|
|
{ "AS1X2", 4, 2 },
|
|
{ "AS1X1", 2, 2 },
|
|
{ "AS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3716c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37170, 0 },
|
|
{ "AT2X", 8, 4 },
|
|
{ "AT4X", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37174, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37178, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3717c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37180, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37184, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37188, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3718c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3719c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x371a0, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 13, 2 },
|
|
{ "DCCLOCK", 11, 2 },
|
|
{ "DCCOFFSET", 8, 3 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x371a4, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x371a8, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x371ac, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE", 0x371c0, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x371c8, 0 },
|
|
{ "OS4X7", 14, 2 },
|
|
{ "OS4X6", 12, 2 },
|
|
{ "OS4X5", 10, 2 },
|
|
{ "OS4X4", 8, 2 },
|
|
{ "OS4X3", 6, 2 },
|
|
{ "OS4X2", 4, 2 },
|
|
{ "OS4X1", 2, 2 },
|
|
{ "OS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x371cc, 0 },
|
|
{ "OS2X3", 6, 2 },
|
|
{ "OS2X2", 4, 2 },
|
|
{ "OS2X1", 2, 2 },
|
|
{ "OS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x371d0, 0 },
|
|
{ "OS1X7", 14, 2 },
|
|
{ "OS1X6", 12, 2 },
|
|
{ "OS1X5", 10, 2 },
|
|
{ "OS1X4", 8, 2 },
|
|
{ "OS1X3", 6, 2 },
|
|
{ "OS1X2", 4, 2 },
|
|
{ "OS1X1", 2, 2 },
|
|
{ "OS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x371d8, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x371dc, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x371e0, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5", 0x371ec, 0 },
|
|
{ "ERRORP", 15, 1 },
|
|
{ "ERRORN", 14, 1 },
|
|
{ "TESTENA", 13, 1 },
|
|
{ "TUNEBIT", 10, 3 },
|
|
{ "DATAPOS", 8, 2 },
|
|
{ "SEGSEL", 3, 5 },
|
|
{ "TAPSEL", 1, 2 },
|
|
{ "DATASIGN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x371f0, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x371f4, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x371f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x371fc, 0 },
|
|
{ "SDOVRDEN", 15, 1 },
|
|
{ "BSOUTN", 7, 1 },
|
|
{ "BSOUTP", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x37400, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_RXLOOP", 5, 1 },
|
|
{ "T5_TX_ENFFE4", 4, 1 },
|
|
{ "T5_TX_BWSEL", 2, 2 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x37404, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "FRCERR", 10, 1 },
|
|
{ "ERROR", 9, 1 },
|
|
{ "SYNC", 8, 1 },
|
|
{ "P7CHK", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x37408, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "SASMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3740c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37410, 0 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37414, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37418, 0 },
|
|
{ "CALSSTN", 8, 6 },
|
|
{ "CALSSTP", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3741c, 0 },
|
|
{ "DRTOL", 2, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x37420, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x37424, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x37428, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT", 0x3742c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x37434, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37438, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "SASCMD", 10, 2 },
|
|
{ "C0UPDT", 6, 2 },
|
|
{ "C3UPDT", 4, 2 },
|
|
{ "C2UPDT", 2, 2 },
|
|
{ "C1UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3743c, 0 },
|
|
{ "C0STAT", 6, 2 },
|
|
{ "C3STAT", 4, 2 },
|
|
{ "C2STAT", 2, 2 },
|
|
{ "C1STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37440, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37444, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37448, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3744c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37450, 0 },
|
|
{ "ATUNEN", 8, 8 },
|
|
{ "ATUNEP", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37458, 0 },
|
|
{ "DCCCOMPINV", 8, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED", 0x37460, 0 },
|
|
{ "AS4X7", 14, 2 },
|
|
{ "AS4X6", 12, 2 },
|
|
{ "AS4X5", 10, 2 },
|
|
{ "AS4X4", 8, 2 },
|
|
{ "AS4X3", 6, 2 },
|
|
{ "AS4X2", 4, 2 },
|
|
{ "AS4X1", 2, 2 },
|
|
{ "AS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED", 0x37464, 0 },
|
|
{ "AS2X3", 6, 2 },
|
|
{ "AS2X2", 4, 2 },
|
|
{ "AS2X1", 2, 2 },
|
|
{ "AS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED", 0x37468, 0 },
|
|
{ "AS1X7", 14, 2 },
|
|
{ "AS1X6", 12, 2 },
|
|
{ "AS1X5", 10, 2 },
|
|
{ "AS1X4", 8, 2 },
|
|
{ "AS1X3", 6, 2 },
|
|
{ "AS1X2", 4, 2 },
|
|
{ "AS1X1", 2, 2 },
|
|
{ "AS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3746c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37470, 0 },
|
|
{ "AT2X", 8, 4 },
|
|
{ "AT4X", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37474, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37478, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3747c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37480, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37484, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37488, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3748c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3749c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x374a0, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 13, 2 },
|
|
{ "DCCLOCK", 11, 2 },
|
|
{ "DCCOFFSET", 8, 3 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x374a4, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x374a8, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x374ac, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE", 0x374c0, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x374c8, 0 },
|
|
{ "OS4X7", 14, 2 },
|
|
{ "OS4X6", 12, 2 },
|
|
{ "OS4X5", 10, 2 },
|
|
{ "OS4X4", 8, 2 },
|
|
{ "OS4X3", 6, 2 },
|
|
{ "OS4X2", 4, 2 },
|
|
{ "OS4X1", 2, 2 },
|
|
{ "OS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x374cc, 0 },
|
|
{ "OS2X3", 6, 2 },
|
|
{ "OS2X2", 4, 2 },
|
|
{ "OS2X1", 2, 2 },
|
|
{ "OS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x374d0, 0 },
|
|
{ "OS1X7", 14, 2 },
|
|
{ "OS1X6", 12, 2 },
|
|
{ "OS1X5", 10, 2 },
|
|
{ "OS1X4", 8, 2 },
|
|
{ "OS1X3", 6, 2 },
|
|
{ "OS1X2", 4, 2 },
|
|
{ "OS1X1", 2, 2 },
|
|
{ "OS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x374d8, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x374dc, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x374e0, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5", 0x374ec, 0 },
|
|
{ "ERRORP", 15, 1 },
|
|
{ "ERRORN", 14, 1 },
|
|
{ "TESTENA", 13, 1 },
|
|
{ "TUNEBIT", 10, 3 },
|
|
{ "DATAPOS", 8, 2 },
|
|
{ "SEGSEL", 3, 5 },
|
|
{ "TAPSEL", 1, 2 },
|
|
{ "DATASIGN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x374f0, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x374f4, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x374f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x374fc, 0 },
|
|
{ "SDOVRDEN", 15, 1 },
|
|
{ "BSOUTN", 7, 1 },
|
|
{ "BSOUTP", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x37500, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_RXLOOP", 5, 1 },
|
|
{ "T5_TX_ENFFE4", 4, 1 },
|
|
{ "T5_TX_BWSEL", 2, 2 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x37504, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "FRCERR", 10, 1 },
|
|
{ "ERROR", 9, 1 },
|
|
{ "SYNC", 8, 1 },
|
|
{ "P7CHK", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x37508, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "SASMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3750c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37510, 0 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37514, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37518, 0 },
|
|
{ "CALSSTN", 8, 6 },
|
|
{ "CALSSTP", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3751c, 0 },
|
|
{ "DRTOL", 2, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x37520, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x37524, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x37528, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT", 0x3752c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x37534, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37538, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "SASCMD", 10, 2 },
|
|
{ "C0UPDT", 6, 2 },
|
|
{ "C3UPDT", 4, 2 },
|
|
{ "C2UPDT", 2, 2 },
|
|
{ "C1UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3753c, 0 },
|
|
{ "C0STAT", 6, 2 },
|
|
{ "C3STAT", 4, 2 },
|
|
{ "C2STAT", 2, 2 },
|
|
{ "C1STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37540, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37544, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37548, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3754c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37550, 0 },
|
|
{ "ATUNEN", 8, 8 },
|
|
{ "ATUNEP", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37558, 0 },
|
|
{ "DCCCOMPINV", 8, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED", 0x37560, 0 },
|
|
{ "AS4X7", 14, 2 },
|
|
{ "AS4X6", 12, 2 },
|
|
{ "AS4X5", 10, 2 },
|
|
{ "AS4X4", 8, 2 },
|
|
{ "AS4X3", 6, 2 },
|
|
{ "AS4X2", 4, 2 },
|
|
{ "AS4X1", 2, 2 },
|
|
{ "AS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED", 0x37564, 0 },
|
|
{ "AS2X3", 6, 2 },
|
|
{ "AS2X2", 4, 2 },
|
|
{ "AS2X1", 2, 2 },
|
|
{ "AS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED", 0x37568, 0 },
|
|
{ "AS1X7", 14, 2 },
|
|
{ "AS1X6", 12, 2 },
|
|
{ "AS1X5", 10, 2 },
|
|
{ "AS1X4", 8, 2 },
|
|
{ "AS1X3", 6, 2 },
|
|
{ "AS1X2", 4, 2 },
|
|
{ "AS1X1", 2, 2 },
|
|
{ "AS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3756c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37570, 0 },
|
|
{ "AT2X", 8, 4 },
|
|
{ "AT4X", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37574, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37578, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3757c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37580, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37584, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37588, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3758c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3759c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x375a0, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 13, 2 },
|
|
{ "DCCLOCK", 11, 2 },
|
|
{ "DCCOFFSET", 8, 3 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x375a4, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x375a8, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x375ac, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE", 0x375c0, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x375c8, 0 },
|
|
{ "OS4X7", 14, 2 },
|
|
{ "OS4X6", 12, 2 },
|
|
{ "OS4X5", 10, 2 },
|
|
{ "OS4X4", 8, 2 },
|
|
{ "OS4X3", 6, 2 },
|
|
{ "OS4X2", 4, 2 },
|
|
{ "OS4X1", 2, 2 },
|
|
{ "OS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x375cc, 0 },
|
|
{ "OS2X3", 6, 2 },
|
|
{ "OS2X2", 4, 2 },
|
|
{ "OS2X1", 2, 2 },
|
|
{ "OS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x375d0, 0 },
|
|
{ "OS1X7", 14, 2 },
|
|
{ "OS1X6", 12, 2 },
|
|
{ "OS1X5", 10, 2 },
|
|
{ "OS1X4", 8, 2 },
|
|
{ "OS1X3", 6, 2 },
|
|
{ "OS1X2", 4, 2 },
|
|
{ "OS1X1", 2, 2 },
|
|
{ "OS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x375d8, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x375dc, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x375e0, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5", 0x375ec, 0 },
|
|
{ "ERRORP", 15, 1 },
|
|
{ "ERRORN", 14, 1 },
|
|
{ "TESTENA", 13, 1 },
|
|
{ "TUNEBIT", 10, 3 },
|
|
{ "DATAPOS", 8, 2 },
|
|
{ "SEGSEL", 3, 5 },
|
|
{ "TAPSEL", 1, 2 },
|
|
{ "DATASIGN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x375f0, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x375f4, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x375f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x375fc, 0 },
|
|
{ "SDOVRDEN", 15, 1 },
|
|
{ "BSOUTN", 7, 1 },
|
|
{ "BSOUTP", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x37900, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_RXLOOP", 5, 1 },
|
|
{ "T5_TX_ENFFE4", 4, 1 },
|
|
{ "T5_TX_BWSEL", 2, 2 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x37904, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "FRCERR", 10, 1 },
|
|
{ "ERROR", 9, 1 },
|
|
{ "SYNC", 8, 1 },
|
|
{ "P7CHK", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x37908, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "SASMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3790c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37910, 0 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37914, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37918, 0 },
|
|
{ "CALSSTN", 8, 6 },
|
|
{ "CALSSTP", 0, 6 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3791c, 0 },
|
|
{ "DRTOL", 2, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x37920, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x37924, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x37928, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT", 0x3792c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x37934, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37938, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "SASCMD", 10, 2 },
|
|
{ "C0UPDT", 6, 2 },
|
|
{ "C3UPDT", 4, 2 },
|
|
{ "C2UPDT", 2, 2 },
|
|
{ "C1UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3793c, 0 },
|
|
{ "C0STAT", 6, 2 },
|
|
{ "C3STAT", 4, 2 },
|
|
{ "C2STAT", 2, 2 },
|
|
{ "C1STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37940, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37944, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37948, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3794c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37950, 0 },
|
|
{ "ATUNEN", 8, 8 },
|
|
{ "ATUNEP", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37958, 0 },
|
|
{ "DCCCOMPINV", 8, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED", 0x37960, 0 },
|
|
{ "AS4X7", 14, 2 },
|
|
{ "AS4X6", 12, 2 },
|
|
{ "AS4X5", 10, 2 },
|
|
{ "AS4X4", 8, 2 },
|
|
{ "AS4X3", 6, 2 },
|
|
{ "AS4X2", 4, 2 },
|
|
{ "AS4X1", 2, 2 },
|
|
{ "AS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED", 0x37964, 0 },
|
|
{ "AS2X3", 6, 2 },
|
|
{ "AS2X2", 4, 2 },
|
|
{ "AS2X1", 2, 2 },
|
|
{ "AS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED", 0x37968, 0 },
|
|
{ "AS1X7", 14, 2 },
|
|
{ "AS1X6", 12, 2 },
|
|
{ "AS1X5", 10, 2 },
|
|
{ "AS1X4", 8, 2 },
|
|
{ "AS1X3", 6, 2 },
|
|
{ "AS1X2", 4, 2 },
|
|
{ "AS1X1", 2, 2 },
|
|
{ "AS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3796c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37970, 0 },
|
|
{ "AT2X", 8, 4 },
|
|
{ "AT4X", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37974, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37978, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3797c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37980, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37984, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37988, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3798c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3799c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x379a0, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 13, 2 },
|
|
{ "DCCLOCK", 11, 2 },
|
|
{ "DCCOFFSET", 8, 3 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x379a4, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x379a8, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x379ac, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE", 0x379c0, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x379c8, 0 },
|
|
{ "OS4X7", 14, 2 },
|
|
{ "OS4X6", 12, 2 },
|
|
{ "OS4X5", 10, 2 },
|
|
{ "OS4X4", 8, 2 },
|
|
{ "OS4X3", 6, 2 },
|
|
{ "OS4X2", 4, 2 },
|
|
{ "OS4X1", 2, 2 },
|
|
{ "OS4X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x379cc, 0 },
|
|
{ "OS2X3", 6, 2 },
|
|
{ "OS2X2", 4, 2 },
|
|
{ "OS2X1", 2, 2 },
|
|
{ "OS2X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x379d0, 0 },
|
|
{ "OS1X7", 14, 2 },
|
|
{ "OS1X6", 12, 2 },
|
|
{ "OS1X5", 10, 2 },
|
|
{ "OS1X4", 8, 2 },
|
|
{ "OS1X3", 6, 2 },
|
|
{ "OS1X2", 4, 2 },
|
|
{ "OS1X1", 2, 2 },
|
|
{ "OS1X0", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x379d8, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x379dc, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x379e0, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5", 0x379ec, 0 },
|
|
{ "ERRORP", 15, 1 },
|
|
{ "ERRORN", 14, 1 },
|
|
{ "TESTENA", 13, 1 },
|
|
{ "TUNEBIT", 10, 3 },
|
|
{ "DATAPOS", 8, 2 },
|
|
{ "SEGSEL", 3, 5 },
|
|
{ "TAPSEL", 1, 2 },
|
|
{ "DATASIGN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x379f0, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x379f4, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x379f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x379fc, 0 },
|
|
{ "SDOVRDEN", 15, 1 },
|
|
{ "BSOUTN", 7, 1 },
|
|
{ "BSOUTP", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x37200, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_MODE8023AZ", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x37204, 0 },
|
|
{ "APLYDCD", 15, 1 },
|
|
{ "PPOL", 13, 2 },
|
|
{ "PCLKSEL", 11, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x37208, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3720c, 0 },
|
|
{ "H1ANOFST", 12, 4 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "TMSCAL", 8, 2 },
|
|
{ "APADJ", 7, 1 },
|
|
{ "RSEL", 6, 1 },
|
|
{ "PHOFFS", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x37210, 0 },
|
|
{ "ROTA", 8, 6 },
|
|
{ "ROTD", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x37214, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROTE", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37218, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOFFF", 8, 4 },
|
|
{ "RAOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3721c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x37220, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 8, 4 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x37224, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x37228, 0 },
|
|
{ "REQWOV", 15, 1 },
|
|
{ "RASEL", 11, 3 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3722c, 0 },
|
|
{ "WRAPSEL", 15, 1 },
|
|
{ "ACTL", 14, 1 },
|
|
{ "PEAK", 9, 5 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x37230, 0 },
|
|
{ "FVOFFSKP", 15, 1 },
|
|
{ "FGAINCHK", 14, 1 },
|
|
{ "FH1ACAL", 13, 1 },
|
|
{ "FH1AFLTR", 11, 2 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "WGAIN", 8, 2 },
|
|
{ "GAIN_STAT", 7, 1 },
|
|
{ "T5VGAIN", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x37234, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37238, 0 },
|
|
{ "PMCFG", 6, 2 },
|
|
{ "PMOFFTIME", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1", 0x3723c, 0 },
|
|
{ "SELI", 9, 1 },
|
|
{ "SERVREF", 5, 3 },
|
|
{ "IQAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2", 0x37240, 0 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37244, 0 },
|
|
{ "SAVEADAC", 8, 1 },
|
|
{ "LOAD2", 7, 1 },
|
|
{ "LOAD1", 6, 1 },
|
|
{ "WRTACC2", 5, 1 },
|
|
{ "WRTACC1", 4, 1 },
|
|
{ "SELAPAN", 3, 1 },
|
|
{ "DASEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x37248, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN", 0x3724c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x37250, 0 },
|
|
{ "ADAC2", 8, 8 },
|
|
{ "ADAC1", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL", 0x37254, 0 },
|
|
{ "FACCPLDYN", 13, 1 },
|
|
{ "ACCPLGAIN", 10, 3 },
|
|
{ "ACCPLREF", 8, 2 },
|
|
{ "ACCPLSTEP", 6, 2 },
|
|
{ "ACCPLASTEP", 1, 5 },
|
|
{ "FACCPL", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE", 0x37258, 0 },
|
|
{ "ACCPLMEANS", 15, 1 },
|
|
{ "CDROVREN", 8, 1 },
|
|
{ "ACCPLBIAS", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET", 0x3725c, 0 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37260, 0 },
|
|
{ "H1OX", 8, 6 },
|
|
{ "H1EX", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR", 0x37264, 0 },
|
|
{ "PILOCK", 10, 1 },
|
|
{ "UNPKPKA", 2, 6 },
|
|
{ "UNPKVGA", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH", 0x37268, 0 },
|
|
{ "OVRAC", 15, 1 },
|
|
{ "OVRPK", 14, 1 },
|
|
{ "OVRTAILS", 12, 2 },
|
|
{ "OVRTAILV", 9, 3 },
|
|
{ "OVRCAP", 8, 1 },
|
|
{ "OVRDCDPRE", 7, 1 },
|
|
{ "OVRDCDPST", 6, 1 },
|
|
{ "DCVSCTMODE", 2, 1 },
|
|
{ "CDRANLGSW", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3726c, 0 },
|
|
{ "PFLAG", 5, 2 },
|
|
{ "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37270, 0 },
|
|
{ "DACCLIP", 15, 1 },
|
|
{ "DPCFRZ", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCLKNQ", 11, 1 },
|
|
{ "DPCWDFE", 10, 1 },
|
|
{ "DPCWPK", 9, 1 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x37274, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "VIEWSCAN", 4, 1 },
|
|
{ "ODEC", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x37278, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "ACCCMP", 11, 1 },
|
|
{ "DCCCMP", 10, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5IQCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3727c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x37280, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FDCCAL", 14, 1 },
|
|
{ "FROTCAL", 13, 1 },
|
|
{ "FIQAMP", 12, 1 },
|
|
{ "FRPTCALF", 11, 1 },
|
|
{ "FINTCALGS", 10, 1 },
|
|
{ "FDCC", 9, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FDCD", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FINTRCALDYN", 1, 1 },
|
|
{ "FQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL", 0x37284, 0 },
|
|
{ "QCCIND", 13, 1 },
|
|
{ "DCDIND", 10, 3 },
|
|
{ "DCCIND", 8, 2 },
|
|
{ "CFSEL", 5, 1 },
|
|
{ "LOFCH", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE", 0x37288, 0 },
|
|
{ "LOFU", 8, 7 },
|
|
{ "LOFL", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST", 0x3728c, 0 },
|
|
{ "HBISTMAN", 12, 1 },
|
|
{ "HBISTRES", 11, 1 },
|
|
{ "HBISTSP", 8, 3 },
|
|
{ "HBISTEN", 7, 1 },
|
|
{ "HBISTRST", 6, 1 },
|
|
{ "HCOMP", 5, 1 },
|
|
{ "HPASS", 4, 1 },
|
|
{ "HSEL", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST", 0x37290, 0 },
|
|
{ "ACCCMP", 13, 1 },
|
|
{ "ACCEN", 12, 1 },
|
|
{ "ACCRST", 11, 1 },
|
|
{ "ACCIND", 8, 3 },
|
|
{ "ACCRD", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER", 0x37298, 0 },
|
|
{ "LFREG", 15, 1 },
|
|
{ "LFRC", 14, 1 },
|
|
{ "LGIDLE", 13, 1 },
|
|
{ "LFTGT", 8, 5 },
|
|
{ "LGTGT", 7, 1 },
|
|
{ "LRDY", 6, 1 },
|
|
{ "LIDLE", 5, 1 },
|
|
{ "LCURR", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3729c, 0 },
|
|
{ "OFFSN", 13, 2 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x372a0, 0 },
|
|
{ "RX_OVRSUMPD", 15, 1 },
|
|
{ "RX_OVRKBPD", 14, 1 },
|
|
{ "RX_OVRDIVPD", 13, 1 },
|
|
{ "RX_OFFVGADIS", 12, 1 },
|
|
{ "RX_OFFACDIS", 11, 1 },
|
|
{ "RX_VTERM", 10, 1 },
|
|
{ "RX_DISSPY2D", 8, 1 },
|
|
{ "RX_OBSOVEN", 7, 1 },
|
|
{ "RX_LINKANLGSW", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x372a4, 0 },
|
|
{ "INTDACEGS", 13, 3 },
|
|
{ "INTDACE", 8, 5 },
|
|
{ "INTDACGS", 6, 2 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x372a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x372ac, 0 },
|
|
{ "SMQM", 13, 3 },
|
|
{ "SMQ", 5, 8 },
|
|
{ "EMMD", 3, 2 },
|
|
{ "EMBRDY", 2, 1 },
|
|
{ "EMBUMP", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x372b0, 0 },
|
|
{ "EMSF", 13, 1 },
|
|
{ "EMDATA59", 12, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x372b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x372b8, 0 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3", 0x372bc, 0 },
|
|
{ "FTIMEOUT", 15, 1 },
|
|
{ "FROTCAL4", 14, 1 },
|
|
{ "FDCD2", 13, 1 },
|
|
{ "FPRBSPOLTOG", 12, 1 },
|
|
{ "FPRBSOFF2", 11, 1 },
|
|
{ "FDDCAL2", 10, 1 },
|
|
{ "FDDCFLTR", 9, 1 },
|
|
{ "FDAC6", 8, 1 },
|
|
{ "FDDC5", 7, 1 },
|
|
{ "FDDC3456", 6, 1 },
|
|
{ "FSPY2DATA", 5, 1 },
|
|
{ "FPHSLOCK", 4, 1 },
|
|
{ "FCLKALGN", 3, 1 },
|
|
{ "FCLKALDYN", 2, 1 },
|
|
{ "FDFE", 1, 1 },
|
|
{ "FPRBSOFF", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_TAP_CONTROL", 0x372c0, 0 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_TAP", 0x372c4, 0 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2", 0x372e4, 0 },
|
|
{ "STNDBYSTAT", 15, 1 },
|
|
{ "CALSDONE", 14, 1 },
|
|
{ "ACISRCCMP", 5, 1 },
|
|
{ "PRBSOFFCMP", 4, 1 },
|
|
{ "CLKALGNCMP", 3, 1 },
|
|
{ "ROTFCMP", 2, 1 },
|
|
{ "DCDCMP", 1, 1 },
|
|
{ "QCCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x372e8, 0 },
|
|
{ "FCSADJ", 6, 1 },
|
|
{ "CSIND", 3, 2 },
|
|
{ "CSVAL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL", 0x372ec, 0 },
|
|
{ "DCDTMDOUT", 15, 1 },
|
|
{ "DCDTOEN", 14, 1 },
|
|
{ "DCDLOCK", 13, 1 },
|
|
{ "DCDSTEP", 11, 2 },
|
|
{ "DCDALTWPDIS", 10, 1 },
|
|
{ "DCDOVRDEN", 9, 1 },
|
|
{ "DCCAOVRDEN", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL", 0x372f0, 0 },
|
|
{ "PRBSMODE", 14, 2 },
|
|
{ "DCCSTEP", 10, 2 },
|
|
{ "DCCOVRDEN", 9, 1 },
|
|
{ "DCCLOCK", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL", 0x372f4, 0 },
|
|
{ "DCCQCCMODE", 15, 1 },
|
|
{ "DCCQCCDYN", 14, 1 },
|
|
{ "DCCQCCHOLD", 13, 1 },
|
|
{ "QCCSTEP", 10, 2 },
|
|
{ "QCCOVRDEN", 9, 1 },
|
|
{ "QCCLOCK", 8, 1 },
|
|
{ "QCCSIGN", 6, 2 },
|
|
{ "QCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x372f8, 0 },
|
|
{ "TSTCMP", 15, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x372fc, 0 },
|
|
{ "CALMODEEDGE", 14, 1 },
|
|
{ "TESTCAP", 13, 1 },
|
|
{ "SNAPEN", 12, 1 },
|
|
{ "ASYNCDIR", 11, 1 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x37300, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_MODE8023AZ", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x37304, 0 },
|
|
{ "APLYDCD", 15, 1 },
|
|
{ "PPOL", 13, 2 },
|
|
{ "PCLKSEL", 11, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x37308, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3730c, 0 },
|
|
{ "H1ANOFST", 12, 4 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "TMSCAL", 8, 2 },
|
|
{ "APADJ", 7, 1 },
|
|
{ "RSEL", 6, 1 },
|
|
{ "PHOFFS", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x37310, 0 },
|
|
{ "ROTA", 8, 6 },
|
|
{ "ROTD", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x37314, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROTE", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37318, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOFFF", 8, 4 },
|
|
{ "RAOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3731c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x37320, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 8, 4 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x37324, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x37328, 0 },
|
|
{ "REQWOV", 15, 1 },
|
|
{ "RASEL", 11, 3 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3732c, 0 },
|
|
{ "WRAPSEL", 15, 1 },
|
|
{ "ACTL", 14, 1 },
|
|
{ "PEAK", 9, 5 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x37330, 0 },
|
|
{ "FVOFFSKP", 15, 1 },
|
|
{ "FGAINCHK", 14, 1 },
|
|
{ "FH1ACAL", 13, 1 },
|
|
{ "FH1AFLTR", 11, 2 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "WGAIN", 8, 2 },
|
|
{ "GAIN_STAT", 7, 1 },
|
|
{ "T5VGAIN", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x37334, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37338, 0 },
|
|
{ "PMCFG", 6, 2 },
|
|
{ "PMOFFTIME", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1", 0x3733c, 0 },
|
|
{ "SELI", 9, 1 },
|
|
{ "SERVREF", 5, 3 },
|
|
{ "IQAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2", 0x37340, 0 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37344, 0 },
|
|
{ "SAVEADAC", 8, 1 },
|
|
{ "LOAD2", 7, 1 },
|
|
{ "LOAD1", 6, 1 },
|
|
{ "WRTACC2", 5, 1 },
|
|
{ "WRTACC1", 4, 1 },
|
|
{ "SELAPAN", 3, 1 },
|
|
{ "DASEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x37348, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN", 0x3734c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x37350, 0 },
|
|
{ "ADAC2", 8, 8 },
|
|
{ "ADAC1", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL", 0x37354, 0 },
|
|
{ "FACCPLDYN", 13, 1 },
|
|
{ "ACCPLGAIN", 10, 3 },
|
|
{ "ACCPLREF", 8, 2 },
|
|
{ "ACCPLSTEP", 6, 2 },
|
|
{ "ACCPLASTEP", 1, 5 },
|
|
{ "FACCPL", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE", 0x37358, 0 },
|
|
{ "ACCPLMEANS", 15, 1 },
|
|
{ "CDROVREN", 8, 1 },
|
|
{ "ACCPLBIAS", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET", 0x3735c, 0 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37360, 0 },
|
|
{ "H1OX", 8, 6 },
|
|
{ "H1EX", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR", 0x37364, 0 },
|
|
{ "PILOCK", 10, 1 },
|
|
{ "UNPKPKA", 2, 6 },
|
|
{ "UNPKVGA", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH", 0x37368, 0 },
|
|
{ "OVRAC", 15, 1 },
|
|
{ "OVRPK", 14, 1 },
|
|
{ "OVRTAILS", 12, 2 },
|
|
{ "OVRTAILV", 9, 3 },
|
|
{ "OVRCAP", 8, 1 },
|
|
{ "OVRDCDPRE", 7, 1 },
|
|
{ "OVRDCDPST", 6, 1 },
|
|
{ "DCVSCTMODE", 2, 1 },
|
|
{ "CDRANLGSW", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3736c, 0 },
|
|
{ "PFLAG", 5, 2 },
|
|
{ "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37370, 0 },
|
|
{ "DACCLIP", 15, 1 },
|
|
{ "DPCFRZ", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCLKNQ", 11, 1 },
|
|
{ "DPCWDFE", 10, 1 },
|
|
{ "DPCWPK", 9, 1 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x37374, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "VIEWSCAN", 4, 1 },
|
|
{ "ODEC", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x37378, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "ACCCMP", 11, 1 },
|
|
{ "DCCCMP", 10, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5IQCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3737c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x37380, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FDCCAL", 14, 1 },
|
|
{ "FROTCAL", 13, 1 },
|
|
{ "FIQAMP", 12, 1 },
|
|
{ "FRPTCALF", 11, 1 },
|
|
{ "FINTCALGS", 10, 1 },
|
|
{ "FDCC", 9, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FDCD", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FINTRCALDYN", 1, 1 },
|
|
{ "FQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL", 0x37384, 0 },
|
|
{ "QCCIND", 13, 1 },
|
|
{ "DCDIND", 10, 3 },
|
|
{ "DCCIND", 8, 2 },
|
|
{ "CFSEL", 5, 1 },
|
|
{ "LOFCH", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE", 0x37388, 0 },
|
|
{ "LOFU", 8, 7 },
|
|
{ "LOFL", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST", 0x3738c, 0 },
|
|
{ "HBISTMAN", 12, 1 },
|
|
{ "HBISTRES", 11, 1 },
|
|
{ "HBISTSP", 8, 3 },
|
|
{ "HBISTEN", 7, 1 },
|
|
{ "HBISTRST", 6, 1 },
|
|
{ "HCOMP", 5, 1 },
|
|
{ "HPASS", 4, 1 },
|
|
{ "HSEL", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST", 0x37390, 0 },
|
|
{ "ACCCMP", 13, 1 },
|
|
{ "ACCEN", 12, 1 },
|
|
{ "ACCRST", 11, 1 },
|
|
{ "ACCIND", 8, 3 },
|
|
{ "ACCRD", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER", 0x37398, 0 },
|
|
{ "LFREG", 15, 1 },
|
|
{ "LFRC", 14, 1 },
|
|
{ "LGIDLE", 13, 1 },
|
|
{ "LFTGT", 8, 5 },
|
|
{ "LGTGT", 7, 1 },
|
|
{ "LRDY", 6, 1 },
|
|
{ "LIDLE", 5, 1 },
|
|
{ "LCURR", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3739c, 0 },
|
|
{ "OFFSN", 13, 2 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x373a0, 0 },
|
|
{ "RX_OVRSUMPD", 15, 1 },
|
|
{ "RX_OVRKBPD", 14, 1 },
|
|
{ "RX_OVRDIVPD", 13, 1 },
|
|
{ "RX_OFFVGADIS", 12, 1 },
|
|
{ "RX_OFFACDIS", 11, 1 },
|
|
{ "RX_VTERM", 10, 1 },
|
|
{ "RX_DISSPY2D", 8, 1 },
|
|
{ "RX_OBSOVEN", 7, 1 },
|
|
{ "RX_LINKANLGSW", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x373a4, 0 },
|
|
{ "INTDACEGS", 13, 3 },
|
|
{ "INTDACE", 8, 5 },
|
|
{ "INTDACGS", 6, 2 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x373a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x373ac, 0 },
|
|
{ "SMQM", 13, 3 },
|
|
{ "SMQ", 5, 8 },
|
|
{ "EMMD", 3, 2 },
|
|
{ "EMBRDY", 2, 1 },
|
|
{ "EMBUMP", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x373b0, 0 },
|
|
{ "EMSF", 13, 1 },
|
|
{ "EMDATA59", 12, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x373b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x373b8, 0 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3", 0x373bc, 0 },
|
|
{ "FTIMEOUT", 15, 1 },
|
|
{ "FROTCAL4", 14, 1 },
|
|
{ "FDCD2", 13, 1 },
|
|
{ "FPRBSPOLTOG", 12, 1 },
|
|
{ "FPRBSOFF2", 11, 1 },
|
|
{ "FDDCAL2", 10, 1 },
|
|
{ "FDDCFLTR", 9, 1 },
|
|
{ "FDAC6", 8, 1 },
|
|
{ "FDDC5", 7, 1 },
|
|
{ "FDDC3456", 6, 1 },
|
|
{ "FSPY2DATA", 5, 1 },
|
|
{ "FPHSLOCK", 4, 1 },
|
|
{ "FCLKALGN", 3, 1 },
|
|
{ "FCLKALDYN", 2, 1 },
|
|
{ "FDFE", 1, 1 },
|
|
{ "FPRBSOFF", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_TAP_CONTROL", 0x373c0, 0 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_TAP", 0x373c4, 0 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2", 0x373e4, 0 },
|
|
{ "STNDBYSTAT", 15, 1 },
|
|
{ "CALSDONE", 14, 1 },
|
|
{ "ACISRCCMP", 5, 1 },
|
|
{ "PRBSOFFCMP", 4, 1 },
|
|
{ "CLKALGNCMP", 3, 1 },
|
|
{ "ROTFCMP", 2, 1 },
|
|
{ "DCDCMP", 1, 1 },
|
|
{ "QCCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x373e8, 0 },
|
|
{ "FCSADJ", 6, 1 },
|
|
{ "CSIND", 3, 2 },
|
|
{ "CSVAL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL", 0x373ec, 0 },
|
|
{ "DCDTMDOUT", 15, 1 },
|
|
{ "DCDTOEN", 14, 1 },
|
|
{ "DCDLOCK", 13, 1 },
|
|
{ "DCDSTEP", 11, 2 },
|
|
{ "DCDALTWPDIS", 10, 1 },
|
|
{ "DCDOVRDEN", 9, 1 },
|
|
{ "DCCAOVRDEN", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL", 0x373f0, 0 },
|
|
{ "PRBSMODE", 14, 2 },
|
|
{ "DCCSTEP", 10, 2 },
|
|
{ "DCCOVRDEN", 9, 1 },
|
|
{ "DCCLOCK", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL", 0x373f4, 0 },
|
|
{ "DCCQCCMODE", 15, 1 },
|
|
{ "DCCQCCDYN", 14, 1 },
|
|
{ "DCCQCCHOLD", 13, 1 },
|
|
{ "QCCSTEP", 10, 2 },
|
|
{ "QCCOVRDEN", 9, 1 },
|
|
{ "QCCLOCK", 8, 1 },
|
|
{ "QCCSIGN", 6, 2 },
|
|
{ "QCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x373f8, 0 },
|
|
{ "TSTCMP", 15, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x373fc, 0 },
|
|
{ "CALMODEEDGE", 14, 1 },
|
|
{ "TESTCAP", 13, 1 },
|
|
{ "SNAPEN", 12, 1 },
|
|
{ "ASYNCDIR", 11, 1 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x37600, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_MODE8023AZ", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x37604, 0 },
|
|
{ "APLYDCD", 15, 1 },
|
|
{ "PPOL", 13, 2 },
|
|
{ "PCLKSEL", 11, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x37608, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3760c, 0 },
|
|
{ "H1ANOFST", 12, 4 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "TMSCAL", 8, 2 },
|
|
{ "APADJ", 7, 1 },
|
|
{ "RSEL", 6, 1 },
|
|
{ "PHOFFS", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x37610, 0 },
|
|
{ "ROTA", 8, 6 },
|
|
{ "ROTD", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x37614, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROTE", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37618, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOFFF", 8, 4 },
|
|
{ "RAOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3761c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x37620, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 8, 4 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x37624, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x37628, 0 },
|
|
{ "REQWOV", 15, 1 },
|
|
{ "RASEL", 11, 3 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3762c, 0 },
|
|
{ "WRAPSEL", 15, 1 },
|
|
{ "ACTL", 14, 1 },
|
|
{ "PEAK", 9, 5 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x37630, 0 },
|
|
{ "FVOFFSKP", 15, 1 },
|
|
{ "FGAINCHK", 14, 1 },
|
|
{ "FH1ACAL", 13, 1 },
|
|
{ "FH1AFLTR", 11, 2 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "WGAIN", 8, 2 },
|
|
{ "GAIN_STAT", 7, 1 },
|
|
{ "T5VGAIN", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x37634, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37638, 0 },
|
|
{ "PMCFG", 6, 2 },
|
|
{ "PMOFFTIME", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1", 0x3763c, 0 },
|
|
{ "SELI", 9, 1 },
|
|
{ "SERVREF", 5, 3 },
|
|
{ "IQAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2", 0x37640, 0 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37644, 0 },
|
|
{ "SAVEADAC", 8, 1 },
|
|
{ "LOAD2", 7, 1 },
|
|
{ "LOAD1", 6, 1 },
|
|
{ "WRTACC2", 5, 1 },
|
|
{ "WRTACC1", 4, 1 },
|
|
{ "SELAPAN", 3, 1 },
|
|
{ "DASEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x37648, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN", 0x3764c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x37650, 0 },
|
|
{ "ADAC2", 8, 8 },
|
|
{ "ADAC1", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL", 0x37654, 0 },
|
|
{ "FACCPLDYN", 13, 1 },
|
|
{ "ACCPLGAIN", 10, 3 },
|
|
{ "ACCPLREF", 8, 2 },
|
|
{ "ACCPLSTEP", 6, 2 },
|
|
{ "ACCPLASTEP", 1, 5 },
|
|
{ "FACCPL", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE", 0x37658, 0 },
|
|
{ "ACCPLMEANS", 15, 1 },
|
|
{ "CDROVREN", 8, 1 },
|
|
{ "ACCPLBIAS", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET", 0x3765c, 0 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37660, 0 },
|
|
{ "H1OX", 8, 6 },
|
|
{ "H1EX", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR", 0x37664, 0 },
|
|
{ "PILOCK", 10, 1 },
|
|
{ "UNPKPKA", 2, 6 },
|
|
{ "UNPKVGA", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH", 0x37668, 0 },
|
|
{ "OVRAC", 15, 1 },
|
|
{ "OVRPK", 14, 1 },
|
|
{ "OVRTAILS", 12, 2 },
|
|
{ "OVRTAILV", 9, 3 },
|
|
{ "OVRCAP", 8, 1 },
|
|
{ "OVRDCDPRE", 7, 1 },
|
|
{ "OVRDCDPST", 6, 1 },
|
|
{ "DCVSCTMODE", 2, 1 },
|
|
{ "CDRANLGSW", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3766c, 0 },
|
|
{ "PFLAG", 5, 2 },
|
|
{ "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37670, 0 },
|
|
{ "DACCLIP", 15, 1 },
|
|
{ "DPCFRZ", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCLKNQ", 11, 1 },
|
|
{ "DPCWDFE", 10, 1 },
|
|
{ "DPCWPK", 9, 1 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x37674, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "VIEWSCAN", 4, 1 },
|
|
{ "ODEC", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x37678, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "ACCCMP", 11, 1 },
|
|
{ "DCCCMP", 10, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5IQCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3767c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x37680, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FDCCAL", 14, 1 },
|
|
{ "FROTCAL", 13, 1 },
|
|
{ "FIQAMP", 12, 1 },
|
|
{ "FRPTCALF", 11, 1 },
|
|
{ "FINTCALGS", 10, 1 },
|
|
{ "FDCC", 9, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FDCD", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FINTRCALDYN", 1, 1 },
|
|
{ "FQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL", 0x37684, 0 },
|
|
{ "QCCIND", 13, 1 },
|
|
{ "DCDIND", 10, 3 },
|
|
{ "DCCIND", 8, 2 },
|
|
{ "CFSEL", 5, 1 },
|
|
{ "LOFCH", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE", 0x37688, 0 },
|
|
{ "LOFU", 8, 7 },
|
|
{ "LOFL", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST", 0x3768c, 0 },
|
|
{ "HBISTMAN", 12, 1 },
|
|
{ "HBISTRES", 11, 1 },
|
|
{ "HBISTSP", 8, 3 },
|
|
{ "HBISTEN", 7, 1 },
|
|
{ "HBISTRST", 6, 1 },
|
|
{ "HCOMP", 5, 1 },
|
|
{ "HPASS", 4, 1 },
|
|
{ "HSEL", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST", 0x37690, 0 },
|
|
{ "ACCCMP", 13, 1 },
|
|
{ "ACCEN", 12, 1 },
|
|
{ "ACCRST", 11, 1 },
|
|
{ "ACCIND", 8, 3 },
|
|
{ "ACCRD", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER", 0x37698, 0 },
|
|
{ "LFREG", 15, 1 },
|
|
{ "LFRC", 14, 1 },
|
|
{ "LGIDLE", 13, 1 },
|
|
{ "LFTGT", 8, 5 },
|
|
{ "LGTGT", 7, 1 },
|
|
{ "LRDY", 6, 1 },
|
|
{ "LIDLE", 5, 1 },
|
|
{ "LCURR", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3769c, 0 },
|
|
{ "OFFSN", 13, 2 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x376a0, 0 },
|
|
{ "RX_OVRSUMPD", 15, 1 },
|
|
{ "RX_OVRKBPD", 14, 1 },
|
|
{ "RX_OVRDIVPD", 13, 1 },
|
|
{ "RX_OFFVGADIS", 12, 1 },
|
|
{ "RX_OFFACDIS", 11, 1 },
|
|
{ "RX_VTERM", 10, 1 },
|
|
{ "RX_DISSPY2D", 8, 1 },
|
|
{ "RX_OBSOVEN", 7, 1 },
|
|
{ "RX_LINKANLGSW", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x376a4, 0 },
|
|
{ "INTDACEGS", 13, 3 },
|
|
{ "INTDACE", 8, 5 },
|
|
{ "INTDACGS", 6, 2 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x376a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x376ac, 0 },
|
|
{ "SMQM", 13, 3 },
|
|
{ "SMQ", 5, 8 },
|
|
{ "EMMD", 3, 2 },
|
|
{ "EMBRDY", 2, 1 },
|
|
{ "EMBUMP", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x376b0, 0 },
|
|
{ "EMSF", 13, 1 },
|
|
{ "EMDATA59", 12, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x376b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x376b8, 0 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3", 0x376bc, 0 },
|
|
{ "FTIMEOUT", 15, 1 },
|
|
{ "FROTCAL4", 14, 1 },
|
|
{ "FDCD2", 13, 1 },
|
|
{ "FPRBSPOLTOG", 12, 1 },
|
|
{ "FPRBSOFF2", 11, 1 },
|
|
{ "FDDCAL2", 10, 1 },
|
|
{ "FDDCFLTR", 9, 1 },
|
|
{ "FDAC6", 8, 1 },
|
|
{ "FDDC5", 7, 1 },
|
|
{ "FDDC3456", 6, 1 },
|
|
{ "FSPY2DATA", 5, 1 },
|
|
{ "FPHSLOCK", 4, 1 },
|
|
{ "FCLKALGN", 3, 1 },
|
|
{ "FCLKALDYN", 2, 1 },
|
|
{ "FDFE", 1, 1 },
|
|
{ "FPRBSOFF", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_TAP_CONTROL", 0x376c0, 0 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_TAP", 0x376c4, 0 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2", 0x376e4, 0 },
|
|
{ "STNDBYSTAT", 15, 1 },
|
|
{ "CALSDONE", 14, 1 },
|
|
{ "ACISRCCMP", 5, 1 },
|
|
{ "PRBSOFFCMP", 4, 1 },
|
|
{ "CLKALGNCMP", 3, 1 },
|
|
{ "ROTFCMP", 2, 1 },
|
|
{ "DCDCMP", 1, 1 },
|
|
{ "QCCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x376e8, 0 },
|
|
{ "FCSADJ", 6, 1 },
|
|
{ "CSIND", 3, 2 },
|
|
{ "CSVAL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL", 0x376ec, 0 },
|
|
{ "DCDTMDOUT", 15, 1 },
|
|
{ "DCDTOEN", 14, 1 },
|
|
{ "DCDLOCK", 13, 1 },
|
|
{ "DCDSTEP", 11, 2 },
|
|
{ "DCDALTWPDIS", 10, 1 },
|
|
{ "DCDOVRDEN", 9, 1 },
|
|
{ "DCCAOVRDEN", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL", 0x376f0, 0 },
|
|
{ "PRBSMODE", 14, 2 },
|
|
{ "DCCSTEP", 10, 2 },
|
|
{ "DCCOVRDEN", 9, 1 },
|
|
{ "DCCLOCK", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL", 0x376f4, 0 },
|
|
{ "DCCQCCMODE", 15, 1 },
|
|
{ "DCCQCCDYN", 14, 1 },
|
|
{ "DCCQCCHOLD", 13, 1 },
|
|
{ "QCCSTEP", 10, 2 },
|
|
{ "QCCOVRDEN", 9, 1 },
|
|
{ "QCCLOCK", 8, 1 },
|
|
{ "QCCSIGN", 6, 2 },
|
|
{ "QCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x376f8, 0 },
|
|
{ "TSTCMP", 15, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x376fc, 0 },
|
|
{ "CALMODEEDGE", 14, 1 },
|
|
{ "TESTCAP", 13, 1 },
|
|
{ "SNAPEN", 12, 1 },
|
|
{ "ASYNCDIR", 11, 1 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x37700, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_MODE8023AZ", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x37704, 0 },
|
|
{ "APLYDCD", 15, 1 },
|
|
{ "PPOL", 13, 2 },
|
|
{ "PCLKSEL", 11, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x37708, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3770c, 0 },
|
|
{ "H1ANOFST", 12, 4 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "TMSCAL", 8, 2 },
|
|
{ "APADJ", 7, 1 },
|
|
{ "RSEL", 6, 1 },
|
|
{ "PHOFFS", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x37710, 0 },
|
|
{ "ROTA", 8, 6 },
|
|
{ "ROTD", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x37714, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROTE", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37718, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOFFF", 8, 4 },
|
|
{ "RAOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3771c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x37720, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 8, 4 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x37724, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x37728, 0 },
|
|
{ "REQWOV", 15, 1 },
|
|
{ "RASEL", 11, 3 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3772c, 0 },
|
|
{ "WRAPSEL", 15, 1 },
|
|
{ "ACTL", 14, 1 },
|
|
{ "PEAK", 9, 5 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x37730, 0 },
|
|
{ "FVOFFSKP", 15, 1 },
|
|
{ "FGAINCHK", 14, 1 },
|
|
{ "FH1ACAL", 13, 1 },
|
|
{ "FH1AFLTR", 11, 2 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "WGAIN", 8, 2 },
|
|
{ "GAIN_STAT", 7, 1 },
|
|
{ "T5VGAIN", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x37734, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37738, 0 },
|
|
{ "PMCFG", 6, 2 },
|
|
{ "PMOFFTIME", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1", 0x3773c, 0 },
|
|
{ "SELI", 9, 1 },
|
|
{ "SERVREF", 5, 3 },
|
|
{ "IQAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2", 0x37740, 0 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37744, 0 },
|
|
{ "SAVEADAC", 8, 1 },
|
|
{ "LOAD2", 7, 1 },
|
|
{ "LOAD1", 6, 1 },
|
|
{ "WRTACC2", 5, 1 },
|
|
{ "WRTACC1", 4, 1 },
|
|
{ "SELAPAN", 3, 1 },
|
|
{ "DASEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x37748, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN", 0x3774c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x37750, 0 },
|
|
{ "ADAC2", 8, 8 },
|
|
{ "ADAC1", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL", 0x37754, 0 },
|
|
{ "FACCPLDYN", 13, 1 },
|
|
{ "ACCPLGAIN", 10, 3 },
|
|
{ "ACCPLREF", 8, 2 },
|
|
{ "ACCPLSTEP", 6, 2 },
|
|
{ "ACCPLASTEP", 1, 5 },
|
|
{ "FACCPL", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE", 0x37758, 0 },
|
|
{ "ACCPLMEANS", 15, 1 },
|
|
{ "CDROVREN", 8, 1 },
|
|
{ "ACCPLBIAS", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET", 0x3775c, 0 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37760, 0 },
|
|
{ "H1OX", 8, 6 },
|
|
{ "H1EX", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR", 0x37764, 0 },
|
|
{ "PILOCK", 10, 1 },
|
|
{ "UNPKPKA", 2, 6 },
|
|
{ "UNPKVGA", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH", 0x37768, 0 },
|
|
{ "OVRAC", 15, 1 },
|
|
{ "OVRPK", 14, 1 },
|
|
{ "OVRTAILS", 12, 2 },
|
|
{ "OVRTAILV", 9, 3 },
|
|
{ "OVRCAP", 8, 1 },
|
|
{ "OVRDCDPRE", 7, 1 },
|
|
{ "OVRDCDPST", 6, 1 },
|
|
{ "DCVSCTMODE", 2, 1 },
|
|
{ "CDRANLGSW", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3776c, 0 },
|
|
{ "PFLAG", 5, 2 },
|
|
{ "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37770, 0 },
|
|
{ "DACCLIP", 15, 1 },
|
|
{ "DPCFRZ", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCLKNQ", 11, 1 },
|
|
{ "DPCWDFE", 10, 1 },
|
|
{ "DPCWPK", 9, 1 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x37774, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "VIEWSCAN", 4, 1 },
|
|
{ "ODEC", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x37778, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "ACCCMP", 11, 1 },
|
|
{ "DCCCMP", 10, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5IQCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3777c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x37780, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FDCCAL", 14, 1 },
|
|
{ "FROTCAL", 13, 1 },
|
|
{ "FIQAMP", 12, 1 },
|
|
{ "FRPTCALF", 11, 1 },
|
|
{ "FINTCALGS", 10, 1 },
|
|
{ "FDCC", 9, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FDCD", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FINTRCALDYN", 1, 1 },
|
|
{ "FQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL", 0x37784, 0 },
|
|
{ "QCCIND", 13, 1 },
|
|
{ "DCDIND", 10, 3 },
|
|
{ "DCCIND", 8, 2 },
|
|
{ "CFSEL", 5, 1 },
|
|
{ "LOFCH", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE", 0x37788, 0 },
|
|
{ "LOFU", 8, 7 },
|
|
{ "LOFL", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST", 0x3778c, 0 },
|
|
{ "HBISTMAN", 12, 1 },
|
|
{ "HBISTRES", 11, 1 },
|
|
{ "HBISTSP", 8, 3 },
|
|
{ "HBISTEN", 7, 1 },
|
|
{ "HBISTRST", 6, 1 },
|
|
{ "HCOMP", 5, 1 },
|
|
{ "HPASS", 4, 1 },
|
|
{ "HSEL", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST", 0x37790, 0 },
|
|
{ "ACCCMP", 13, 1 },
|
|
{ "ACCEN", 12, 1 },
|
|
{ "ACCRST", 11, 1 },
|
|
{ "ACCIND", 8, 3 },
|
|
{ "ACCRD", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER", 0x37798, 0 },
|
|
{ "LFREG", 15, 1 },
|
|
{ "LFRC", 14, 1 },
|
|
{ "LGIDLE", 13, 1 },
|
|
{ "LFTGT", 8, 5 },
|
|
{ "LGTGT", 7, 1 },
|
|
{ "LRDY", 6, 1 },
|
|
{ "LIDLE", 5, 1 },
|
|
{ "LCURR", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3779c, 0 },
|
|
{ "OFFSN", 13, 2 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x377a0, 0 },
|
|
{ "RX_OVRSUMPD", 15, 1 },
|
|
{ "RX_OVRKBPD", 14, 1 },
|
|
{ "RX_OVRDIVPD", 13, 1 },
|
|
{ "RX_OFFVGADIS", 12, 1 },
|
|
{ "RX_OFFACDIS", 11, 1 },
|
|
{ "RX_VTERM", 10, 1 },
|
|
{ "RX_DISSPY2D", 8, 1 },
|
|
{ "RX_OBSOVEN", 7, 1 },
|
|
{ "RX_LINKANLGSW", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x377a4, 0 },
|
|
{ "INTDACEGS", 13, 3 },
|
|
{ "INTDACE", 8, 5 },
|
|
{ "INTDACGS", 6, 2 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x377a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x377ac, 0 },
|
|
{ "SMQM", 13, 3 },
|
|
{ "SMQ", 5, 8 },
|
|
{ "EMMD", 3, 2 },
|
|
{ "EMBRDY", 2, 1 },
|
|
{ "EMBUMP", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x377b0, 0 },
|
|
{ "EMSF", 13, 1 },
|
|
{ "EMDATA59", 12, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x377b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x377b8, 0 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3", 0x377bc, 0 },
|
|
{ "FTIMEOUT", 15, 1 },
|
|
{ "FROTCAL4", 14, 1 },
|
|
{ "FDCD2", 13, 1 },
|
|
{ "FPRBSPOLTOG", 12, 1 },
|
|
{ "FPRBSOFF2", 11, 1 },
|
|
{ "FDDCAL2", 10, 1 },
|
|
{ "FDDCFLTR", 9, 1 },
|
|
{ "FDAC6", 8, 1 },
|
|
{ "FDDC5", 7, 1 },
|
|
{ "FDDC3456", 6, 1 },
|
|
{ "FSPY2DATA", 5, 1 },
|
|
{ "FPHSLOCK", 4, 1 },
|
|
{ "FCLKALGN", 3, 1 },
|
|
{ "FCLKALDYN", 2, 1 },
|
|
{ "FDFE", 1, 1 },
|
|
{ "FPRBSOFF", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_TAP_CONTROL", 0x377c0, 0 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_TAP", 0x377c4, 0 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2", 0x377e4, 0 },
|
|
{ "STNDBYSTAT", 15, 1 },
|
|
{ "CALSDONE", 14, 1 },
|
|
{ "ACISRCCMP", 5, 1 },
|
|
{ "PRBSOFFCMP", 4, 1 },
|
|
{ "CLKALGNCMP", 3, 1 },
|
|
{ "ROTFCMP", 2, 1 },
|
|
{ "DCDCMP", 1, 1 },
|
|
{ "QCCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x377e8, 0 },
|
|
{ "FCSADJ", 6, 1 },
|
|
{ "CSIND", 3, 2 },
|
|
{ "CSVAL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL", 0x377ec, 0 },
|
|
{ "DCDTMDOUT", 15, 1 },
|
|
{ "DCDTOEN", 14, 1 },
|
|
{ "DCDLOCK", 13, 1 },
|
|
{ "DCDSTEP", 11, 2 },
|
|
{ "DCDALTWPDIS", 10, 1 },
|
|
{ "DCDOVRDEN", 9, 1 },
|
|
{ "DCCAOVRDEN", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL", 0x377f0, 0 },
|
|
{ "PRBSMODE", 14, 2 },
|
|
{ "DCCSTEP", 10, 2 },
|
|
{ "DCCOVRDEN", 9, 1 },
|
|
{ "DCCLOCK", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL", 0x377f4, 0 },
|
|
{ "DCCQCCMODE", 15, 1 },
|
|
{ "DCCQCCDYN", 14, 1 },
|
|
{ "DCCQCCHOLD", 13, 1 },
|
|
{ "QCCSTEP", 10, 2 },
|
|
{ "QCCOVRDEN", 9, 1 },
|
|
{ "QCCLOCK", 8, 1 },
|
|
{ "QCCSIGN", 6, 2 },
|
|
{ "QCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x377f8, 0 },
|
|
{ "TSTCMP", 15, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x377fc, 0 },
|
|
{ "CALMODEEDGE", 14, 1 },
|
|
{ "TESTCAP", 13, 1 },
|
|
{ "SNAPEN", 12, 1 },
|
|
{ "ASYNCDIR", 11, 1 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x37a00, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_MODE8023AZ", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x37a04, 0 },
|
|
{ "APLYDCD", 15, 1 },
|
|
{ "PPOL", 13, 2 },
|
|
{ "PCLKSEL", 11, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x37a08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x37a0c, 0 },
|
|
{ "H1ANOFST", 12, 4 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "TMSCAL", 8, 2 },
|
|
{ "APADJ", 7, 1 },
|
|
{ "RSEL", 6, 1 },
|
|
{ "PHOFFS", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x37a10, 0 },
|
|
{ "ROTA", 8, 6 },
|
|
{ "ROTD", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x37a14, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROTE", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37a18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOFFF", 8, 4 },
|
|
{ "RAOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x37a1c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x37a20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 8, 4 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x37a24, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x37a28, 0 },
|
|
{ "REQWOV", 15, 1 },
|
|
{ "RASEL", 11, 3 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x37a2c, 0 },
|
|
{ "WRAPSEL", 15, 1 },
|
|
{ "ACTL", 14, 1 },
|
|
{ "PEAK", 9, 5 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x37a30, 0 },
|
|
{ "FVOFFSKP", 15, 1 },
|
|
{ "FGAINCHK", 14, 1 },
|
|
{ "FH1ACAL", 13, 1 },
|
|
{ "FH1AFLTR", 11, 2 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "WGAIN", 8, 2 },
|
|
{ "GAIN_STAT", 7, 1 },
|
|
{ "T5VGAIN", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x37a34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37a38, 0 },
|
|
{ "PMCFG", 6, 2 },
|
|
{ "PMOFFTIME", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1", 0x37a3c, 0 },
|
|
{ "SELI", 9, 1 },
|
|
{ "SERVREF", 5, 3 },
|
|
{ "IQAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2", 0x37a40, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37a44, 0 },
|
|
{ "SAVEADAC", 8, 1 },
|
|
{ "LOAD2", 7, 1 },
|
|
{ "LOAD1", 6, 1 },
|
|
{ "WRTACC2", 5, 1 },
|
|
{ "WRTACC1", 4, 1 },
|
|
{ "SELAPAN", 3, 1 },
|
|
{ "DASEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x37a48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN", 0x37a4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x37a50, 0 },
|
|
{ "ADAC2", 8, 8 },
|
|
{ "ADAC1", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL", 0x37a54, 0 },
|
|
{ "FACCPLDYN", 13, 1 },
|
|
{ "ACCPLGAIN", 10, 3 },
|
|
{ "ACCPLREF", 8, 2 },
|
|
{ "ACCPLSTEP", 6, 2 },
|
|
{ "ACCPLASTEP", 1, 5 },
|
|
{ "FACCPL", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE", 0x37a58, 0 },
|
|
{ "ACCPLMEANS", 15, 1 },
|
|
{ "CDROVREN", 8, 1 },
|
|
{ "ACCPLBIAS", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET", 0x37a5c, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37a60, 0 },
|
|
{ "H1OX", 8, 6 },
|
|
{ "H1EX", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR", 0x37a64, 0 },
|
|
{ "PILOCK", 10, 1 },
|
|
{ "UNPKPKA", 2, 6 },
|
|
{ "UNPKVGA", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH", 0x37a68, 0 },
|
|
{ "OVRAC", 15, 1 },
|
|
{ "OVRPK", 14, 1 },
|
|
{ "OVRTAILS", 12, 2 },
|
|
{ "OVRTAILV", 9, 3 },
|
|
{ "OVRCAP", 8, 1 },
|
|
{ "OVRDCDPRE", 7, 1 },
|
|
{ "OVRDCDPST", 6, 1 },
|
|
{ "DCVSCTMODE", 2, 1 },
|
|
{ "CDRANLGSW", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x37a6c, 0 },
|
|
{ "PFLAG", 5, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37a70, 0 },
|
|
{ "DACCLIP", 15, 1 },
|
|
{ "DPCFRZ", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCLKNQ", 11, 1 },
|
|
{ "DPCWDFE", 10, 1 },
|
|
{ "DPCWPK", 9, 1 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x37a74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "VIEWSCAN", 4, 1 },
|
|
{ "ODEC", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x37a78, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "ACCCMP", 11, 1 },
|
|
{ "DCCCMP", 10, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5IQCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x37a7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x37a80, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FDCCAL", 14, 1 },
|
|
{ "FROTCAL", 13, 1 },
|
|
{ "FIQAMP", 12, 1 },
|
|
{ "FRPTCALF", 11, 1 },
|
|
{ "FINTCALGS", 10, 1 },
|
|
{ "FDCC", 9, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FDCD", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FINTRCALDYN", 1, 1 },
|
|
{ "FQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL", 0x37a84, 0 },
|
|
{ "QCCIND", 13, 1 },
|
|
{ "DCDIND", 10, 3 },
|
|
{ "DCCIND", 8, 2 },
|
|
{ "CFSEL", 5, 1 },
|
|
{ "LOFCH", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE", 0x37a88, 0 },
|
|
{ "LOFU", 8, 7 },
|
|
{ "LOFL", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST", 0x37a8c, 0 },
|
|
{ "HBISTMAN", 12, 1 },
|
|
{ "HBISTRES", 11, 1 },
|
|
{ "HBISTSP", 8, 3 },
|
|
{ "HBISTEN", 7, 1 },
|
|
{ "HBISTRST", 6, 1 },
|
|
{ "HCOMP", 5, 1 },
|
|
{ "HPASS", 4, 1 },
|
|
{ "HSEL", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST", 0x37a90, 0 },
|
|
{ "ACCCMP", 13, 1 },
|
|
{ "ACCEN", 12, 1 },
|
|
{ "ACCRST", 11, 1 },
|
|
{ "ACCIND", 8, 3 },
|
|
{ "ACCRD", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER", 0x37a98, 0 },
|
|
{ "LFREG", 15, 1 },
|
|
{ "LFRC", 14, 1 },
|
|
{ "LGIDLE", 13, 1 },
|
|
{ "LFTGT", 8, 5 },
|
|
{ "LGTGT", 7, 1 },
|
|
{ "LRDY", 6, 1 },
|
|
{ "LIDLE", 5, 1 },
|
|
{ "LCURR", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x37a9c, 0 },
|
|
{ "OFFSN", 13, 2 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x37aa0, 0 },
|
|
{ "RX_OVRSUMPD", 15, 1 },
|
|
{ "RX_OVRKBPD", 14, 1 },
|
|
{ "RX_OVRDIVPD", 13, 1 },
|
|
{ "RX_OFFVGADIS", 12, 1 },
|
|
{ "RX_OFFACDIS", 11, 1 },
|
|
{ "RX_VTERM", 10, 1 },
|
|
{ "RX_DISSPY2D", 8, 1 },
|
|
{ "RX_OBSOVEN", 7, 1 },
|
|
{ "RX_LINKANLGSW", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x37aa4, 0 },
|
|
{ "INTDACEGS", 13, 3 },
|
|
{ "INTDACE", 8, 5 },
|
|
{ "INTDACGS", 6, 2 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x37aa8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x37aac, 0 },
|
|
{ "SMQM", 13, 3 },
|
|
{ "SMQ", 5, 8 },
|
|
{ "EMMD", 3, 2 },
|
|
{ "EMBRDY", 2, 1 },
|
|
{ "EMBUMP", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x37ab0, 0 },
|
|
{ "EMSF", 13, 1 },
|
|
{ "EMDATA59", 12, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x37ab4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x37ab8, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3", 0x37abc, 0 },
|
|
{ "FTIMEOUT", 15, 1 },
|
|
{ "FROTCAL4", 14, 1 },
|
|
{ "FDCD2", 13, 1 },
|
|
{ "FPRBSPOLTOG", 12, 1 },
|
|
{ "FPRBSOFF2", 11, 1 },
|
|
{ "FDDCAL2", 10, 1 },
|
|
{ "FDDCFLTR", 9, 1 },
|
|
{ "FDAC6", 8, 1 },
|
|
{ "FDDC5", 7, 1 },
|
|
{ "FDDC3456", 6, 1 },
|
|
{ "FSPY2DATA", 5, 1 },
|
|
{ "FPHSLOCK", 4, 1 },
|
|
{ "FCLKALGN", 3, 1 },
|
|
{ "FCLKALDYN", 2, 1 },
|
|
{ "FDFE", 1, 1 },
|
|
{ "FPRBSOFF", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL", 0x37ac0, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_TAP", 0x37ac4, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2", 0x37ae4, 0 },
|
|
{ "STNDBYSTAT", 15, 1 },
|
|
{ "CALSDONE", 14, 1 },
|
|
{ "ACISRCCMP", 5, 1 },
|
|
{ "PRBSOFFCMP", 4, 1 },
|
|
{ "CLKALGNCMP", 3, 1 },
|
|
{ "ROTFCMP", 2, 1 },
|
|
{ "DCDCMP", 1, 1 },
|
|
{ "QCCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x37ae8, 0 },
|
|
{ "FCSADJ", 6, 1 },
|
|
{ "CSIND", 3, 2 },
|
|
{ "CSVAL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL", 0x37aec, 0 },
|
|
{ "DCDTMDOUT", 15, 1 },
|
|
{ "DCDTOEN", 14, 1 },
|
|
{ "DCDLOCK", 13, 1 },
|
|
{ "DCDSTEP", 11, 2 },
|
|
{ "DCDALTWPDIS", 10, 1 },
|
|
{ "DCDOVRDEN", 9, 1 },
|
|
{ "DCCAOVRDEN", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL", 0x37af0, 0 },
|
|
{ "PRBSMODE", 14, 2 },
|
|
{ "DCCSTEP", 10, 2 },
|
|
{ "DCCOVRDEN", 9, 1 },
|
|
{ "DCCLOCK", 8, 1 },
|
|
{ "DCDSIGN", 6, 2 },
|
|
{ "DCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL", 0x37af4, 0 },
|
|
{ "DCCQCCMODE", 15, 1 },
|
|
{ "DCCQCCDYN", 14, 1 },
|
|
{ "DCCQCCHOLD", 13, 1 },
|
|
{ "QCCSTEP", 10, 2 },
|
|
{ "QCCOVRDEN", 9, 1 },
|
|
{ "QCCLOCK", 8, 1 },
|
|
{ "QCCSIGN", 6, 2 },
|
|
{ "QCDAMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x37af8, 0 },
|
|
{ "TSTCMP", 15, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x37afc, 0 },
|
|
{ "CALMODEEDGE", 14, 1 },
|
|
{ "TESTCAP", 13, 1 },
|
|
{ "SNAPEN", 12, 1 },
|
|
{ "ASYNCDIR", 11, 1 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_mc_0_regs[] = {
|
|
{ "MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS", 0x47000, 0 },
|
|
{ "DP18_PLL_LOCK", 1, 15 },
|
|
{ "MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS", 0x47004, 0 },
|
|
{ "AD32S_PLL_LOCK", 14, 2 },
|
|
{ "MC_DDRPHY_PC_RANK_PAIR0", 0x47008, 0 },
|
|
{ "RANK_PAIR0_PRI", 13, 3 },
|
|
{ "RANK_PAIR0_PRI_V", 12, 1 },
|
|
{ "RANK_PAIR0_SEC", 9, 3 },
|
|
{ "RANK_PAIR0_SEC_V", 8, 1 },
|
|
{ "RANK_PAIR1_PRI", 5, 3 },
|
|
{ "RANK_PAIR1_PRI_V", 4, 1 },
|
|
{ "RANK_PAIR1_SEC", 1, 3 },
|
|
{ "RANK_PAIR1_SEC_V", 0, 1 },
|
|
{ "MC_DDRPHY_PC_RANK_PAIR1", 0x4700c, 0 },
|
|
{ "RANK_PAIR2_PRI", 13, 3 },
|
|
{ "RANK_PAIR2_PRI_V", 12, 1 },
|
|
{ "RANK_PAIR2_SEC", 9, 3 },
|
|
{ "RANK_PAIR2_SEC_V", 8, 1 },
|
|
{ "RANK_PAIR3_PRI", 5, 3 },
|
|
{ "RANK_PAIR3_PRI_V", 4, 1 },
|
|
{ "RANK_PAIR3_SEC", 1, 3 },
|
|
{ "RANK_PAIR3_SEC_V", 0, 1 },
|
|
{ "MC_DDRPHY_PC_BASE_CNTR0", 0x47010, 0 },
|
|
{ "MC_DDRPHY_PC_RELOAD_VALUE0", 0x47014, 0 },
|
|
{ "PERIODIC_CAL_REQ_EN", 15, 1 },
|
|
{ "PERIODIC_RELOAD_VALUE0", 0, 15 },
|
|
{ "MC_DDRPHY_PC_BASE_CNTR1", 0x47018, 0 },
|
|
{ "MC_DDRPHY_PC_CAL_TIMER", 0x4701c, 0 },
|
|
{ "MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE", 0x47020, 0 },
|
|
{ "MC_DDRPHY_PC_ZCAL_TIMER", 0x47024, 0 },
|
|
{ "MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE", 0x47028, 0 },
|
|
{ "MC_DDRPHY_PC_PER_CAL_CONFIG", 0x4702c, 0 },
|
|
{ "PER_ENA_RANK_PAIR", 12, 4 },
|
|
{ "PER_ENA_ZCAL", 11, 1 },
|
|
{ "PER_ENA_SYSCLK_ALIGN", 10, 1 },
|
|
{ "ENA_PER_RD_CTR", 9, 1 },
|
|
{ "ENA_PER_RDCLK_ALIGN", 8, 1 },
|
|
{ "ENA_PER_DQS_ALIGN", 7, 1 },
|
|
{ "PER_NEXT_RANK_PAIR", 5, 2 },
|
|
{ "FAST_SIM_PER_CNTR", 4, 1 },
|
|
{ "START_INIT_CAL", 3, 1 },
|
|
{ "START_PER_CAL", 2, 1 },
|
|
{ "MC_DDRPHY_PC_PER_ZCAL_CONFIG", 0x4703c, 0 },
|
|
{ "PER_ZCAL_ENA_RANK", 8, 8 },
|
|
{ "PER_ZCAL_NEXT_RANK", 5, 3 },
|
|
{ "START_PER_ZCAL", 4, 1 },
|
|
{ "MC_DDRPHY_PC_CONFIG0", 0x47030, 0 },
|
|
{ "DDRPHY_PROTOCOL", 12, 4 },
|
|
{ "DATA_MUX4_1MODE", 11, 1 },
|
|
{ "SPAM_EN", 10, 1 },
|
|
{ "DDR4_CMD_SIG_REDUCTION", 9, 1 },
|
|
{ "SYSCLK_2X_MEMINTCLKO", 8, 1 },
|
|
{ "LOW_LATENCY", 3, 1 },
|
|
{ "DDR4_IPW_LOOP_DIS", 2, 1 },
|
|
{ "DDR4_VLEVEL_BANK_GROUP", 1, 1 },
|
|
{ "MC_DDRPHY_PC_CONFIG1", 0x47034, 0 },
|
|
{ "WRITE_LATENCY_OFFSET", 12, 4 },
|
|
{ "READ_LATENCY_OFFSET", 8, 4 },
|
|
{ "MEMCTL_CIC_FAST", 7, 1 },
|
|
{ "MEMCTL_CIS_IGNORE", 6, 1 },
|
|
{ "DISABLE_MEMCTL_CAL", 5, 1 },
|
|
{ "MEMORY_TYPE", 2, 3 },
|
|
{ "DDR4_PDA_MODE", 1, 1 },
|
|
{ "MC_DDRPHY_PC_RESETS", 0x47038, 0 },
|
|
{ "PLL_RESET", 15, 1 },
|
|
{ "SYSCLK_RESET", 14, 1 },
|
|
{ "MC_DDRPHY_PC_ERROR_STATUS0", 0x47048, 0 },
|
|
{ "RC_ERROR", 15, 1 },
|
|
{ "WC_ERROR", 14, 1 },
|
|
{ "SEQ_ERROR", 13, 1 },
|
|
{ "CC_ERROR", 12, 1 },
|
|
{ "APB_ERROR", 11, 1 },
|
|
{ "PC_ERROR", 10, 1 },
|
|
{ "MC_DDRPHY_PC_ERROR_MASK0", 0x4704c, 0 },
|
|
{ "RC_ERROR_MASK", 15, 1 },
|
|
{ "WC_ERROR_MASK", 14, 1 },
|
|
{ "SEQ_ERROR_MASK", 13, 1 },
|
|
{ "CC_ERROR_MASK", 12, 1 },
|
|
{ "APB_ERROR_MASK", 11, 1 },
|
|
{ "PC_ERROR_MASK", 10, 1 },
|
|
{ "MC_DDRPHY_PC_IO_PVT_FET_CONTROL", 0x47050, 0 },
|
|
{ "PVTP", 11, 5 },
|
|
{ "PVTN", 6, 5 },
|
|
{ "PVT_OVERRIDE", 5, 1 },
|
|
{ "ENABLE_ZCAL", 4, 1 },
|
|
{ "MC_DDRPHY_PC_VREF_DRV_CONTROL", 0x47054, 0 },
|
|
{ "VREFDQ0DSGN", 15, 1 },
|
|
{ "VREFDQ0D", 11, 4 },
|
|
{ "VREFDQ1DSGN", 10, 1 },
|
|
{ "VREFDQ1D", 6, 4 },
|
|
{ "EN_ANALOG_PD", 3, 1 },
|
|
{ "ANALOG_PD_DLY", 2, 1 },
|
|
{ "ANALOG_PD_DIV", 0, 2 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_CONFIG0", 0x47058, 0 },
|
|
{ "ENA_WR_LEVEL", 15, 1 },
|
|
{ "ENA_INITIAL_PAT_WR", 14, 1 },
|
|
{ "ENA_DQS_ALIGN", 13, 1 },
|
|
{ "ENA_RDCLK_ALIGN", 12, 1 },
|
|
{ "ENA_READ_CTR", 11, 1 },
|
|
{ "ENA_WRITE_CTR", 10, 1 },
|
|
{ "ENA_INITIAL_COARSE_WR", 9, 1 },
|
|
{ "ENA_COARSE_RD", 8, 1 },
|
|
{ "ENA_CUSTOM_RD", 7, 1 },
|
|
{ "ENA_CUSTOM_WR", 6, 1 },
|
|
{ "ABORT_ON_CAL_ERROR", 5, 1 },
|
|
{ "ENA_DIGITAL_EYE", 4, 1 },
|
|
{ "ENA_RANK_PAIR", 0, 4 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_CONFIG1", 0x4705c, 0 },
|
|
{ "REFRESH_COUNT", 12, 4 },
|
|
{ "REFRESH_CONTROL", 10, 2 },
|
|
{ "REFRESH_ALL_RANKS", 9, 1 },
|
|
{ "REFRESH_INTERVAL", 0, 7 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_ERROR", 0x47060, 0 },
|
|
{ "ERROR_WR_LEVEL", 15, 1 },
|
|
{ "ERROR_INITIAL_PAT_WRITE", 14, 1 },
|
|
{ "ERROR_DQS_ALIGN", 13, 1 },
|
|
{ "ERROR_RDCLK_ALIGN", 12, 1 },
|
|
{ "ERROR_READ_CTR", 11, 1 },
|
|
{ "ERROR_WRITE_CTR", 10, 1 },
|
|
{ "ERROR_INITIAL_COARSE_WR", 9, 1 },
|
|
{ "ERROR_COARSE_RD", 8, 1 },
|
|
{ "ERROR_CUSTOM_RD", 7, 1 },
|
|
{ "ERROR_CUSTOM_WR", 6, 1 },
|
|
{ "ERROR_DIGITAL_EYE", 5, 1 },
|
|
{ "ERROR_RANK_PAIR", 0, 4 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_MASK", 0x47068, 0 },
|
|
{ "ERROR_WR_LEVEL_MASK", 15, 1 },
|
|
{ "ERROR_INITIAL_PAT_WRITE_MASK", 14, 1 },
|
|
{ "ERROR_DQS_ALIGN_MASK", 13, 1 },
|
|
{ "ERROR_RDCLK_ALIGN_MASK", 12, 1 },
|
|
{ "ERROR_READ_CTR_MASK", 11, 1 },
|
|
{ "ERROR_WRITE_CTR_MASK", 10, 1 },
|
|
{ "ERROR_INITIAL_COARSE_WR_MASK", 9, 1 },
|
|
{ "ERROR_COARSE_RD_MASK", 8, 1 },
|
|
{ "ERROR_CUSTOM_RD_MASK", 7, 1 },
|
|
{ "ERROR_CUSTOM_WR_MASK", 6, 1 },
|
|
{ "ERROR_DIGITAL_EYE_MASK", 5, 1 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_STATUS", 0x47064, 0 },
|
|
{ "INIT_CAL_COMPLETE", 12, 4 },
|
|
{ "PER_CAL_ABORT", 6, 1 },
|
|
{ "MC_DDRPHY_PC_IO_PVT_FET_STATUS", 0x4706c, 0 },
|
|
{ "PVTP", 11, 5 },
|
|
{ "PVTN", 6, 5 },
|
|
{ "MC_DDRPHY_PC_MR0_PRI_RP", 0x47070, 0 },
|
|
{ "MC_DDRPHY_PC_MR1_PRI_RP", 0x47074, 0 },
|
|
{ "MC_DDRPHY_PC_MR2_PRI_RP", 0x47078, 0 },
|
|
{ "MC_DDRPHY_PC_MR3_PRI_RP", 0x4707c, 0 },
|
|
{ "MC_DDRPHY_PC_MR0_SEC_RP", 0x47080, 0 },
|
|
{ "MC_DDRPHY_PC_MR1_SEC_RP", 0x47084, 0 },
|
|
{ "MC_DDRPHY_PC_MR2_SEC_RP", 0x47088, 0 },
|
|
{ "MC_DDRPHY_PC_MR3_SEC_RP", 0x4708c, 0 },
|
|
{ "MC_DDRPHY_PC_RANK_GROUP", 0x47044, 0 },
|
|
{ "ADDR_MIRROR_RP0_PRI", 15, 1 },
|
|
{ "ADDR_MIRROR_RP0_SEC", 14, 1 },
|
|
{ "ADDR_MIRROR_RP1_PRI", 13, 1 },
|
|
{ "ADDR_MIRROR_RP1_SEC", 12, 1 },
|
|
{ "ADDR_MIRROR_RP2_PRI", 11, 1 },
|
|
{ "ADDR_MIRROR_RP2_SEC", 10, 1 },
|
|
{ "ADDR_MIRROR_RP3_PRI", 9, 1 },
|
|
{ "ADDR_MIRROR_RP3_SEC", 8, 1 },
|
|
{ "RANK_GROUPING", 6, 2 },
|
|
{ "ADDR_MIRROR_A3_A4", 5, 1 },
|
|
{ "ADDR_MIRROR_A5_A6", 4, 1 },
|
|
{ "ADDR_MIRROR_A7_A8", 3, 1 },
|
|
{ "ADDR_MIRROR_A11_A13", 2, 1 },
|
|
{ "ADDR_MIRROR_BA0_BA1", 1, 1 },
|
|
{ "ADDR_MIRROR_BG0_BG1", 0, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x45800, 0 },
|
|
{ "BIT_ENABLE_0_11", 4, 12 },
|
|
{ "BIT_ENABLE_12_15", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x45804, 0 },
|
|
{ "DI_ADR0_ADR1", 15, 1 },
|
|
{ "DI_ADR2_ADR3", 14, 1 },
|
|
{ "DI_ADR4_ADR5", 13, 1 },
|
|
{ "DI_ADR6_ADR7", 12, 1 },
|
|
{ "DI_ADR8_ADR9", 11, 1 },
|
|
{ "DI_ADR10_ADR11", 10, 1 },
|
|
{ "DI_ADR12_ADR13", 9, 1 },
|
|
{ "DI_ADR14_ADR15", 8, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY0", 0x45810, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY1", 0x45814, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY2", 0x45818, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY3", 0x4581c, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY4", 0x45820, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY5", 0x45824, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY6", 0x45828, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY7", 0x4582c, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x45830, 0 },
|
|
{ "ADR_TEST_LANE_PAIR_FAIL", 8, 8 },
|
|
{ "ADR_TEST_DATA_EN", 7, 1 },
|
|
{ "ADR_TEST_MODE", 5, 2 },
|
|
{ "ADR_TEST_4TO1_MODE", 4, 1 },
|
|
{ "ADR_TEST_RESET", 3, 1 },
|
|
{ "ADR_TEST_GEN_EN", 2, 1 },
|
|
{ "ADR_TEST_CLEAR_ERROR", 1, 1 },
|
|
{ "ADR_TEST_CHECK_EN", 0, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x45840, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x45844, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x45848, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4584c, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x45850, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x45854, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x45858, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4585c, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x45880, 0 },
|
|
{ "SLICE_SEL_REG_BITS0_1", 14, 2 },
|
|
{ "SLICE_SEL_REG_BITS2_3", 12, 2 },
|
|
{ "SLICE_SEL_REG_BITS4_5", 10, 2 },
|
|
{ "SLICE_SEL_REG_BITS6_7", 8, 2 },
|
|
{ "SLICE_SEL_REG_BITS8_9", 6, 2 },
|
|
{ "SLICE_SEL_REG_BITS10_11", 4, 2 },
|
|
{ "SLICE_SEL_REG_BITS12_13", 2, 2 },
|
|
{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x45884, 0 },
|
|
{ "SLICE_SEL_REG_BITS0_1", 14, 2 },
|
|
{ "SLICE_SEL_REG_BITS2_3", 12, 2 },
|
|
{ "SLICE_SEL_REG_BITS4_5", 10, 2 },
|
|
{ "SLICE_SEL_REG_BITS6_7", 8, 2 },
|
|
{ "SLICE_SEL_REG_BITS8_9", 6, 2 },
|
|
{ "SLICE_SEL_REG_BITS10_11", 4, 2 },
|
|
{ "SLICE_SEL_REG_BITS12_13", 2, 2 },
|
|
{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x45860, 0 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x458a0, 0 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x458a4, 0 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x45868, 0 },
|
|
{ "SLEW_CTL0", 12, 4 },
|
|
{ "SLEW_CTL1", 8, 4 },
|
|
{ "SLEW_CTL2", 4, 4 },
|
|
{ "SLEW_CTL3", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x458a8, 0 },
|
|
{ "SLEW_CTL_SEL_BITS0_1", 14, 2 },
|
|
{ "SLEW_CTL_SEL_BITS2_3", 12, 2 },
|
|
{ "SLEW_CTL_SEL_BITS4_5", 10, 2 },
|
|
{ "SLEW_CTL_SEL_BITS6_7", 8, 2 },
|
|
{ "SLEW_CTL_SEL_BITS8_9", 6, 2 },
|
|
{ "SLEW_CTL_SEL_BITS10_11", 4, 2 },
|
|
{ "SLEW_CTL_SEL_BITS12_13", 2, 2 },
|
|
{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x458ac, 0 },
|
|
{ "SLEW_CTL_SEL_BITS0_1", 14, 2 },
|
|
{ "SLEW_CTL_SEL_BITS2_3", 12, 2 },
|
|
{ "SLEW_CTL_SEL_BITS4_5", 10, 2 },
|
|
{ "SLEW_CTL_SEL_BITS6_7", 8, 2 },
|
|
{ "SLEW_CTL_SEL_BITS8_9", 6, 2 },
|
|
{ "SLEW_CTL_SEL_BITS10_11", 4, 2 },
|
|
{ "SLEW_CTL_SEL_BITS12_13", 2, 2 },
|
|
{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x458b0, 0 },
|
|
{ "ADR_LANE_0_11_PD", 4, 12 },
|
|
{ "ADR_LANE_12_15_PD", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x45a00, 0 },
|
|
{ "BIT_ENABLE_0_11", 4, 12 },
|
|
{ "BIT_ENABLE_12_15", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x45a04, 0 },
|
|
{ "DI_ADR0_ADR1", 15, 1 },
|
|
{ "DI_ADR2_ADR3", 14, 1 },
|
|
{ "DI_ADR4_ADR5", 13, 1 },
|
|
{ "DI_ADR6_ADR7", 12, 1 },
|
|
{ "DI_ADR8_ADR9", 11, 1 },
|
|
{ "DI_ADR10_ADR11", 10, 1 },
|
|
{ "DI_ADR12_ADR13", 9, 1 },
|
|
{ "DI_ADR14_ADR15", 8, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY0", 0x45a10, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY1", 0x45a14, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY2", 0x45a18, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY3", 0x45a1c, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY4", 0x45a20, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY5", 0x45a24, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY6", 0x45a28, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY7", 0x45a2c, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x45a30, 0 },
|
|
{ "ADR_TEST_LANE_PAIR_FAIL", 8, 8 },
|
|
{ "ADR_TEST_DATA_EN", 7, 1 },
|
|
{ "ADR_TEST_MODE", 5, 2 },
|
|
{ "ADR_TEST_4TO1_MODE", 4, 1 },
|
|
{ "ADR_TEST_RESET", 3, 1 },
|
|
{ "ADR_TEST_GEN_EN", 2, 1 },
|
|
{ "ADR_TEST_CLEAR_ERROR", 1, 1 },
|
|
{ "ADR_TEST_CHECK_EN", 0, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x45a40, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x45a44, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x45a48, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x45a4c, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x45a50, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x45a54, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x45a58, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x45a5c, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x45a80, 0 },
|
|
{ "SLICE_SEL_REG_BITS0_1", 14, 2 },
|
|
{ "SLICE_SEL_REG_BITS2_3", 12, 2 },
|
|
{ "SLICE_SEL_REG_BITS4_5", 10, 2 },
|
|
{ "SLICE_SEL_REG_BITS6_7", 8, 2 },
|
|
{ "SLICE_SEL_REG_BITS8_9", 6, 2 },
|
|
{ "SLICE_SEL_REG_BITS10_11", 4, 2 },
|
|
{ "SLICE_SEL_REG_BITS12_13", 2, 2 },
|
|
{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x45a84, 0 },
|
|
{ "SLICE_SEL_REG_BITS0_1", 14, 2 },
|
|
{ "SLICE_SEL_REG_BITS2_3", 12, 2 },
|
|
{ "SLICE_SEL_REG_BITS4_5", 10, 2 },
|
|
{ "SLICE_SEL_REG_BITS6_7", 8, 2 },
|
|
{ "SLICE_SEL_REG_BITS8_9", 6, 2 },
|
|
{ "SLICE_SEL_REG_BITS10_11", 4, 2 },
|
|
{ "SLICE_SEL_REG_BITS12_13", 2, 2 },
|
|
{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x45a60, 0 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x45aa0, 0 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x45aa4, 0 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x45a68, 0 },
|
|
{ "SLEW_CTL0", 12, 4 },
|
|
{ "SLEW_CTL1", 8, 4 },
|
|
{ "SLEW_CTL2", 4, 4 },
|
|
{ "SLEW_CTL3", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x45aa8, 0 },
|
|
{ "SLEW_CTL_SEL_BITS0_1", 14, 2 },
|
|
{ "SLEW_CTL_SEL_BITS2_3", 12, 2 },
|
|
{ "SLEW_CTL_SEL_BITS4_5", 10, 2 },
|
|
{ "SLEW_CTL_SEL_BITS6_7", 8, 2 },
|
|
{ "SLEW_CTL_SEL_BITS8_9", 6, 2 },
|
|
{ "SLEW_CTL_SEL_BITS10_11", 4, 2 },
|
|
{ "SLEW_CTL_SEL_BITS12_13", 2, 2 },
|
|
{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x45aac, 0 },
|
|
{ "SLEW_CTL_SEL_BITS0_1", 14, 2 },
|
|
{ "SLEW_CTL_SEL_BITS2_3", 12, 2 },
|
|
{ "SLEW_CTL_SEL_BITS4_5", 10, 2 },
|
|
{ "SLEW_CTL_SEL_BITS6_7", 8, 2 },
|
|
{ "SLEW_CTL_SEL_BITS8_9", 6, 2 },
|
|
{ "SLEW_CTL_SEL_BITS10_11", 4, 2 },
|
|
{ "SLEW_CTL_SEL_BITS12_13", 2, 2 },
|
|
{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x45ab0, 0 },
|
|
{ "ADR_LANE_0_11_PD", 4, 12 },
|
|
{ "ADR_LANE_12_15_PD", 0, 4 },
|
|
{ "MC_DDRPHY_AD32S_PLL_VREG_CONFIG_0", 0x460c0, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_AD32S_PLL_VREG_CONFIG_1", 0x460c4, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "VREG_VREGSPARE", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "INTERP_SIG_SLEW_0_3", 1, 4 },
|
|
{ "ANALOG_WRAPON", 0, 1 },
|
|
{ "MC_DDRPHY_AD32S_SYSCLK_CNTL_PR", 0x460c8, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESE", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "CE0DLTVCC", 0, 2 },
|
|
{ "MC_DDRPHY_AD32S_MCCLK_WRCLK_PR_STATIC_OFFSET", 0x460cc, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_AD32S_SYSCLK_PR_VALUE_RO", 0x460d0, 0 },
|
|
{ "SLEW_LATE_SAMPLE", 15, 1 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "BB_LOCK", 7, 1 },
|
|
{ "SLEW_EARLY_SAMPLE", 6, 1 },
|
|
{ "SLEW_DONE_STATUS", 4, 2 },
|
|
{ "SLEW_CNTL", 0, 4 },
|
|
{ "MC_DDRPHY_AD32S_OUTPUT_FORCE_ATEST_CNTL", 0x460d4, 0 },
|
|
{ "FLUSH", 15, 1 },
|
|
{ "FORCE_EN", 14, 1 },
|
|
{ "AD32S_HS_PROBE_A_SEL", 8, 4 },
|
|
{ "AD32S_HS_PROBE_B_SEL", 4, 4 },
|
|
{ "ATEST1CTL0", 3, 1 },
|
|
{ "ATEST1CTL1", 2, 1 },
|
|
{ "ATEST1CTL2", 1, 1 },
|
|
{ "ATEST1CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE0", 0x460d8, 0 },
|
|
{ "MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE1", 0x460dc, 0 },
|
|
{ "MC_DDRPHY_AD32S_POWERDOWN_1", 0x460e0, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_AD32S_SLEW_CAL_CNTL", 0x460e4, 0 },
|
|
{ "SLEW_CAL_ENABLE", 15, 1 },
|
|
{ "SLEW_CAL_START", 14, 1 },
|
|
{ "SLEW_CAL_OVERRIDE_EN", 12, 1 },
|
|
{ "SLEW_CAL_OVERRIDE", 8, 4 },
|
|
{ "SLEW_TARGET_PR_OFFSET", 0, 5 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44000, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44004, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "DP18_WRAPSEL", 5, 1 },
|
|
{ "HW_VALUE", 4, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x441f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x441f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44008, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4400c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44010, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44014, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x441f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44018, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4401c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x441cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "BB_LOCK", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4417c, 0 },
|
|
{ "FAIL_PASS_VALUE", 8, 7 },
|
|
{ "PASS_FAIL_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44178, 0 },
|
|
{ "WRCLK_CALIB_DONE", 15, 1 },
|
|
{ "VALUE_UPDATED", 14, 1 },
|
|
{ "FAIL_PASS_V", 13, 1 },
|
|
{ "PASS_FAIL_V", 12, 1 },
|
|
{ "FP_PF_EDGE_NF", 11, 1 },
|
|
{ "NON_SYMETRIC", 10, 1 },
|
|
{ "FULL_RANGE", 8, 1 },
|
|
{ "QUAD3_EDGES", 7, 1 },
|
|
{ "QUAD2_EDGES", 6, 1 },
|
|
{ "QUAD1_EDGES", 5, 1 },
|
|
{ "QUAD0_EDGES", 4, 1 },
|
|
{ "QUAD3_CAVEAT", 3, 1 },
|
|
{ "QUAD2_CAVEAT", 2, 1 },
|
|
{ "QUAD1_CAVEAT", 1, 1 },
|
|
{ "QUAD0_CAVEAT", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44058, 0 },
|
|
{ "PRBS_WAIT", 14, 2 },
|
|
{ "PRBS_SYNC_EARLY", 13, 1 },
|
|
{ "RD_DELAY_EARLY", 12, 1 },
|
|
{ "SS_QUAD_CAL", 10, 1 },
|
|
{ "SS_QUAD", 8, 2 },
|
|
{ "SS_RD_DELAY", 7, 1 },
|
|
{ "FORCE_HI_Z", 6, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4407c, 0 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x441d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x440c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x440c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44024, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44170, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44174, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x440e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x440e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x440e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x440ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x440f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x440f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x440f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x440fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44100, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44104, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44108, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4410c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44110, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44114, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44118, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4411c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44120, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44124, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44128, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4412c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44130, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44134, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44138, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4413c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44140, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44144, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44148, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4414c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44150, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44154, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44158, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4415c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44160, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44164, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44168, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4416c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44030, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44034, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x441c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x441c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x441c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44180, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44184, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44188, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4418c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44190, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44194, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44198, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4419c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x441a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x441a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x441a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x441ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44028, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44038, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4403c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44040, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44044, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4404c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44050, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44054, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4405c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "WR_LVL_DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44060, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "WR_CNTR_DONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44064, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44068, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4406c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44070, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "DQS_REC_LOW_POWER", 11, 1 },
|
|
{ "DQ_REC_LOW_POWER", 10, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "ADVANCE_PR_VALUE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x441d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x441dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x441e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x441e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x441e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x441ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x441d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44074, 0 },
|
|
{ "CHECKER_ENABLE", 15, 1 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "DP18_DFT_ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44020, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x440c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x440cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x440d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44078, 0 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x440d4, 0 },
|
|
{ "DQS_ALIGN_SM", 11, 5 },
|
|
{ "DQS_ALIGN_CNTR", 7, 4 },
|
|
{ "ITERATION_CNTR", 6, 1 },
|
|
{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x440d8, 0 },
|
|
{ "CALIBRATE_BIT", 13, 3 },
|
|
{ "DQS_ALIGN_QUAD", 11, 2 },
|
|
{ "DQS_QUAD_CONFIG", 8, 3 },
|
|
{ "OPERATE_MODE", 4, 4 },
|
|
{ "EN_DQS_OFFSET", 3, 1 },
|
|
{ "DQS_ALIGN_JITTER", 2, 1 },
|
|
{ "DIS_CLK_GATE", 1, 1 },
|
|
{ "MAX_DQS_ITER", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x441b4, 0 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x441b8, 0 },
|
|
{ "APPROACH_ALIGNMENT", 15, 1 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x440dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4402c, 0 },
|
|
{ "DP18_HS_PROBE_A_SEL", 11, 5 },
|
|
{ "DP18_HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x441fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "VCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44048, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DQS_ALIGN_BY_QUAD", 4, 1 },
|
|
{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x441bc, 0 },
|
|
{ "QUAD0_PWR_CTL", 12, 4 },
|
|
{ "QUAD1_PWR_CTL", 8, 4 },
|
|
{ "QUAD2_PWR_CTL", 4, 4 },
|
|
{ "QUAD3_PWR_CTL", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44200, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44204, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "DP18_WRAPSEL", 5, 1 },
|
|
{ "HW_VALUE", 4, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x443f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x443f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44208, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4420c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44210, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44214, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x443f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44218, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4421c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x443cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "BB_LOCK", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4437c, 0 },
|
|
{ "FAIL_PASS_VALUE", 8, 7 },
|
|
{ "PASS_FAIL_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44378, 0 },
|
|
{ "WRCLK_CALIB_DONE", 15, 1 },
|
|
{ "VALUE_UPDATED", 14, 1 },
|
|
{ "FAIL_PASS_V", 13, 1 },
|
|
{ "PASS_FAIL_V", 12, 1 },
|
|
{ "FP_PF_EDGE_NF", 11, 1 },
|
|
{ "NON_SYMETRIC", 10, 1 },
|
|
{ "FULL_RANGE", 8, 1 },
|
|
{ "QUAD3_EDGES", 7, 1 },
|
|
{ "QUAD2_EDGES", 6, 1 },
|
|
{ "QUAD1_EDGES", 5, 1 },
|
|
{ "QUAD0_EDGES", 4, 1 },
|
|
{ "QUAD3_CAVEAT", 3, 1 },
|
|
{ "QUAD2_CAVEAT", 2, 1 },
|
|
{ "QUAD1_CAVEAT", 1, 1 },
|
|
{ "QUAD0_CAVEAT", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44258, 0 },
|
|
{ "PRBS_WAIT", 14, 2 },
|
|
{ "PRBS_SYNC_EARLY", 13, 1 },
|
|
{ "RD_DELAY_EARLY", 12, 1 },
|
|
{ "SS_QUAD_CAL", 10, 1 },
|
|
{ "SS_QUAD", 8, 2 },
|
|
{ "SS_RD_DELAY", 7, 1 },
|
|
{ "FORCE_HI_Z", 6, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4427c, 0 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x443d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x442c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x442c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44224, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44370, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44374, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x442e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x442e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x442e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x442ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x442f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x442f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x442f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x442fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44300, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44304, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44308, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4430c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44310, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44314, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44318, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4431c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44320, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44324, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44328, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4432c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44330, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44334, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44338, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4433c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44340, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44344, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44348, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4434c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44350, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44354, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44358, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4435c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44360, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44364, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44368, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4436c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44230, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44234, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x443c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x443c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x443c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44380, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44384, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44388, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4438c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44390, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44394, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44398, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4439c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x443a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x443a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x443a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x443ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44228, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44238, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4423c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44240, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44244, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4424c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44250, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44254, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4425c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "WR_LVL_DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44260, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "WR_CNTR_DONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44264, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44268, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4426c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44270, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "DQS_REC_LOW_POWER", 11, 1 },
|
|
{ "DQ_REC_LOW_POWER", 10, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "ADVANCE_PR_VALUE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x443d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x443dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x443e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x443e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x443e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x443ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x443d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44274, 0 },
|
|
{ "CHECKER_ENABLE", 15, 1 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "DP18_DFT_ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44220, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x442c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x442cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x442d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44278, 0 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x442d4, 0 },
|
|
{ "DQS_ALIGN_SM", 11, 5 },
|
|
{ "DQS_ALIGN_CNTR", 7, 4 },
|
|
{ "ITERATION_CNTR", 6, 1 },
|
|
{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x442d8, 0 },
|
|
{ "CALIBRATE_BIT", 13, 3 },
|
|
{ "DQS_ALIGN_QUAD", 11, 2 },
|
|
{ "DQS_QUAD_CONFIG", 8, 3 },
|
|
{ "OPERATE_MODE", 4, 4 },
|
|
{ "EN_DQS_OFFSET", 3, 1 },
|
|
{ "DQS_ALIGN_JITTER", 2, 1 },
|
|
{ "DIS_CLK_GATE", 1, 1 },
|
|
{ "MAX_DQS_ITER", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x443b4, 0 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x443b8, 0 },
|
|
{ "APPROACH_ALIGNMENT", 15, 1 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x442dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4422c, 0 },
|
|
{ "DP18_HS_PROBE_A_SEL", 11, 5 },
|
|
{ "DP18_HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x443fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "VCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44248, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DQS_ALIGN_BY_QUAD", 4, 1 },
|
|
{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x443bc, 0 },
|
|
{ "QUAD0_PWR_CTL", 12, 4 },
|
|
{ "QUAD1_PWR_CTL", 8, 4 },
|
|
{ "QUAD2_PWR_CTL", 4, 4 },
|
|
{ "QUAD3_PWR_CTL", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44400, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44404, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "DP18_WRAPSEL", 5, 1 },
|
|
{ "HW_VALUE", 4, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x445f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x445f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44408, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4440c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44410, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44414, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x445f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44418, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4441c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x445cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "BB_LOCK", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4457c, 0 },
|
|
{ "FAIL_PASS_VALUE", 8, 7 },
|
|
{ "PASS_FAIL_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44578, 0 },
|
|
{ "WRCLK_CALIB_DONE", 15, 1 },
|
|
{ "VALUE_UPDATED", 14, 1 },
|
|
{ "FAIL_PASS_V", 13, 1 },
|
|
{ "PASS_FAIL_V", 12, 1 },
|
|
{ "FP_PF_EDGE_NF", 11, 1 },
|
|
{ "NON_SYMETRIC", 10, 1 },
|
|
{ "FULL_RANGE", 8, 1 },
|
|
{ "QUAD3_EDGES", 7, 1 },
|
|
{ "QUAD2_EDGES", 6, 1 },
|
|
{ "QUAD1_EDGES", 5, 1 },
|
|
{ "QUAD0_EDGES", 4, 1 },
|
|
{ "QUAD3_CAVEAT", 3, 1 },
|
|
{ "QUAD2_CAVEAT", 2, 1 },
|
|
{ "QUAD1_CAVEAT", 1, 1 },
|
|
{ "QUAD0_CAVEAT", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44458, 0 },
|
|
{ "PRBS_WAIT", 14, 2 },
|
|
{ "PRBS_SYNC_EARLY", 13, 1 },
|
|
{ "RD_DELAY_EARLY", 12, 1 },
|
|
{ "SS_QUAD_CAL", 10, 1 },
|
|
{ "SS_QUAD", 8, 2 },
|
|
{ "SS_RD_DELAY", 7, 1 },
|
|
{ "FORCE_HI_Z", 6, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4447c, 0 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x445d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x444c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x444c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44424, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44570, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44574, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x444e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x444e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x444e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x444ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x444f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x444f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x444f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x444fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44500, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44504, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44508, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4450c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44510, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44514, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44518, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4451c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44520, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44524, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44528, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4452c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44530, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44534, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44538, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4453c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44540, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44544, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44548, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4454c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44550, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44554, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44558, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4455c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44560, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44564, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44568, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4456c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44430, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44434, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x445c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x445c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x445c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44580, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44584, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44588, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4458c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44590, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44594, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44598, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4459c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x445a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x445a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x445a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x445ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44428, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44438, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4443c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44440, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44444, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4444c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44450, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44454, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4445c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "WR_LVL_DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44460, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "WR_CNTR_DONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44464, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44468, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4446c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44470, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "DQS_REC_LOW_POWER", 11, 1 },
|
|
{ "DQ_REC_LOW_POWER", 10, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "ADVANCE_PR_VALUE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x445d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x445dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x445e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x445e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x445e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x445ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x445d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44474, 0 },
|
|
{ "CHECKER_ENABLE", 15, 1 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "DP18_DFT_ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44420, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x444c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x444cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x444d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44478, 0 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x444d4, 0 },
|
|
{ "DQS_ALIGN_SM", 11, 5 },
|
|
{ "DQS_ALIGN_CNTR", 7, 4 },
|
|
{ "ITERATION_CNTR", 6, 1 },
|
|
{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x444d8, 0 },
|
|
{ "CALIBRATE_BIT", 13, 3 },
|
|
{ "DQS_ALIGN_QUAD", 11, 2 },
|
|
{ "DQS_QUAD_CONFIG", 8, 3 },
|
|
{ "OPERATE_MODE", 4, 4 },
|
|
{ "EN_DQS_OFFSET", 3, 1 },
|
|
{ "DQS_ALIGN_JITTER", 2, 1 },
|
|
{ "DIS_CLK_GATE", 1, 1 },
|
|
{ "MAX_DQS_ITER", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x445b4, 0 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x445b8, 0 },
|
|
{ "APPROACH_ALIGNMENT", 15, 1 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x444dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4442c, 0 },
|
|
{ "DP18_HS_PROBE_A_SEL", 11, 5 },
|
|
{ "DP18_HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x445fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "VCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44448, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DQS_ALIGN_BY_QUAD", 4, 1 },
|
|
{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x445bc, 0 },
|
|
{ "QUAD0_PWR_CTL", 12, 4 },
|
|
{ "QUAD1_PWR_CTL", 8, 4 },
|
|
{ "QUAD2_PWR_CTL", 4, 4 },
|
|
{ "QUAD3_PWR_CTL", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44600, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44604, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "DP18_WRAPSEL", 5, 1 },
|
|
{ "HW_VALUE", 4, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x447f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x447f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44608, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4460c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44610, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44614, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x447f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44618, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4461c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x447cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "BB_LOCK", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4477c, 0 },
|
|
{ "FAIL_PASS_VALUE", 8, 7 },
|
|
{ "PASS_FAIL_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44778, 0 },
|
|
{ "WRCLK_CALIB_DONE", 15, 1 },
|
|
{ "VALUE_UPDATED", 14, 1 },
|
|
{ "FAIL_PASS_V", 13, 1 },
|
|
{ "PASS_FAIL_V", 12, 1 },
|
|
{ "FP_PF_EDGE_NF", 11, 1 },
|
|
{ "NON_SYMETRIC", 10, 1 },
|
|
{ "FULL_RANGE", 8, 1 },
|
|
{ "QUAD3_EDGES", 7, 1 },
|
|
{ "QUAD2_EDGES", 6, 1 },
|
|
{ "QUAD1_EDGES", 5, 1 },
|
|
{ "QUAD0_EDGES", 4, 1 },
|
|
{ "QUAD3_CAVEAT", 3, 1 },
|
|
{ "QUAD2_CAVEAT", 2, 1 },
|
|
{ "QUAD1_CAVEAT", 1, 1 },
|
|
{ "QUAD0_CAVEAT", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44658, 0 },
|
|
{ "PRBS_WAIT", 14, 2 },
|
|
{ "PRBS_SYNC_EARLY", 13, 1 },
|
|
{ "RD_DELAY_EARLY", 12, 1 },
|
|
{ "SS_QUAD_CAL", 10, 1 },
|
|
{ "SS_QUAD", 8, 2 },
|
|
{ "SS_RD_DELAY", 7, 1 },
|
|
{ "FORCE_HI_Z", 6, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4467c, 0 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x447d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x446c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x446c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44624, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44770, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44774, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x446e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x446e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x446e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x446ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x446f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x446f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x446f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x446fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44700, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44704, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44708, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4470c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44710, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44714, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44718, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4471c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44720, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44724, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44728, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4472c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44730, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44734, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44738, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4473c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44740, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44744, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44748, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4474c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44750, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44754, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44758, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4475c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44760, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44764, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44768, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4476c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44630, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44634, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x447c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x447c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x447c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44780, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44784, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44788, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4478c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44790, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44794, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44798, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4479c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x447a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x447a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x447a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x447ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44628, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44638, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4463c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44640, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44644, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4464c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44650, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44654, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4465c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "WR_LVL_DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44660, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "WR_CNTR_DONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44664, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44668, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4466c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44670, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "DQS_REC_LOW_POWER", 11, 1 },
|
|
{ "DQ_REC_LOW_POWER", 10, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "ADVANCE_PR_VALUE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x447d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x447dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x447e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x447e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x447e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x447ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x447d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44674, 0 },
|
|
{ "CHECKER_ENABLE", 15, 1 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "DP18_DFT_ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44620, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x446c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x446cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x446d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44678, 0 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x446d4, 0 },
|
|
{ "DQS_ALIGN_SM", 11, 5 },
|
|
{ "DQS_ALIGN_CNTR", 7, 4 },
|
|
{ "ITERATION_CNTR", 6, 1 },
|
|
{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x446d8, 0 },
|
|
{ "CALIBRATE_BIT", 13, 3 },
|
|
{ "DQS_ALIGN_QUAD", 11, 2 },
|
|
{ "DQS_QUAD_CONFIG", 8, 3 },
|
|
{ "OPERATE_MODE", 4, 4 },
|
|
{ "EN_DQS_OFFSET", 3, 1 },
|
|
{ "DQS_ALIGN_JITTER", 2, 1 },
|
|
{ "DIS_CLK_GATE", 1, 1 },
|
|
{ "MAX_DQS_ITER", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x447b4, 0 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x447b8, 0 },
|
|
{ "APPROACH_ALIGNMENT", 15, 1 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x446dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4462c, 0 },
|
|
{ "DP18_HS_PROBE_A_SEL", 11, 5 },
|
|
{ "DP18_HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x447fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "VCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44648, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DQS_ALIGN_BY_QUAD", 4, 1 },
|
|
{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x447bc, 0 },
|
|
{ "QUAD0_PWR_CTL", 12, 4 },
|
|
{ "QUAD1_PWR_CTL", 8, 4 },
|
|
{ "QUAD2_PWR_CTL", 4, 4 },
|
|
{ "QUAD3_PWR_CTL", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44800, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44804, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "DP18_WRAPSEL", 5, 1 },
|
|
{ "HW_VALUE", 4, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x449f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x449f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44808, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4480c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44810, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44814, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x449f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44818, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4481c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x449cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "BB_LOCK", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4497c, 0 },
|
|
{ "FAIL_PASS_VALUE", 8, 7 },
|
|
{ "PASS_FAIL_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44978, 0 },
|
|
{ "WRCLK_CALIB_DONE", 15, 1 },
|
|
{ "VALUE_UPDATED", 14, 1 },
|
|
{ "FAIL_PASS_V", 13, 1 },
|
|
{ "PASS_FAIL_V", 12, 1 },
|
|
{ "FP_PF_EDGE_NF", 11, 1 },
|
|
{ "NON_SYMETRIC", 10, 1 },
|
|
{ "FULL_RANGE", 8, 1 },
|
|
{ "QUAD3_EDGES", 7, 1 },
|
|
{ "QUAD2_EDGES", 6, 1 },
|
|
{ "QUAD1_EDGES", 5, 1 },
|
|
{ "QUAD0_EDGES", 4, 1 },
|
|
{ "QUAD3_CAVEAT", 3, 1 },
|
|
{ "QUAD2_CAVEAT", 2, 1 },
|
|
{ "QUAD1_CAVEAT", 1, 1 },
|
|
{ "QUAD0_CAVEAT", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44858, 0 },
|
|
{ "PRBS_WAIT", 14, 2 },
|
|
{ "PRBS_SYNC_EARLY", 13, 1 },
|
|
{ "RD_DELAY_EARLY", 12, 1 },
|
|
{ "SS_QUAD_CAL", 10, 1 },
|
|
{ "SS_QUAD", 8, 2 },
|
|
{ "SS_RD_DELAY", 7, 1 },
|
|
{ "FORCE_HI_Z", 6, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4487c, 0 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x449d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x448c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x448c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44824, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44970, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44974, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x448e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x448e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x448e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x448ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x448f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x448f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x448f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x448fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44900, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44904, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44908, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4490c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44910, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44914, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44918, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4491c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44920, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44924, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44928, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4492c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44930, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44934, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44938, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4493c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44940, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44944, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44948, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4494c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44950, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44954, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44958, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4495c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44960, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44964, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44968, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4496c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44830, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44834, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x449c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x449c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x449c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44980, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44984, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44988, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4498c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44990, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44994, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44998, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4499c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x449a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x449a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x449a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x449ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44828, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44838, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4483c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44840, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44844, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4484c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44850, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44854, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4485c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "WR_LVL_DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44860, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "WR_CNTR_DONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44864, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44868, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4486c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44870, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "DQS_REC_LOW_POWER", 11, 1 },
|
|
{ "DQ_REC_LOW_POWER", 10, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "ADVANCE_PR_VALUE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x449d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x449dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x449e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x449e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x449e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x449ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x449d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44874, 0 },
|
|
{ "CHECKER_ENABLE", 15, 1 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "DP18_DFT_ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44820, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x448c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x448cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x448d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44878, 0 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x448d4, 0 },
|
|
{ "DQS_ALIGN_SM", 11, 5 },
|
|
{ "DQS_ALIGN_CNTR", 7, 4 },
|
|
{ "ITERATION_CNTR", 6, 1 },
|
|
{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x448d8, 0 },
|
|
{ "CALIBRATE_BIT", 13, 3 },
|
|
{ "DQS_ALIGN_QUAD", 11, 2 },
|
|
{ "DQS_QUAD_CONFIG", 8, 3 },
|
|
{ "OPERATE_MODE", 4, 4 },
|
|
{ "EN_DQS_OFFSET", 3, 1 },
|
|
{ "DQS_ALIGN_JITTER", 2, 1 },
|
|
{ "DIS_CLK_GATE", 1, 1 },
|
|
{ "MAX_DQS_ITER", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x449b4, 0 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x449b8, 0 },
|
|
{ "APPROACH_ALIGNMENT", 15, 1 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x448dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4482c, 0 },
|
|
{ "DP18_HS_PROBE_A_SEL", 11, 5 },
|
|
{ "DP18_HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x449fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "VCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44848, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DQS_ALIGN_BY_QUAD", 4, 1 },
|
|
{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x449bc, 0 },
|
|
{ "QUAD0_PWR_CTL", 12, 4 },
|
|
{ "QUAD1_PWR_CTL", 8, 4 },
|
|
{ "QUAD2_PWR_CTL", 4, 4 },
|
|
{ "QUAD3_PWR_CTL", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44a00, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44a04, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "DP18_WRAPSEL", 5, 1 },
|
|
{ "HW_VALUE", 4, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x44bf0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x44bf4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44a08, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x44a0c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44a10, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44a14, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x44bf8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44a18, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x44a1c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x44bcc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "BB_LOCK", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x44b7c, 0 },
|
|
{ "FAIL_PASS_VALUE", 8, 7 },
|
|
{ "PASS_FAIL_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44b78, 0 },
|
|
{ "WRCLK_CALIB_DONE", 15, 1 },
|
|
{ "VALUE_UPDATED", 14, 1 },
|
|
{ "FAIL_PASS_V", 13, 1 },
|
|
{ "PASS_FAIL_V", 12, 1 },
|
|
{ "FP_PF_EDGE_NF", 11, 1 },
|
|
{ "NON_SYMETRIC", 10, 1 },
|
|
{ "FULL_RANGE", 8, 1 },
|
|
{ "QUAD3_EDGES", 7, 1 },
|
|
{ "QUAD2_EDGES", 6, 1 },
|
|
{ "QUAD1_EDGES", 5, 1 },
|
|
{ "QUAD0_EDGES", 4, 1 },
|
|
{ "QUAD3_CAVEAT", 3, 1 },
|
|
{ "QUAD2_CAVEAT", 2, 1 },
|
|
{ "QUAD1_CAVEAT", 1, 1 },
|
|
{ "QUAD0_CAVEAT", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44a58, 0 },
|
|
{ "PRBS_WAIT", 14, 2 },
|
|
{ "PRBS_SYNC_EARLY", 13, 1 },
|
|
{ "RD_DELAY_EARLY", 12, 1 },
|
|
{ "SS_QUAD_CAL", 10, 1 },
|
|
{ "SS_QUAD", 8, 2 },
|
|
{ "SS_RD_DELAY", 7, 1 },
|
|
{ "FORCE_HI_Z", 6, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x44a7c, 0 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x44bd0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x44ac0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x44ac4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44a24, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44b70, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44b74, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x44ae0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x44ae4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x44ae8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x44aec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x44af0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x44af4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x44af8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x44afc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44b00, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44b04, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44b08, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x44b0c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44b10, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44b14, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44b18, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x44b1c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44b20, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44b24, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44b28, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x44b2c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44b30, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44b34, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44b38, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x44b3c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44b40, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44b44, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44b48, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x44b4c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44b50, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44b54, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44b58, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x44b5c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44b60, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44b64, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44b68, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x44b6c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44a30, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44a34, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x44bc0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x44bc4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x44bc8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44b80, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44b84, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44b88, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x44b8c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44b90, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44b94, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44b98, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x44b9c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x44ba0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x44ba4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x44ba8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x44bac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44a28, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44a38, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x44a3c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44a40, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44a44, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x44a4c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44a50, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44a54, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x44a5c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "WR_LVL_DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44a60, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "WR_CNTR_DONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44a64, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44a68, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x44a6c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44a70, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "DQS_REC_LOW_POWER", 11, 1 },
|
|
{ "DQ_REC_LOW_POWER", 10, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "ADVANCE_PR_VALUE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x44bd8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x44bdc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x44be0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x44be8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x44be4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x44bec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x44bd4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44a74, 0 },
|
|
{ "CHECKER_ENABLE", 15, 1 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "DP18_DFT_ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44a20, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x44ac8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x44acc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x44ad0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44a78, 0 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x44ad4, 0 },
|
|
{ "DQS_ALIGN_SM", 11, 5 },
|
|
{ "DQS_ALIGN_CNTR", 7, 4 },
|
|
{ "ITERATION_CNTR", 6, 1 },
|
|
{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x44ad8, 0 },
|
|
{ "CALIBRATE_BIT", 13, 3 },
|
|
{ "DQS_ALIGN_QUAD", 11, 2 },
|
|
{ "DQS_QUAD_CONFIG", 8, 3 },
|
|
{ "OPERATE_MODE", 4, 4 },
|
|
{ "EN_DQS_OFFSET", 3, 1 },
|
|
{ "DQS_ALIGN_JITTER", 2, 1 },
|
|
{ "DIS_CLK_GATE", 1, 1 },
|
|
{ "MAX_DQS_ITER", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x44bb4, 0 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x44bb8, 0 },
|
|
{ "APPROACH_ALIGNMENT", 15, 1 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x44adc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x44a2c, 0 },
|
|
{ "DP18_HS_PROBE_A_SEL", 11, 5 },
|
|
{ "DP18_HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x44bfc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "VCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44a48, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DQS_ALIGN_BY_QUAD", 4, 1 },
|
|
{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x44bbc, 0 },
|
|
{ "QUAD0_PWR_CTL", 12, 4 },
|
|
{ "QUAD1_PWR_CTL", 8, 4 },
|
|
{ "QUAD2_PWR_CTL", 4, 4 },
|
|
{ "QUAD3_PWR_CTL", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44c00, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44c04, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "DP18_WRAPSEL", 5, 1 },
|
|
{ "HW_VALUE", 4, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x44df0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x44df4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44c08, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x44c0c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44c10, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44c14, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x44df8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44c18, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x44c1c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x44dcc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "BB_LOCK", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x44d7c, 0 },
|
|
{ "FAIL_PASS_VALUE", 8, 7 },
|
|
{ "PASS_FAIL_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44d78, 0 },
|
|
{ "WRCLK_CALIB_DONE", 15, 1 },
|
|
{ "VALUE_UPDATED", 14, 1 },
|
|
{ "FAIL_PASS_V", 13, 1 },
|
|
{ "PASS_FAIL_V", 12, 1 },
|
|
{ "FP_PF_EDGE_NF", 11, 1 },
|
|
{ "NON_SYMETRIC", 10, 1 },
|
|
{ "FULL_RANGE", 8, 1 },
|
|
{ "QUAD3_EDGES", 7, 1 },
|
|
{ "QUAD2_EDGES", 6, 1 },
|
|
{ "QUAD1_EDGES", 5, 1 },
|
|
{ "QUAD0_EDGES", 4, 1 },
|
|
{ "QUAD3_CAVEAT", 3, 1 },
|
|
{ "QUAD2_CAVEAT", 2, 1 },
|
|
{ "QUAD1_CAVEAT", 1, 1 },
|
|
{ "QUAD0_CAVEAT", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44c58, 0 },
|
|
{ "PRBS_WAIT", 14, 2 },
|
|
{ "PRBS_SYNC_EARLY", 13, 1 },
|
|
{ "RD_DELAY_EARLY", 12, 1 },
|
|
{ "SS_QUAD_CAL", 10, 1 },
|
|
{ "SS_QUAD", 8, 2 },
|
|
{ "SS_RD_DELAY", 7, 1 },
|
|
{ "FORCE_HI_Z", 6, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x44c7c, 0 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x44dd0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x44cc0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x44cc4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44c24, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44d70, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44d74, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x44ce0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x44ce4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x44ce8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x44cec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x44cf0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x44cf4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x44cf8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x44cfc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44d00, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44d04, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44d08, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x44d0c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44d10, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44d14, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44d18, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x44d1c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44d20, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44d24, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44d28, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x44d2c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44d30, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44d34, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44d38, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x44d3c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44d40, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44d44, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44d48, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x44d4c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44d50, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44d54, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44d58, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x44d5c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44d60, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44d64, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44d68, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x44d6c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44c30, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44c34, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x44dc0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x44dc4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x44dc8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44d80, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44d84, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44d88, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x44d8c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44d90, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44d94, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44d98, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x44d9c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x44da0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x44da4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x44da8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x44dac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44c28, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44c38, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x44c3c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44c40, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44c44, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x44c4c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44c50, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44c54, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x44c5c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "WR_LVL_DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44c60, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "WR_CNTR_DONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44c64, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44c68, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x44c6c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44c70, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "DQS_REC_LOW_POWER", 11, 1 },
|
|
{ "DQ_REC_LOW_POWER", 10, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "ADVANCE_PR_VALUE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x44dd8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x44ddc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x44de0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x44de8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x44de4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x44dec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x44dd4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44c74, 0 },
|
|
{ "CHECKER_ENABLE", 15, 1 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "DP18_DFT_ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44c20, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x44cc8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x44ccc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x44cd0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44c78, 0 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x44cd4, 0 },
|
|
{ "DQS_ALIGN_SM", 11, 5 },
|
|
{ "DQS_ALIGN_CNTR", 7, 4 },
|
|
{ "ITERATION_CNTR", 6, 1 },
|
|
{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x44cd8, 0 },
|
|
{ "CALIBRATE_BIT", 13, 3 },
|
|
{ "DQS_ALIGN_QUAD", 11, 2 },
|
|
{ "DQS_QUAD_CONFIG", 8, 3 },
|
|
{ "OPERATE_MODE", 4, 4 },
|
|
{ "EN_DQS_OFFSET", 3, 1 },
|
|
{ "DQS_ALIGN_JITTER", 2, 1 },
|
|
{ "DIS_CLK_GATE", 1, 1 },
|
|
{ "MAX_DQS_ITER", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x44db4, 0 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x44db8, 0 },
|
|
{ "APPROACH_ALIGNMENT", 15, 1 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x44cdc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x44c2c, 0 },
|
|
{ "DP18_HS_PROBE_A_SEL", 11, 5 },
|
|
{ "DP18_HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x44dfc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "VCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44c48, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DQS_ALIGN_BY_QUAD", 4, 1 },
|
|
{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x44dbc, 0 },
|
|
{ "QUAD0_PWR_CTL", 12, 4 },
|
|
{ "QUAD1_PWR_CTL", 8, 4 },
|
|
{ "QUAD2_PWR_CTL", 4, 4 },
|
|
{ "QUAD3_PWR_CTL", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44e00, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44e04, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "DP18_WRAPSEL", 5, 1 },
|
|
{ "HW_VALUE", 4, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x44ff0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x44ff4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44e08, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x44e0c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44e10, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44e14, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x44ff8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44e18, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x44e1c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x44fcc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "BB_LOCK", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x44f7c, 0 },
|
|
{ "FAIL_PASS_VALUE", 8, 7 },
|
|
{ "PASS_FAIL_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44f78, 0 },
|
|
{ "WRCLK_CALIB_DONE", 15, 1 },
|
|
{ "VALUE_UPDATED", 14, 1 },
|
|
{ "FAIL_PASS_V", 13, 1 },
|
|
{ "PASS_FAIL_V", 12, 1 },
|
|
{ "FP_PF_EDGE_NF", 11, 1 },
|
|
{ "NON_SYMETRIC", 10, 1 },
|
|
{ "FULL_RANGE", 8, 1 },
|
|
{ "QUAD3_EDGES", 7, 1 },
|
|
{ "QUAD2_EDGES", 6, 1 },
|
|
{ "QUAD1_EDGES", 5, 1 },
|
|
{ "QUAD0_EDGES", 4, 1 },
|
|
{ "QUAD3_CAVEAT", 3, 1 },
|
|
{ "QUAD2_CAVEAT", 2, 1 },
|
|
{ "QUAD1_CAVEAT", 1, 1 },
|
|
{ "QUAD0_CAVEAT", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44e58, 0 },
|
|
{ "PRBS_WAIT", 14, 2 },
|
|
{ "PRBS_SYNC_EARLY", 13, 1 },
|
|
{ "RD_DELAY_EARLY", 12, 1 },
|
|
{ "SS_QUAD_CAL", 10, 1 },
|
|
{ "SS_QUAD", 8, 2 },
|
|
{ "SS_RD_DELAY", 7, 1 },
|
|
{ "FORCE_HI_Z", 6, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x44e7c, 0 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x44fd0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x44ec0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x44ec4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44e24, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44f70, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44f74, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x44ee0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x44ee4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x44ee8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x44eec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x44ef0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x44ef4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x44ef8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x44efc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44f00, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44f04, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44f08, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x44f0c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44f10, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44f14, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44f18, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x44f1c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44f20, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44f24, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44f28, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x44f2c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44f30, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44f34, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44f38, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x44f3c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44f40, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44f44, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44f48, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x44f4c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44f50, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44f54, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44f58, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x44f5c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44f60, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44f64, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44f68, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x44f6c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44e30, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44e34, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x44fc0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x44fc4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x44fc8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44f80, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44f84, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44f88, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x44f8c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44f90, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44f94, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44f98, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x44f9c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x44fa0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x44fa4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x44fa8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x44fac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44e28, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44e38, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x44e3c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44e40, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44e44, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x44e4c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44e50, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44e54, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x44e5c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "WR_LVL_DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44e60, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "WR_CNTR_DONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44e64, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44e68, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x44e6c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44e70, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "DQS_REC_LOW_POWER", 11, 1 },
|
|
{ "DQ_REC_LOW_POWER", 10, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "ADVANCE_PR_VALUE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x44fd8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x44fdc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x44fe0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x44fe8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x44fe4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x44fec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x44fd4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44e74, 0 },
|
|
{ "CHECKER_ENABLE", 15, 1 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "DP18_DFT_ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44e20, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x44ec8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x44ecc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x44ed0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44e78, 0 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x44ed4, 0 },
|
|
{ "DQS_ALIGN_SM", 11, 5 },
|
|
{ "DQS_ALIGN_CNTR", 7, 4 },
|
|
{ "ITERATION_CNTR", 6, 1 },
|
|
{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x44ed8, 0 },
|
|
{ "CALIBRATE_BIT", 13, 3 },
|
|
{ "DQS_ALIGN_QUAD", 11, 2 },
|
|
{ "DQS_QUAD_CONFIG", 8, 3 },
|
|
{ "OPERATE_MODE", 4, 4 },
|
|
{ "EN_DQS_OFFSET", 3, 1 },
|
|
{ "DQS_ALIGN_JITTER", 2, 1 },
|
|
{ "DIS_CLK_GATE", 1, 1 },
|
|
{ "MAX_DQS_ITER", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x44fb4, 0 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x44fb8, 0 },
|
|
{ "APPROACH_ALIGNMENT", 15, 1 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x44edc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x44e2c, 0 },
|
|
{ "DP18_HS_PROBE_A_SEL", 11, 5 },
|
|
{ "DP18_HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x44ffc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "VCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44e48, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DQS_ALIGN_BY_QUAD", 4, 1 },
|
|
{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x44fbc, 0 },
|
|
{ "QUAD0_PWR_CTL", 12, 4 },
|
|
{ "QUAD1_PWR_CTL", 8, 4 },
|
|
{ "QUAD2_PWR_CTL", 4, 4 },
|
|
{ "QUAD3_PWR_CTL", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x45000, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x45004, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "DP18_WRAPSEL", 5, 1 },
|
|
{ "HW_VALUE", 4, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x451f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x451f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x45008, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4500c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x45010, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x45014, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x451f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x45018, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4501c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x451cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "BB_LOCK", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4517c, 0 },
|
|
{ "FAIL_PASS_VALUE", 8, 7 },
|
|
{ "PASS_FAIL_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_STATUS", 0x45178, 0 },
|
|
{ "WRCLK_CALIB_DONE", 15, 1 },
|
|
{ "VALUE_UPDATED", 14, 1 },
|
|
{ "FAIL_PASS_V", 13, 1 },
|
|
{ "PASS_FAIL_V", 12, 1 },
|
|
{ "FP_PF_EDGE_NF", 11, 1 },
|
|
{ "NON_SYMETRIC", 10, 1 },
|
|
{ "FULL_RANGE", 8, 1 },
|
|
{ "QUAD3_EDGES", 7, 1 },
|
|
{ "QUAD2_EDGES", 6, 1 },
|
|
{ "QUAD1_EDGES", 5, 1 },
|
|
{ "QUAD0_EDGES", 4, 1 },
|
|
{ "QUAD3_CAVEAT", 3, 1 },
|
|
{ "QUAD2_CAVEAT", 2, 1 },
|
|
{ "QUAD1_CAVEAT", 1, 1 },
|
|
{ "QUAD0_CAVEAT", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_CNTL", 0x45058, 0 },
|
|
{ "PRBS_WAIT", 14, 2 },
|
|
{ "PRBS_SYNC_EARLY", 13, 1 },
|
|
{ "RD_DELAY_EARLY", 12, 1 },
|
|
{ "SS_QUAD_CAL", 10, 1 },
|
|
{ "SS_QUAD", 8, 2 },
|
|
{ "SS_RD_DELAY", 7, 1 },
|
|
{ "FORCE_HI_Z", 6, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4507c, 0 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x451d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x450c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x450c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x45024, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x45170, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x45174, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x450e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x450e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x450e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x450ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x450f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x450f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x450f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x450fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x45100, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x45104, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x45108, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4510c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x45110, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x45114, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x45118, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4511c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x45120, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x45124, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x45128, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4512c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x45130, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x45134, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x45138, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4513c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x45140, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x45144, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x45148, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4514c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x45150, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x45154, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x45158, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4515c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x45160, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x45164, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x45168, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4516c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x45030, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x45034, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x451c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x451c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x451c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x45180, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x45184, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x45188, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4518c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x45190, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x45194, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x45198, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4519c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x451a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x451a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x451a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x451ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x45028, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x45038, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4503c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x45040, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x45044, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4504c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x45050, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x45054, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4505c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "WR_LVL_DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x45060, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "WR_CNTR_DONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x45064, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x45068, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4506c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x45070, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "DQS_REC_LOW_POWER", 11, 1 },
|
|
{ "DQ_REC_LOW_POWER", 10, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "ADVANCE_PR_VALUE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x451d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x451dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x451e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x451e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x451e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x451ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x451d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x45074, 0 },
|
|
{ "CHECKER_ENABLE", 15, 1 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "DP18_DFT_ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x45020, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x450c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x450cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x450d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x45078, 0 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x450d4, 0 },
|
|
{ "DQS_ALIGN_SM", 11, 5 },
|
|
{ "DQS_ALIGN_CNTR", 7, 4 },
|
|
{ "ITERATION_CNTR", 6, 1 },
|
|
{ "DQS_ALIGN_ITER_CNTR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x450d8, 0 },
|
|
{ "CALIBRATE_BIT", 13, 3 },
|
|
{ "DQS_ALIGN_QUAD", 11, 2 },
|
|
{ "DQS_QUAD_CONFIG", 8, 3 },
|
|
{ "OPERATE_MODE", 4, 4 },
|
|
{ "EN_DQS_OFFSET", 3, 1 },
|
|
{ "DQS_ALIGN_JITTER", 2, 1 },
|
|
{ "DIS_CLK_GATE", 1, 1 },
|
|
{ "MAX_DQS_ITER", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x451b4, 0 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
|
|
{ "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x451b8, 0 },
|
|
{ "APPROACH_ALIGNMENT", 15, 1 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x450dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4502c, 0 },
|
|
{ "DP18_HS_PROBE_A_SEL", 11, 5 },
|
|
{ "DP18_HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x451fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "VCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x45048, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DQS_ALIGN_BY_QUAD", 4, 1 },
|
|
{ "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x451bc, 0 },
|
|
{ "QUAD0_PWR_CTL", 12, 4 },
|
|
{ "QUAD1_PWR_CTL", 8, 4 },
|
|
{ "QUAD2_PWR_CTL", 4, 4 },
|
|
{ "QUAD3_PWR_CTL", 0, 4 },
|
|
{ "MC_DDRPHY_SEQ_RD_WR_DATA0", 0x47200, 0 },
|
|
{ "MC_DDRPHY_SEQ_RD_WR_DATA1", 0x47204, 0 },
|
|
{ "MC_DDRPHY_SEQ_CONFIG0", 0x47208, 0 },
|
|
{ "MPR_PATTERN_BIT", 15, 1 },
|
|
{ "TWO_CYCLE_ADDR_EN", 14, 1 },
|
|
{ "MR_MASK_EN", 10, 4 },
|
|
{ "PARITY_DLY", 9, 1 },
|
|
{ "FORCE_RESERVED", 7, 1 },
|
|
{ "HALT_ROTATION", 6, 1 },
|
|
{ "FORCE_MPR", 5, 1 },
|
|
{ "IPW_SIDEAB_SEL", 2, 1 },
|
|
{ "PARITY_A17_MASK", 1, 1 },
|
|
{ "X16_DEVICE", 0, 1 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR0", 0x4720c, 0 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR1", 0x47210, 0 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR2", 0x47214, 0 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR3", 0x47218, 0 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR4", 0x4721c, 0 },
|
|
{ "MC_DDRPHY_SEQ_ERROR_STATUS0", 0x47220, 0 },
|
|
{ "MULTIPLE_REQ_ERROR", 15, 1 },
|
|
{ "INVALID_REQTYPE_ERRO", 14, 1 },
|
|
{ "EARLY_REQ_ERROR", 13, 1 },
|
|
{ "MULTIPLE_REQ_SOURCE", 10, 3 },
|
|
{ "INVALID_REQTYPE", 6, 4 },
|
|
{ "INVALID_REQ_SOURCE", 3, 3 },
|
|
{ "EARLY_REQ_SOURCE", 0, 3 },
|
|
{ "MC_DDRPHY_SEQ_ERROR_MASK0", 0x47224, 0 },
|
|
{ "MULT_REQ_ERR_MASK", 15, 1 },
|
|
{ "INVALID_REQTYPE_ERR_MASK", 14, 1 },
|
|
{ "EARLY_REQ_ERR_MASK", 13, 1 },
|
|
{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG0", 0x47228, 0 },
|
|
{ "ODT_WR_VALUES_BITS0_7", 8, 8 },
|
|
{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG1", 0x4722c, 0 },
|
|
{ "ODT_WR_VALUES_BITS0_7", 8, 8 },
|
|
{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG2", 0x47230, 0 },
|
|
{ "ODT_WR_VALUES_BITS0_7", 8, 8 },
|
|
{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG3", 0x47234, 0 },
|
|
{ "ODT_WR_VALUES_BITS0_7", 8, 8 },
|
|
{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG0", 0x47238, 0 },
|
|
{ "ODT_RD_VALUES_x2", 8, 8 },
|
|
{ "ODT_RD_VALUES_x2plus1", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG1", 0x4723c, 0 },
|
|
{ "ODT_RD_VALUES_x2", 8, 8 },
|
|
{ "ODT_RD_VALUES_x2plus1", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG2", 0x47240, 0 },
|
|
{ "ODT_RD_VALUES_x2", 8, 8 },
|
|
{ "ODT_RD_VALUES_x2plus1", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG3", 0x47244, 0 },
|
|
{ "ODT_RD_VALUES_x2", 8, 8 },
|
|
{ "ODT_RD_VALUES_x2plus1", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_MEM_TIMING_PARAM0", 0x47248, 0 },
|
|
{ "TMOD_CYCLES", 12, 4 },
|
|
{ "TRCD_CYCLES", 8, 4 },
|
|
{ "TRP_CYCLES", 4, 4 },
|
|
{ "TRFC_CYCLES", 0, 4 },
|
|
{ "MC_DDRPHY_SEQ_MEM_TIMING_PARAM1", 0x4724c, 0 },
|
|
{ "TZQINIT_CYCLES", 12, 4 },
|
|
{ "TZQCS_CYCLES", 8, 4 },
|
|
{ "TWLDQSEN_CYCLES", 4, 4 },
|
|
{ "TWRMRD_CYCLES", 0, 4 },
|
|
{ "MC_DDRPHY_SEQ_MEM_TIMING_PARAM2", 0x47250, 0 },
|
|
{ "TODTLON_OFF_CYCLES", 12, 4 },
|
|
{ "TRC_CYCLES", 8, 4 },
|
|
{ "TMRSC_CYCLES", 4, 4 },
|
|
{ "MRS_CMD_SPACE", 0, 4 },
|
|
{ "MC_DDRPHY_WC_CONFIG0", 0x47600, 0 },
|
|
{ "TWLO_TWLOE", 8, 8 },
|
|
{ "WL_ONE_DQS_PULSE", 7, 1 },
|
|
{ "FW_WR_RD", 1, 6 },
|
|
{ "CUSTOM_INIT_WRITE", 0, 1 },
|
|
{ "MC_DDRPHY_WC_CONFIG1", 0x47604, 0 },
|
|
{ "BIG_STEP", 12, 4 },
|
|
{ "SMALL_STEP", 9, 3 },
|
|
{ "WR_PRE_DLY", 3, 6 },
|
|
{ "MC_DDRPHY_WC_CONFIG2", 0x47608, 0 },
|
|
{ "NUM_VALID_SAMPLES", 12, 4 },
|
|
{ "FW_RD_WR", 6, 6 },
|
|
{ "TWR_MPR", 2, 4 },
|
|
{ "EN_RESET_WR_DELAY_WL", 0, 1 },
|
|
{ "MC_DDRPHY_WC_CONFIG3", 0x47614, 0 },
|
|
{ "DDR4_MRS_CMD_DQ_EN", 15, 1 },
|
|
{ "MRS_CMD_DQ_ON", 9, 6 },
|
|
{ "MRS_CMD_DQ_OFF", 3, 6 },
|
|
{ "MC_DDRPHY_WC_WRCLK_CNTL", 0x47618, 0 },
|
|
{ "WRCLK_CAL_START", 15, 1 },
|
|
{ "WRCLK_CAL_DONE", 14, 1 },
|
|
{ "MC_DDRPHY_WC_ERROR_STATUS0", 0x4760c, 0 },
|
|
{ "WR_CNTL_ERROR", 15, 1 },
|
|
{ "MC_DDRPHY_WC_ERROR_MASK0", 0x47610, 0 },
|
|
{ "WR_CNTL_ERROR_MASK", 15, 1 },
|
|
{ "MC_DDRPHY_RC_CONFIG0", 0x47400, 0 },
|
|
{ "GLOBAL_PHY_OFFSET", 12, 4 },
|
|
{ "ADVANCE_RD_VALID", 11, 1 },
|
|
{ "ERS_MODE", 10, 1 },
|
|
{ "SINGLE_BIT_MPR_RP0", 6, 1 },
|
|
{ "SINGLE_BIT_MPR_RP1", 5, 1 },
|
|
{ "SINGLE_BIT_MPR_RP2", 4, 1 },
|
|
{ "SINGLE_BIT_MPR_RP3", 3, 1 },
|
|
{ "ALIGN_ON_EVEN_CYCLES", 2, 1 },
|
|
{ "PERFORM_RDCLK_ALIGN", 1, 1 },
|
|
{ "STAGGERED_PATTERN", 0, 1 },
|
|
{ "MC_DDRPHY_RC_CONFIG1", 0x47404, 0 },
|
|
{ "OUTER_LOOP_CNT", 2, 14 },
|
|
{ "MC_DDRPHY_RC_CONFIG2", 0x47408, 0 },
|
|
{ "CONSEQ_PASS", 11, 5 },
|
|
{ "BURST_WINDOW", 5, 2 },
|
|
{ "ALLOW_RD_FIFO_AUTO_R_ESET", 4, 1 },
|
|
{ "DIS_LOW_PWR_PER_CAL", 3, 1 },
|
|
{ "MC_DDRPHY_RC_CONFIG3", 0x4741c, 0 },
|
|
{ "FINE_CAL_STEP_SIZE", 13, 3 },
|
|
{ "COARSE_CAL_STEP_SIZE", 9, 4 },
|
|
{ "DQ_SEL_QUAD", 7, 2 },
|
|
{ "DQ_SEL_LANE", 4, 3 },
|
|
{ "MC_DDRPHY_RC_PERIODIC", 0x47420, 0 },
|
|
{ "MC_DDRPHY_RC_ERROR_STATUS0", 0x47414, 0 },
|
|
{ "RD_CNTL_ERROR", 15, 1 },
|
|
{ "MC_DDRPHY_RC_ERROR_MASK0", 0x47418, 0 },
|
|
{ "RD_CNTL_ERROR_MASK", 15, 1 },
|
|
{ "MC_DDRPHY_APB_CONFIG0", 0x47800, 0 },
|
|
{ "DISABLE_PARITY_CHECKER", 15, 1 },
|
|
{ "GENERATE_EVEN_PARITY", 14, 1 },
|
|
{ "FORCE_ON_CLK_GATE", 13, 1 },
|
|
{ "DEBUG_BUS_SEL_LO", 12, 1 },
|
|
{ "DEBUG_BUS_SEL_HI", 8, 4 },
|
|
{ "MC_DDRPHY_APB_ERROR_STATUS0", 0x47804, 0 },
|
|
{ "INVALID_ADDRESS", 15, 1 },
|
|
{ "WR_PAR_ERR", 14, 1 },
|
|
{ "MC_DDRPHY_APB_ERROR_MASK0", 0x47808, 0 },
|
|
{ "INVALID_ADDRESS_MASK", 15, 1 },
|
|
{ "WR_PAR_ERR_MASK", 14, 1 },
|
|
{ "MC_DDRPHY_APB_DP18_POPULATION", 0x4780c, 0 },
|
|
{ "DP18_0_Populated", 15, 1 },
|
|
{ "DP18_1_Populated", 14, 1 },
|
|
{ "DP18_2_Populated", 13, 1 },
|
|
{ "DP18_3_Populated", 12, 1 },
|
|
{ "DP18_4_Populated", 11, 1 },
|
|
{ "DP18_5_Populated", 10, 1 },
|
|
{ "DP18_6_Populated", 9, 1 },
|
|
{ "DP18_7_Populated", 8, 1 },
|
|
{ "DP18_8_Populated", 7, 1 },
|
|
{ "DP18_9_Populated", 6, 1 },
|
|
{ "DP18_10_Populated", 5, 1 },
|
|
{ "DP18_11_Populated", 4, 1 },
|
|
{ "DP18_12_Populated", 3, 1 },
|
|
{ "DP18_13_Populated", 2, 1 },
|
|
{ "DP18_14_Populated", 1, 1 },
|
|
{ "MC_DDRPHY_APB_ADR_POPULATION", 0x47810, 0 },
|
|
{ "ADR16_0_Populated", 15, 1 },
|
|
{ "ADR16_1_Populated", 14, 1 },
|
|
{ "ADR16_2_Populated", 13, 1 },
|
|
{ "ADR16_3_Populated", 12, 1 },
|
|
{ "ADR12_0_Populated", 7, 1 },
|
|
{ "ADR12_1_Populated", 6, 1 },
|
|
{ "ADR12_2_Populated", 5, 1 },
|
|
{ "ADR12_3_Populated", 4, 1 },
|
|
{ "MC_DDRPHY_APB_ATEST_MUX_SEL", 0x47814, 0 },
|
|
{ "ATEST_CNTL", 10, 6 },
|
|
{ "MC_DDRPHY_APB_MTCTL_REG0", 0x47820, 0 },
|
|
{ "MT_DATA_MUX4_1MODE", 15, 1 },
|
|
{ "MT_PLL_RESET", 14, 1 },
|
|
{ "MT_SYSCLK_RESET", 13, 1 },
|
|
{ "MT_GLOBAL_PHY_OFFSET", 9, 4 },
|
|
{ "MT_DQ_SEL_QUAD", 7, 2 },
|
|
{ "MT_PERFORM_RDCLK_ALIGN", 6, 1 },
|
|
{ "MT_ALIGN_ON_EVEN_CYCLES", 5, 1 },
|
|
{ "MT_WRCLK_CAL_START", 4, 1 },
|
|
{ "MC_DDRPHY_APB_MTCTL_REG1", 0x47824, 0 },
|
|
{ "MT_WPRD_ENABLE", 15, 1 },
|
|
{ "MT_PVTP", 10, 5 },
|
|
{ "MT_PVTN", 5, 5 },
|
|
{ "MC_DDRPHY_APB_MTSTAT_REG0", 0x47828, 0 },
|
|
{ "MC_DDRPHY_APB_MTSTAT_REG1", 0x4782c, 0 },
|
|
{ "MT_ADR32_PLL_LOCK_SUM", 1, 1 },
|
|
{ "MT_DP18_PLL_LOCK_SUM", 0, 1 },
|
|
{ "MC_LMC_MCSTAT", 0x40040, 0 },
|
|
{ "INIT_COMPLETE", 31, 1 },
|
|
{ "SELF_REF_MODE", 30, 1 },
|
|
{ "IDLE", 29, 1 },
|
|
{ "DFI_INIT_COMPLETE", 28, 1 },
|
|
{ "PREFILL_COMPLETE", 27, 1 },
|
|
{ "MC_LMC_MCOPT1", 0x40080, 0 },
|
|
{ "MC_PROTOCOL", 31, 1 },
|
|
{ "DM_ENABLE", 30, 1 },
|
|
{ "ECC_EN", 29, 1 },
|
|
{ "ECC_COR", 28, 1 },
|
|
{ "RDIMM", 27, 1 },
|
|
{ "PMUM", 25, 2 },
|
|
{ "WIDTH0", 24, 1 },
|
|
{ "PORT_ID_CHK_EN", 23, 1 },
|
|
{ "UIOS", 22, 1 },
|
|
{ "QUADCS_RDIMM", 21, 1 },
|
|
{ "ZQCL_EN", 20, 1 },
|
|
{ "WIDTH1", 19, 1 },
|
|
{ "WD_DLY", 18, 1 },
|
|
{ "QDEPTH", 16, 2 },
|
|
{ "RWOO", 15, 1 },
|
|
{ "WOOO", 14, 1 },
|
|
{ "DCOO", 13, 1 },
|
|
{ "DEF_REF", 12, 1 },
|
|
{ "DEV_TYPE", 11, 1 },
|
|
{ "CA_PTY_DLY", 10, 1 },
|
|
{ "ECC_MUX", 8, 2 },
|
|
{ "CE_THRESHOLD", 0, 8 },
|
|
{ "MC_LMC_MCOPT2", 0x40084, 0 },
|
|
{ "SELF_REF_EN", 31, 1 },
|
|
{ "XSR_PREVENT", 30, 1 },
|
|
{ "INIT_START", 29, 1 },
|
|
{ "MC_ENABLE", 28, 1 },
|
|
{ "CLK_DISABLE", 24, 4 },
|
|
{ "RESET_RANK", 20, 4 },
|
|
{ "MCIF_COMP_PTY_EN", 19, 1 },
|
|
{ "CKE_OE", 17, 1 },
|
|
{ "RESET_OE", 16, 1 },
|
|
{ "DFI_PHYUD_CNTL", 14, 1 },
|
|
{ "DFI_PHYUD_ACK", 13, 1 },
|
|
{ "DFI_INIT_START", 12, 1 },
|
|
{ "PM_ENABLE", 8, 4 },
|
|
{ "RD_DEFREF_CNT", 4, 4 },
|
|
{ "MC_LMC_CFGR0", 0x40100, 0 },
|
|
{ "ROW_WIDTH", 12, 3 },
|
|
{ "ADDR_MODE", 8, 4 },
|
|
{ "MIRROR", 4, 1 },
|
|
{ "RANK_ENABLE", 0, 1 },
|
|
{ "MC_LMC_INITSEQ0", 0x40140, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD0", 0x40144, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ1", 0x40148, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD1", 0x4014c, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ2", 0x40150, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD2", 0x40154, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ3", 0x40158, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD3", 0x4015c, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ4", 0x40160, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD4", 0x40164, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ5", 0x40168, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD5", 0x4016c, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ6", 0x40170, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD6", 0x40174, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ7", 0x40178, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD7", 0x4017c, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ8", 0x40180, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD8", 0x40184, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ9", 0x40188, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD9", 0x4018c, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ10", 0x40190, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD10", 0x40194, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ11", 0x40198, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD11", 0x4019c, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ12", 0x401a0, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD12", 0x401a4, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ13", 0x401a8, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD13", 0x401ac, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ14", 0x401b0, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD14", 0x401b4, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_INITSEQ15", 0x401b8, 0 },
|
|
{ "INIT_ENABLE", 31, 1 },
|
|
{ "WAIT", 16, 12 },
|
|
{ "EN_MULTI_RANK_SEL", 4, 1 },
|
|
{ "RANK", 0, 4 },
|
|
{ "MC_LMC_CMD15", 0x401bc, 0 },
|
|
{ "CMD", 29, 3 },
|
|
{ "CMD_ACTN", 28, 1 },
|
|
{ "BG1", 23, 1 },
|
|
{ "BANK", 20, 3 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MC_LMC_SDTR0", 0x40200, 0 },
|
|
{ "REFI", 16, 16 },
|
|
{ "T_RFC_XPR", 0, 12 },
|
|
{ "MC_LMC_SDTR1", 0x40204, 0 },
|
|
{ "T_LEADOFF", 31, 1 },
|
|
{ "ODT_DELAY", 30, 1 },
|
|
{ "ODT_WIDTH", 29, 1 },
|
|
{ "T_WTRO", 24, 4 },
|
|
{ "T_RTWO", 16, 4 },
|
|
{ "T_RTW_ADJ", 12, 4 },
|
|
{ "T_WTWO", 8, 4 },
|
|
{ "T_RTRO", 0, 4 },
|
|
{ "MC_LMC_SDTR2", 0x40208, 0 },
|
|
{ "T_CWL", 28, 4 },
|
|
{ "T_RCD0", 24, 4 },
|
|
{ "T_PL", 20, 4 },
|
|
{ "T_RP0", 16, 4 },
|
|
{ "T_RP1", 15, 1 },
|
|
{ "T_RCD1", 14, 1 },
|
|
{ "T_RC", 8, 6 },
|
|
{ "T_RAS", 0, 6 },
|
|
{ "MC_LMC_SDTR3", 0x4020c, 0 },
|
|
{ "T_WTR_S", 28, 4 },
|
|
{ "T_WTR", 24, 4 },
|
|
{ "FAW_ADJ", 20, 2 },
|
|
{ "T_RTP", 16, 4 },
|
|
{ "T_RRD_L", 12, 4 },
|
|
{ "T_RRD", 8, 4 },
|
|
{ "T_XSDLL", 0, 8 },
|
|
{ "MC_LMC_SDTR4", 0x40210, 0 },
|
|
{ "T_RDDATA_EN", 24, 7 },
|
|
{ "T_SYS_RDLAT", 16, 6 },
|
|
{ "T_CCD_L", 12, 4 },
|
|
{ "T_CCD", 8, 3 },
|
|
{ "T_CPDED", 5, 3 },
|
|
{ "T_MOD", 0, 5 },
|
|
{ "MC_LMC_SDTR5", 0x40214, 0 },
|
|
{ "T_PHY_WRDATA", 24, 3 },
|
|
{ "T_PHY_WRLAT", 16, 5 },
|
|
{ "MC_LMC_DBG0", 0x40228, 0 },
|
|
{ "T_SYS_RDLAT_DBG", 16, 5 },
|
|
{ "MC_LMC_SMR0", 0x40240, 0 },
|
|
{ "SMR0_RFU0", 13, 3 },
|
|
{ "PPD", 12, 1 },
|
|
{ "WR_RTP", 9, 3 },
|
|
{ "SMR0_DLL", 8, 1 },
|
|
{ "TM", 7, 1 },
|
|
{ "CL31", 4, 3 },
|
|
{ "RBT", 3, 1 },
|
|
{ "CL0", 2, 1 },
|
|
{ "BL", 0, 2 },
|
|
{ "MC_LMC_SMR1", 0x40244, 0 },
|
|
{ "QOFF", 12, 1 },
|
|
{ "TDQS", 11, 1 },
|
|
{ "SMR1_RFU0", 10, 1 },
|
|
{ "RTT_NOM0", 9, 1 },
|
|
{ "SMR1_RFU1", 8, 1 },
|
|
{ "WR_LEVEL", 7, 1 },
|
|
{ "RTT_NOM1", 6, 1 },
|
|
{ "DIC0", 5, 1 },
|
|
{ "AL", 3, 2 },
|
|
{ "RTT_NOM2", 2, 1 },
|
|
{ "DIC1", 1, 1 },
|
|
{ "SMR1_DLL", 0, 1 },
|
|
{ "MC_LMC_SMR2", 0x40248, 0 },
|
|
{ "WR_CRC", 12, 1 },
|
|
{ "RD_CRC", 11, 1 },
|
|
{ "RTT_WR", 9, 2 },
|
|
{ "SMR2_RFU0", 8, 1 },
|
|
{ "SRT_ASR1", 7, 1 },
|
|
{ "ASR0", 6, 1 },
|
|
{ "CWL", 3, 3 },
|
|
{ "PASR", 0, 3 },
|
|
{ "MC_LMC_SMR3", 0x4024c, 0 },
|
|
{ "MPR_RD_FMT", 11, 2 },
|
|
{ "SMR3_RFU0", 9, 2 },
|
|
{ "FGR_MODE", 6, 3 },
|
|
{ "MRS_RDO", 5, 1 },
|
|
{ "DRAM_ADR", 4, 1 },
|
|
{ "GD_MODE", 3, 1 },
|
|
{ "MPR", 2, 1 },
|
|
{ "MPR_SEL", 0, 2 },
|
|
{ "MC_LMC_SMR4", 0x40250, 0 },
|
|
{ "WR_PRE", 12, 1 },
|
|
{ "RD_PRE", 11, 1 },
|
|
{ "RPT_MODE", 10, 1 },
|
|
{ "FESR_MODE", 9, 1 },
|
|
{ "CS_LAT_MODE", 6, 3 },
|
|
{ "ALERT_STAT", 5, 1 },
|
|
{ "IVM_MODE", 4, 1 },
|
|
{ "TCR_MODE", 3, 1 },
|
|
{ "TCR_RANGE", 2, 1 },
|
|
{ "MPD_MODE", 1, 1 },
|
|
{ "SMR4_RFU", 0, 1 },
|
|
{ "MC_LMC_SMR5", 0x40254, 0 },
|
|
{ "RD_DBI", 11, 1 },
|
|
{ "WR_DBI", 10, 1 },
|
|
{ "DM_MODE", 9, 1 },
|
|
{ "RTT_PARK", 6, 3 },
|
|
{ "SMR5_RFU", 5, 1 },
|
|
{ "PAR_ERR_STAT", 4, 1 },
|
|
{ "CRC_CLEAR", 3, 1 },
|
|
{ "PAR_LAT_MODE", 0, 3 },
|
|
{ "MC_LMC_SMR6", 0x40258, 0 },
|
|
{ "TCCD_L", 10, 3 },
|
|
{ "SRM6_RFU", 7, 3 },
|
|
{ "VREF_DQ_RANGE", 6, 1 },
|
|
{ "VREF_DQ_VALUE", 0, 6 },
|
|
{ "MC_LMC_ODTR0", 0x40280, 0 },
|
|
{ "RK0W", 25, 1 },
|
|
{ "RK0R", 24, 1 },
|
|
{ "MC_LMC_CALSTAT", 0x40304, 0 },
|
|
{ "PHYUPD_ERR", 28, 4 },
|
|
{ "PHYUPD_BUSY", 27, 1 },
|
|
{ "MC_LMC_T_PHYUPD0", 0x40330, 0 },
|
|
{ "MC_LMC_T_PHYUPD1", 0x40334, 0 },
|
|
{ "MC_LMC_T_PHYUPD2", 0x40338, 0 },
|
|
{ "MC_LMC_T_PHYUPD3", 0x4033c, 0 },
|
|
{ "MC_P_DDRPHY_RST_CTRL", 0x41300, 0 },
|
|
{ "PHY_CAL_REQ", 21, 1 },
|
|
{ "PHY_DRAM_WL", 17, 4 },
|
|
{ "PHY_CALIB_DONE", 5, 1 },
|
|
{ "CTL_CAL_REQ", 4, 1 },
|
|
{ "CTL_CKE", 3, 1 },
|
|
{ "CTL_RST_N", 2, 1 },
|
|
{ "DDRIO_ENABLE", 1, 1 },
|
|
{ "PHY_RST_N", 0, 1 },
|
|
{ "MC_P_PERFORMANCE_CTRL", 0x41304, 0 },
|
|
{ "BUF_USE_TH", 12, 3 },
|
|
{ "MC_IDLE_TH", 8, 4 },
|
|
{ "RMW_DEFER_EN", 7, 1 },
|
|
{ "DDR3_BRBC_MODE", 6, 1 },
|
|
{ "RMW_DWRITE_EN", 5, 1 },
|
|
{ "RMW_MERGE_EN", 4, 1 },
|
|
{ "SYNC_PAB_EN", 3, 1 },
|
|
{ "STALL_CHK_BIT", 2, 1 },
|
|
{ "DDR3_BRC_MODE", 1, 1 },
|
|
{ "RMW_PERF_CTRL", 0, 1 },
|
|
{ "MC_P_ECC_CTRL", 0x41308, 0 },
|
|
{ "ECC_BYPASS_BIST", 1, 1 },
|
|
{ "ECC_DISABLE", 0, 1 },
|
|
{ "MC_P_PAR_ENABLE", 0x4130c, 0 },
|
|
{ "ECC_UE_PAR_ENABLE", 3, 1 },
|
|
{ "ECC_CE_PAR_ENABLE", 2, 1 },
|
|
{ "PERR_REG_INT_ENABLE", 1, 1 },
|
|
{ "PERR_BLK_INT_ENABLE", 0, 1 },
|
|
{ "MC_P_PAR_CAUSE", 0x41310, 0 },
|
|
{ "ECC_UE_PAR_CAUSE", 3, 1 },
|
|
{ "ECC_CE_PAR_CAUSE", 2, 1 },
|
|
{ "FIFOR_PAR_CAUSE", 1, 1 },
|
|
{ "RDATA_FIFOR_PAR_CAUSE", 0, 1 },
|
|
{ "MC_P_INT_ENABLE", 0x41314, 0 },
|
|
{ "ECC_UE_INT_ENABLE", 2, 1 },
|
|
{ "ECC_CE_INT_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "MC_P_INT_CAUSE", 0x41318, 0 },
|
|
{ "ECC_UE_INT_CAUSE", 2, 1 },
|
|
{ "ECC_CE_INT_CAUSE", 1, 1 },
|
|
{ "PERR_INT_CAUSE", 0, 1 },
|
|
{ "MC_P_ECC_STATUS", 0x4131c, 0 },
|
|
{ "ECC_CECNT", 16, 16 },
|
|
{ "ECC_UECNT", 0, 16 },
|
|
{ "MC_P_PHY_CTRL", 0x41320, 0 },
|
|
{ "MC_P_STATIC_CFG_STATUS", 0x41324, 0 },
|
|
{ "STATIC_PP64", 26, 1 },
|
|
{ "STATIC_PPEN", 25, 1 },
|
|
{ "STATIC_OOOEN", 24, 1 },
|
|
{ "STATIC_AWEN", 23, 1 },
|
|
{ "STATIC_SWLAT", 18, 5 },
|
|
{ "STATIC_WLAT", 17, 1 },
|
|
{ "STATIC_ALIGN", 16, 1 },
|
|
{ "STATIC_SLAT", 11, 5 },
|
|
{ "STATIC_LAT", 10, 1 },
|
|
{ "STATIC_MODE", 9, 1 },
|
|
{ "STATIC_DEN", 6, 3 },
|
|
{ "STATIC_ORG", 5, 1 },
|
|
{ "STATIC_RKS", 4, 1 },
|
|
{ "STATIC_WIDTH", 1, 3 },
|
|
{ "STATIC_SLOW", 0, 1 },
|
|
{ "MC_P_CORE_PCTL_STAT", 0x41328, 0 },
|
|
{ "MC_P_DEBUG_CNT", 0x4132c, 0 },
|
|
{ "WDATA_OCNT", 8, 5 },
|
|
{ "RDATA_OCNT", 0, 5 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41330, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41334, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41338, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x4133c, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41340, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41344, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41348, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x4134c, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41350, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41354, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41358, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x4135c, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41360, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41364, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41368, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x4136c, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41370, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41374, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41378, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x4137c, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41380, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41384, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41388, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x4138c, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41390, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41394, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41398, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x4139c, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x413a0, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x413a4, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x413a8, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x413ac, 0 },
|
|
{ "MC_CE_ADDR", 0x413b0, 0 },
|
|
{ "MC_UE_ADDR", 0x413b4, 0 },
|
|
{ "MC_P_DEEP_SLEEP", 0x413b8, 0 },
|
|
{ "SleepStatus", 1, 1 },
|
|
{ "SleepReq", 0, 1 },
|
|
{ "MC_P_FPGA_BONUS", 0x413bc, 0 },
|
|
{ "MC_P_DEBUG_CFG", 0x413c0, 0 },
|
|
{ "DEBUG_OR", 15, 1 },
|
|
{ "DEBUG_HI", 14, 1 },
|
|
{ "DEBUG_RPT", 13, 1 },
|
|
{ "DEBUGPAGE", 10, 3 },
|
|
{ "DEBUGSELH", 5, 5 },
|
|
{ "DEBUGSELL", 0, 5 },
|
|
{ "MC_P_DEBUG_RPT", 0x413c4, 0 },
|
|
{ "MC_P_PHY_ADR_CK_EN", 0x413c8, 0 },
|
|
{ "MC_CE_ERR_ECC_DATA0", 0x413d0, 0 },
|
|
{ "MC_CE_ERR_ECC_DATA1", 0x413d4, 0 },
|
|
{ "MC_UE_ERR_ECC_DATA0", 0x413d8, 0 },
|
|
{ "MC_UE_ERR_ECC_DATA1", 0x413dc, 0 },
|
|
{ "MC_P_RMW_PRIO", 0x413f0, 0 },
|
|
{ "WR_HI_TH", 24, 8 },
|
|
{ "WR_MID_TH", 16, 8 },
|
|
{ "RD_HI_TH", 8, 8 },
|
|
{ "RD_MID_TH", 0, 8 },
|
|
{ "MC_P_BIST_CMD", 0x41400, 0 },
|
|
{ "START_BIST", 31, 1 },
|
|
{ "BURST_LEN", 16, 2 },
|
|
{ "BIST_CMD_GAP", 8, 8 },
|
|
{ "BIST_OPCODE", 0, 2 },
|
|
{ "MC_P_BIST_CMD_ADDR", 0x41404, 0 },
|
|
{ "MC_P_BIST_CMD_LEN", 0x41408, 0 },
|
|
{ "MC_P_BIST_DATA_PATTERN", 0x4140c, 0 },
|
|
{ "MC_P_BIST_USER_WMASK0", 0x41414, 0 },
|
|
{ "MC_P_BIST_USER_WMASK1", 0x41418, 0 },
|
|
{ "MC_P_BIST_USER_WMASK2", 0x4141c, 0 },
|
|
{ "MASK_128_1", 9, 1 },
|
|
{ "MASK_128_0", 8, 1 },
|
|
{ "USER_MASK_ECC", 0, 8 },
|
|
{ "MC_P_BIST_NUM_ERR", 0x41480, 0 },
|
|
{ "MC_P_BIST_ERR_FIRST_ADDR", 0x41484, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x41488, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x4148c, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x41490, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x41494, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x41498, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x4149c, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414a0, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414a4, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414a8, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414ac, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414b0, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414b4, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414b8, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414bc, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414c0, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414c4, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414c8, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414cc, 0 },
|
|
{ "MC_P_BIST_CRC_SEED", 0x414d0, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_edc_t60_regs[] = {
|
|
{ "EDC_H_REF", 0x50000, 0 },
|
|
{ "SleepStatus", 31, 1 },
|
|
{ "SleepReq", 30, 1 },
|
|
{ "PING_PONG", 29, 1 },
|
|
{ "QDR_ClkPhase", 24, 3 },
|
|
{ "MaxOpsPerTRC", 21, 3 },
|
|
{ "NumPipeStages", 19, 2 },
|
|
{ "EDC_INST_NUM", 18, 1 },
|
|
{ "ENABLE_PERF", 17, 1 },
|
|
{ "ECC_BYPASS", 16, 1 },
|
|
{ "RefFreq", 0, 16 },
|
|
{ "EDC_H_BIST_CMD", 0x50004, 0 },
|
|
{ "START_BIST", 31, 1 },
|
|
{ "BURST_LEN", 16, 2 },
|
|
{ "BIST_CMD_GAP", 8, 8 },
|
|
{ "BIST_OPCODE", 0, 2 },
|
|
{ "EDC_H_BIST_CMD_ADDR", 0x50008, 0 },
|
|
{ "EDC_H_BIST_CMD_LEN", 0x5000c, 0 },
|
|
{ "EDC_H_BIST_DATA_PATTERN", 0x50010, 0 },
|
|
{ "EDC_H_BIST_USER_WDATA0", 0x50014, 0 },
|
|
{ "EDC_H_BIST_USER_WDATA1", 0x50018, 0 },
|
|
{ "EDC_H_BIST_USER_WDATA2", 0x5001c, 0 },
|
|
{ "USER_DATA_MASK", 8, 9 },
|
|
{ "USER_DATA2", 0, 8 },
|
|
{ "EDC_H_BIST_NUM_ERR", 0x50020, 0 },
|
|
{ "EDC_H_BIST_ERR_FIRST_ADDR", 0x50024, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50028, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5002c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50030, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50034, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50038, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5003c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50040, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50044, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50048, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5004c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50050, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50054, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50058, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5005c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50060, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50064, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50068, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5006c, 0 },
|
|
{ "EDC_H_PAR_ENABLE", 0x50070, 0 },
|
|
{ "ECC_UE_PAR_ENABLE", 2, 1 },
|
|
{ "ECC_CE_PAR_ENABLE", 1, 1 },
|
|
{ "PERR_PAR_ENABLE", 0, 1 },
|
|
{ "EDC_H_INT_ENABLE", 0x50074, 0 },
|
|
{ "ECC_UE_INT_ENABLE", 2, 1 },
|
|
{ "ECC_CE_INT_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "EDC_H_INT_CAUSE", 0x50078, 0 },
|
|
{ "ECC_UE_INT0_CAUSE", 5, 1 },
|
|
{ "ECC_CE_INT0_CAUSE", 4, 1 },
|
|
{ "PERR_INT0_CAUSE", 3, 1 },
|
|
{ "ECC_UE_INT_CAUSE", 2, 1 },
|
|
{ "ECC_CE_INT_CAUSE", 1, 1 },
|
|
{ "PERR_INT_CAUSE", 0, 1 },
|
|
{ "EDC_H_ECC_STATUS", 0x5007c, 0 },
|
|
{ "ECC_CECNT", 16, 16 },
|
|
{ "ECC_UECNT", 0, 16 },
|
|
{ "EDC_H_ECC_ERR_SEL", 0x50080, 0 },
|
|
{ "EDC_H_ECC_ERR_ADDR", 0x50084, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50090, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50094, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50098, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x5009c, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500a0, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500a4, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500a8, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500ac, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500b0, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500b4, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500b8, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500bc, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500c0, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500c4, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500c8, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500cc, 0 },
|
|
{ "EDC_H_DBG_MA_CMD_INTF", 0x50300, 0 },
|
|
{ "MCmdAddr", 12, 20 },
|
|
{ "MCmdLen", 5, 7 },
|
|
{ "MCmdNRE", 4, 1 },
|
|
{ "MCmdNRB", 3, 1 },
|
|
{ "MCmdWr", 2, 1 },
|
|
{ "MCmdRdy", 1, 1 },
|
|
{ "MCmdVld", 0, 1 },
|
|
{ "EDC_H_DBG_MA_WDATA_INTF", 0x50304, 0 },
|
|
{ "MWDataVld", 31, 1 },
|
|
{ "MWDataRdy", 30, 1 },
|
|
{ "MWData", 0, 30 },
|
|
{ "EDC_H_DBG_MA_RDATA_INTF", 0x50308, 0 },
|
|
{ "MRspVld", 31, 1 },
|
|
{ "MRspRdy", 30, 1 },
|
|
{ "MRspData", 0, 30 },
|
|
{ "EDC_H_DBG_BIST_CMD_INTF", 0x5030c, 0 },
|
|
{ "BCmdAddr", 9, 23 },
|
|
{ "BCmdLen", 3, 6 },
|
|
{ "BCmdWr", 2, 1 },
|
|
{ "BCmdRdy", 1, 1 },
|
|
{ "BCmdVld", 0, 1 },
|
|
{ "EDC_H_DBG_BIST_WDATA_INTF", 0x50310, 0 },
|
|
{ "BWDataVld", 31, 1 },
|
|
{ "BWDataRdy", 30, 1 },
|
|
{ "BWData", 0, 30 },
|
|
{ "EDC_H_DBG_BIST_RDATA_INTF", 0x50314, 0 },
|
|
{ "BRspVld", 31, 1 },
|
|
{ "BRspRdy", 30, 1 },
|
|
{ "BRspData", 0, 30 },
|
|
{ "EDC_H_DBG_EDRAM_CMD_INTF", 0x50318, 0 },
|
|
{ "EdramAddr", 16, 16 },
|
|
{ "EdramDwsn", 8, 8 },
|
|
{ "EdramCra", 5, 3 },
|
|
{ "EdramRefEnLo", 4, 1 },
|
|
{ "Edram1WrEnLo", 3, 1 },
|
|
{ "Edram1RdEnLo", 2, 1 },
|
|
{ "Edram0WrEnLo", 1, 1 },
|
|
{ "Edram0RdEnLo", 0, 1 },
|
|
{ "EDC_H_DBG_EDRAM_WDATA_INTF", 0x5031c, 0 },
|
|
{ "EdramWData", 9, 23 },
|
|
{ "EdramWByteEn", 0, 9 },
|
|
{ "EDC_H_DBG_EDRAM0_RDATA_INTF", 0x50320, 0 },
|
|
{ "EDC_H_DBG_EDRAM1_RDATA_INTF", 0x50324, 0 },
|
|
{ "EDC_H_DBG_MA_WR_REQ_CNT", 0x50328, 0 },
|
|
{ "EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT", 0x5032c, 0 },
|
|
{ "EDC_H_DBG_MA_WR_DAT_CYC_CNT", 0x50330, 0 },
|
|
{ "EDC_H_DBG_MA_RD_REQ_CNT", 0x50334, 0 },
|
|
{ "EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT", 0x50338, 0 },
|
|
{ "EDC_H_DBG_MA_RD_DAT_CYC_CNT", 0x5033c, 0 },
|
|
{ "EDC_H_DBG_BIST_WR_REQ_CNT", 0x50340, 0 },
|
|
{ "EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT", 0x50344, 0 },
|
|
{ "EDC_H_DBG_BIST_WR_DAT_CYC_CNT", 0x50348, 0 },
|
|
{ "EDC_H_DBG_BIST_RD_REQ_CNT", 0x5034c, 0 },
|
|
{ "EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT", 0x50350, 0 },
|
|
{ "EDC_H_DBG_BIST_RD_DAT_CYC_CNT", 0x50354, 0 },
|
|
{ "EDC_H_DBG_EDRAM0_WR_REQ_CNT", 0x50358, 0 },
|
|
{ "EDC_H_DBG_EDRAM0_RD_REQ_CNT", 0x5035c, 0 },
|
|
{ "EDC_H_DBG_EDRAM0_RMW_CNT", 0x50360, 0 },
|
|
{ "EDC_H_DBG_EDRAM1_WR_REQ_CNT", 0x50364, 0 },
|
|
{ "EDC_H_DBG_EDRAM1_RD_REQ_CNT", 0x50368, 0 },
|
|
{ "EDC_H_DBG_EDRAM1_RMW_CNT", 0x5036c, 0 },
|
|
{ "EDC_H_DBG_EDRAM_REF_BURST_CNT", 0x50370, 0 },
|
|
{ "EDC_H_DBG_FIFO_STATUS", 0x50374, 0 },
|
|
{ "rdtag_notfull", 17, 1 },
|
|
{ "rdtag_notempty", 16, 1 },
|
|
{ "inp_cmdq_notfull_arb", 15, 1 },
|
|
{ "inp_cmdq_notempty", 14, 1 },
|
|
{ "inp_wrdq_wrrdy", 13, 1 },
|
|
{ "inp_wrdq_notempty", 12, 1 },
|
|
{ "inp_beq_wrrdy_open", 11, 1 },
|
|
{ "inp_beq_notempty", 10, 1 },
|
|
{ "rddq_notfull_open", 9, 1 },
|
|
{ "rddq_rdcnt", 4, 5 },
|
|
{ "rdsideq_notfull", 3, 1 },
|
|
{ "rdsideq_notempty", 2, 1 },
|
|
{ "stg_cmdq_notempty", 1, 1 },
|
|
{ "stg_wrdq_notempty", 0, 1 },
|
|
{ "EDC_H_DBG_FSM_STATE", 0x50378, 0 },
|
|
{ "CmdSplitFsm", 3, 1 },
|
|
{ "CmdFsm", 0, 3 },
|
|
{ "EDC_H_DBG_STALL_CYCLES", 0x5037c, 0 },
|
|
{ "stall_rmw", 19, 1 },
|
|
{ "stall_edc_cmd", 18, 1 },
|
|
{ "dead_cycle0", 17, 1 },
|
|
{ "dead_cycle1", 16, 1 },
|
|
{ "dead_cycle0_bbi", 15, 1 },
|
|
{ "dead_cycle1_bbi", 14, 1 },
|
|
{ "dead_cycle0_max_op", 13, 1 },
|
|
{ "dead_cycle1_max_op", 12, 1 },
|
|
{ "dead_cycle0_pre_ref", 11, 1 },
|
|
{ "dead_cycle1_pre_ref", 10, 1 },
|
|
{ "dead_cycle0_post_ref", 9, 1 },
|
|
{ "dead_cycle1_post_ref", 8, 1 },
|
|
{ "dead_cycle0_rmw", 7, 1 },
|
|
{ "dead_cycle1_rmw", 6, 1 },
|
|
{ "dead_cycle0_bbi_rmw", 5, 1 },
|
|
{ "dead_cycle1_bbi_rmw", 4, 1 },
|
|
{ "dead_cycle0_pre_ref_rmw", 3, 1 },
|
|
{ "dead_cycle1_pre_ref_rmw", 2, 1 },
|
|
{ "dead_cycle0_post_ref_rmw", 1, 1 },
|
|
{ "dead_cycle1_post_ref_rmw", 0, 1 },
|
|
{ "EDC_H_DBG_CMD_QUEUE", 0x50380, 0 },
|
|
{ "ECmdNRE", 31, 1 },
|
|
{ "ECmdNRB", 30, 1 },
|
|
{ "ECmdWr", 29, 1 },
|
|
{ "ECmdLen", 22, 7 },
|
|
{ "ECmdAddr", 0, 22 },
|
|
{ "EDC_H_DBG_REFRESH", 0x50384, 0 },
|
|
{ "RefDone", 12, 1 },
|
|
{ "RefCntExpr", 11, 1 },
|
|
{ "RefPtr", 8, 3 },
|
|
{ "RefCnt", 0, 8 },
|
|
{ "EDC_H_BIST_CRC_SEED", 0x50400, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_edc_t61_regs[] = {
|
|
{ "EDC_H_REF", 0x50800, 0 },
|
|
{ "SleepStatus", 31, 1 },
|
|
{ "SleepReq", 30, 1 },
|
|
{ "PING_PONG", 29, 1 },
|
|
{ "QDR_ClkPhase", 24, 3 },
|
|
{ "MaxOpsPerTRC", 21, 3 },
|
|
{ "NumPipeStages", 19, 2 },
|
|
{ "EDC_INST_NUM", 18, 1 },
|
|
{ "ENABLE_PERF", 17, 1 },
|
|
{ "ECC_BYPASS", 16, 1 },
|
|
{ "RefFreq", 0, 16 },
|
|
{ "EDC_H_BIST_CMD", 0x50804, 0 },
|
|
{ "START_BIST", 31, 1 },
|
|
{ "BURST_LEN", 16, 2 },
|
|
{ "BIST_CMD_GAP", 8, 8 },
|
|
{ "BIST_OPCODE", 0, 2 },
|
|
{ "EDC_H_BIST_CMD_ADDR", 0x50808, 0 },
|
|
{ "EDC_H_BIST_CMD_LEN", 0x5080c, 0 },
|
|
{ "EDC_H_BIST_DATA_PATTERN", 0x50810, 0 },
|
|
{ "EDC_H_BIST_USER_WDATA0", 0x50814, 0 },
|
|
{ "EDC_H_BIST_USER_WDATA1", 0x50818, 0 },
|
|
{ "EDC_H_BIST_USER_WDATA2", 0x5081c, 0 },
|
|
{ "USER_DATA_MASK", 8, 9 },
|
|
{ "USER_DATA2", 0, 8 },
|
|
{ "EDC_H_BIST_NUM_ERR", 0x50820, 0 },
|
|
{ "EDC_H_BIST_ERR_FIRST_ADDR", 0x50824, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50828, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5082c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50830, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50834, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50838, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5083c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50840, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50844, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50848, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5084c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50850, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50854, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50858, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5085c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50860, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50864, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50868, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5086c, 0 },
|
|
{ "EDC_H_PAR_ENABLE", 0x50870, 0 },
|
|
{ "ECC_UE_PAR_ENABLE", 2, 1 },
|
|
{ "ECC_CE_PAR_ENABLE", 1, 1 },
|
|
{ "PERR_PAR_ENABLE", 0, 1 },
|
|
{ "EDC_H_INT_ENABLE", 0x50874, 0 },
|
|
{ "ECC_UE_INT_ENABLE", 2, 1 },
|
|
{ "ECC_CE_INT_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "EDC_H_INT_CAUSE", 0x50878, 0 },
|
|
{ "ECC_UE_INT0_CAUSE", 5, 1 },
|
|
{ "ECC_CE_INT0_CAUSE", 4, 1 },
|
|
{ "PERR_INT0_CAUSE", 3, 1 },
|
|
{ "ECC_UE_INT_CAUSE", 2, 1 },
|
|
{ "ECC_CE_INT_CAUSE", 1, 1 },
|
|
{ "PERR_INT_CAUSE", 0, 1 },
|
|
{ "EDC_H_ECC_STATUS", 0x5087c, 0 },
|
|
{ "ECC_CECNT", 16, 16 },
|
|
{ "ECC_UECNT", 0, 16 },
|
|
{ "EDC_H_ECC_ERR_SEL", 0x50880, 0 },
|
|
{ "EDC_H_ECC_ERR_ADDR", 0x50884, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50890, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50894, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50898, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x5089c, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508a0, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508a4, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508a8, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508ac, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508b0, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508b4, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508b8, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508bc, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508c0, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508c4, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508c8, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508cc, 0 },
|
|
{ "EDC_H_DBG_MA_CMD_INTF", 0x50b00, 0 },
|
|
{ "MCmdAddr", 12, 20 },
|
|
{ "MCmdLen", 5, 7 },
|
|
{ "MCmdNRE", 4, 1 },
|
|
{ "MCmdNRB", 3, 1 },
|
|
{ "MCmdWr", 2, 1 },
|
|
{ "MCmdRdy", 1, 1 },
|
|
{ "MCmdVld", 0, 1 },
|
|
{ "EDC_H_DBG_MA_WDATA_INTF", 0x50b04, 0 },
|
|
{ "MWDataVld", 31, 1 },
|
|
{ "MWDataRdy", 30, 1 },
|
|
{ "MWData", 0, 30 },
|
|
{ "EDC_H_DBG_MA_RDATA_INTF", 0x50b08, 0 },
|
|
{ "MRspVld", 31, 1 },
|
|
{ "MRspRdy", 30, 1 },
|
|
{ "MRspData", 0, 30 },
|
|
{ "EDC_H_DBG_BIST_CMD_INTF", 0x50b0c, 0 },
|
|
{ "BCmdAddr", 9, 23 },
|
|
{ "BCmdLen", 3, 6 },
|
|
{ "BCmdWr", 2, 1 },
|
|
{ "BCmdRdy", 1, 1 },
|
|
{ "BCmdVld", 0, 1 },
|
|
{ "EDC_H_DBG_BIST_WDATA_INTF", 0x50b10, 0 },
|
|
{ "BWDataVld", 31, 1 },
|
|
{ "BWDataRdy", 30, 1 },
|
|
{ "BWData", 0, 30 },
|
|
{ "EDC_H_DBG_BIST_RDATA_INTF", 0x50b14, 0 },
|
|
{ "BRspVld", 31, 1 },
|
|
{ "BRspRdy", 30, 1 },
|
|
{ "BRspData", 0, 30 },
|
|
{ "EDC_H_DBG_EDRAM_CMD_INTF", 0x50b18, 0 },
|
|
{ "EdramAddr", 16, 16 },
|
|
{ "EdramDwsn", 8, 8 },
|
|
{ "EdramCra", 5, 3 },
|
|
{ "EdramRefEnLo", 4, 1 },
|
|
{ "Edram1WrEnLo", 3, 1 },
|
|
{ "Edram1RdEnLo", 2, 1 },
|
|
{ "Edram0WrEnLo", 1, 1 },
|
|
{ "Edram0RdEnLo", 0, 1 },
|
|
{ "EDC_H_DBG_EDRAM_WDATA_INTF", 0x50b1c, 0 },
|
|
{ "EdramWData", 9, 23 },
|
|
{ "EdramWByteEn", 0, 9 },
|
|
{ "EDC_H_DBG_EDRAM0_RDATA_INTF", 0x50b20, 0 },
|
|
{ "EDC_H_DBG_EDRAM1_RDATA_INTF", 0x50b24, 0 },
|
|
{ "EDC_H_DBG_MA_WR_REQ_CNT", 0x50b28, 0 },
|
|
{ "EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT", 0x50b2c, 0 },
|
|
{ "EDC_H_DBG_MA_WR_DAT_CYC_CNT", 0x50b30, 0 },
|
|
{ "EDC_H_DBG_MA_RD_REQ_CNT", 0x50b34, 0 },
|
|
{ "EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT", 0x50b38, 0 },
|
|
{ "EDC_H_DBG_MA_RD_DAT_CYC_CNT", 0x50b3c, 0 },
|
|
{ "EDC_H_DBG_BIST_WR_REQ_CNT", 0x50b40, 0 },
|
|
{ "EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT", 0x50b44, 0 },
|
|
{ "EDC_H_DBG_BIST_WR_DAT_CYC_CNT", 0x50b48, 0 },
|
|
{ "EDC_H_DBG_BIST_RD_REQ_CNT", 0x50b4c, 0 },
|
|
{ "EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT", 0x50b50, 0 },
|
|
{ "EDC_H_DBG_BIST_RD_DAT_CYC_CNT", 0x50b54, 0 },
|
|
{ "EDC_H_DBG_EDRAM0_WR_REQ_CNT", 0x50b58, 0 },
|
|
{ "EDC_H_DBG_EDRAM0_RD_REQ_CNT", 0x50b5c, 0 },
|
|
{ "EDC_H_DBG_EDRAM0_RMW_CNT", 0x50b60, 0 },
|
|
{ "EDC_H_DBG_EDRAM1_WR_REQ_CNT", 0x50b64, 0 },
|
|
{ "EDC_H_DBG_EDRAM1_RD_REQ_CNT", 0x50b68, 0 },
|
|
{ "EDC_H_DBG_EDRAM1_RMW_CNT", 0x50b6c, 0 },
|
|
{ "EDC_H_DBG_EDRAM_REF_BURST_CNT", 0x50b70, 0 },
|
|
{ "EDC_H_DBG_FIFO_STATUS", 0x50b74, 0 },
|
|
{ "rdtag_notfull", 17, 1 },
|
|
{ "rdtag_notempty", 16, 1 },
|
|
{ "inp_cmdq_notfull_arb", 15, 1 },
|
|
{ "inp_cmdq_notempty", 14, 1 },
|
|
{ "inp_wrdq_wrrdy", 13, 1 },
|
|
{ "inp_wrdq_notempty", 12, 1 },
|
|
{ "inp_beq_wrrdy_open", 11, 1 },
|
|
{ "inp_beq_notempty", 10, 1 },
|
|
{ "rddq_notfull_open", 9, 1 },
|
|
{ "rddq_rdcnt", 4, 5 },
|
|
{ "rdsideq_notfull", 3, 1 },
|
|
{ "rdsideq_notempty", 2, 1 },
|
|
{ "stg_cmdq_notempty", 1, 1 },
|
|
{ "stg_wrdq_notempty", 0, 1 },
|
|
{ "EDC_H_DBG_FSM_STATE", 0x50b78, 0 },
|
|
{ "CmdSplitFsm", 3, 1 },
|
|
{ "CmdFsm", 0, 3 },
|
|
{ "EDC_H_DBG_STALL_CYCLES", 0x50b7c, 0 },
|
|
{ "stall_rmw", 19, 1 },
|
|
{ "stall_edc_cmd", 18, 1 },
|
|
{ "dead_cycle0", 17, 1 },
|
|
{ "dead_cycle1", 16, 1 },
|
|
{ "dead_cycle0_bbi", 15, 1 },
|
|
{ "dead_cycle1_bbi", 14, 1 },
|
|
{ "dead_cycle0_max_op", 13, 1 },
|
|
{ "dead_cycle1_max_op", 12, 1 },
|
|
{ "dead_cycle0_pre_ref", 11, 1 },
|
|
{ "dead_cycle1_pre_ref", 10, 1 },
|
|
{ "dead_cycle0_post_ref", 9, 1 },
|
|
{ "dead_cycle1_post_ref", 8, 1 },
|
|
{ "dead_cycle0_rmw", 7, 1 },
|
|
{ "dead_cycle1_rmw", 6, 1 },
|
|
{ "dead_cycle0_bbi_rmw", 5, 1 },
|
|
{ "dead_cycle1_bbi_rmw", 4, 1 },
|
|
{ "dead_cycle0_pre_ref_rmw", 3, 1 },
|
|
{ "dead_cycle1_pre_ref_rmw", 2, 1 },
|
|
{ "dead_cycle0_post_ref_rmw", 1, 1 },
|
|
{ "dead_cycle1_post_ref_rmw", 0, 1 },
|
|
{ "EDC_H_DBG_CMD_QUEUE", 0x50b80, 0 },
|
|
{ "ECmdNRE", 31, 1 },
|
|
{ "ECmdNRB", 30, 1 },
|
|
{ "ECmdWr", 29, 1 },
|
|
{ "ECmdLen", 22, 7 },
|
|
{ "ECmdAddr", 0, 22 },
|
|
{ "EDC_H_DBG_REFRESH", 0x50b84, 0 },
|
|
{ "RefDone", 12, 1 },
|
|
{ "RefCntExpr", 11, 1 },
|
|
{ "RefPtr", 8, 3 },
|
|
{ "RefCnt", 0, 8 },
|
|
{ "EDC_H_BIST_CRC_SEED", 0x50c00, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t6_hma_t6_regs[] = {
|
|
{ "HMA_TABLE_ACCESS", 0x51000, 0 },
|
|
{ "TRIG", 31, 1 },
|
|
{ "RW", 30, 1 },
|
|
{ "L_SEL", 0, 4 },
|
|
{ "HMA_TABLE_LINE0", 0x51004, 0 },
|
|
{ "HMA_TABLE_LINE1", 0x51008, 0 },
|
|
{ "HMA_TABLE_LINE2", 0x5100c, 0 },
|
|
{ "HMA_TABLE_LINE3", 0x51010, 0 },
|
|
{ "HMA_TABLE_LINE4", 0x51014, 0 },
|
|
{ "HMA_TABLE_LINE5", 0x51018, 0 },
|
|
{ "FID", 16, 11 },
|
|
{ "NOS", 15, 1 },
|
|
{ "RO", 14, 1 },
|
|
{ "TPH", 12, 2 },
|
|
{ "TPH_V", 11, 1 },
|
|
{ "DCA", 0, 11 },
|
|
{ "HMA_COOKIE", 0x5101c, 0 },
|
|
{ "C_REQ", 31, 1 },
|
|
{ "C_FID", 18, 11 },
|
|
{ "C_VAL", 8, 10 },
|
|
{ "C_SEL", 0, 4 },
|
|
{ "HMA_CFG", 0x51020, 0 },
|
|
{ "OP_MODE", 31, 1 },
|
|
{ "HMA_TLB_ACCESS", 0x51028, 0 },
|
|
{ "TRIG", 31, 1 },
|
|
{ "RW", 30, 1 },
|
|
{ "INV_ALL", 29, 1 },
|
|
{ "LOCK_ENTRY", 28, 1 },
|
|
{ "E_SEL", 0, 5 },
|
|
{ "HMA_TLB_BITS", 0x5102c, 0 },
|
|
{ "VA", 12, 20 },
|
|
{ "VALID_E", 4, 1 },
|
|
{ "LOCK", 3, 1 },
|
|
{ "USED", 2, 1 },
|
|
{ "REGION", 0, 2 },
|
|
{ "HMA_TLB_DESC_0_H", 0x51030, 0 },
|
|
{ "HMA_TLB_DESC_0_L", 0x51034, 0 },
|
|
{ "HMA_TLB_DESC_1_H", 0x51038, 0 },
|
|
{ "HMA_TLB_DESC_1_L", 0x5103c, 0 },
|
|
{ "HMA_TLB_DESC_2_H", 0x51040, 0 },
|
|
{ "HMA_TLB_DESC_2_L", 0x51044, 0 },
|
|
{ "HMA_TLB_DESC_3_H", 0x51048, 0 },
|
|
{ "HMA_TLB_DESC_3_L", 0x5104c, 0 },
|
|
{ "HMA_TLB_DESC_4_H", 0x51050, 0 },
|
|
{ "HMA_TLB_DESC_4_L", 0x51054, 0 },
|
|
{ "HMA_TLB_DESC_5_H", 0x51058, 0 },
|
|
{ "HMA_TLB_DESC_5_L", 0x5105c, 0 },
|
|
{ "HMA_TLB_DESC_6_H", 0x51060, 0 },
|
|
{ "HMA_TLB_DESC_6_L", 0x51064, 0 },
|
|
{ "HMA_TLB_DESC_7_H", 0x51068, 0 },
|
|
{ "HMA_TLB_DESC_7_L", 0x5106c, 0 },
|
|
{ "HMA_REG0_MIN", 0x51070, 0 },
|
|
{ "ADDR0_MIN", 12, 20 },
|
|
{ "HMA_REG0_MAX", 0x51074, 0 },
|
|
{ "ADDR0_MAX", 12, 20 },
|
|
{ "HMA_REG0_MASK", 0x51078, 0 },
|
|
{ "PAGE_SIZE0", 12, 20 },
|
|
{ "HMA_REG0_BASE", 0x5107c, 0 },
|
|
{ "HMA_REG1_MIN", 0x51080, 0 },
|
|
{ "ADDR1_MIN", 12, 20 },
|
|
{ "HMA_REG1_MAX", 0x51084, 0 },
|
|
{ "ADDR1_MAX", 12, 20 },
|
|
{ "HMA_REG1_MASK", 0x51088, 0 },
|
|
{ "PAGE_SIZE1", 12, 20 },
|
|
{ "HMA_REG1_BASE", 0x5108c, 0 },
|
|
{ "HMA_REG2_MIN", 0x51090, 0 },
|
|
{ "ADDR2_MIN", 12, 20 },
|
|
{ "HMA_REG2_MAX", 0x51094, 0 },
|
|
{ "ADDR2_MAX", 12, 20 },
|
|
{ "HMA_REG2_MASK", 0x51098, 0 },
|
|
{ "PAGE_SIZE2", 12, 20 },
|
|
{ "HMA_REG2_BASE", 0x5109c, 0 },
|
|
{ "HMA_REG3_MIN", 0x510a0, 0 },
|
|
{ "ADDR3_MIN", 12, 20 },
|
|
{ "HMA_REG3_MAX", 0x510a4, 0 },
|
|
{ "ADDR3_MAX", 12, 20 },
|
|
{ "HMA_REG3_MASK", 0x510a8, 0 },
|
|
{ "PAGE_SIZE3", 12, 20 },
|
|
{ "HMA_REG3_BASE", 0x510ac, 0 },
|
|
{ "HMA_SW_SYNC", 0x510b0, 0 },
|
|
{ "ENTER_SYNC", 31, 1 },
|
|
{ "EXIT_SYNC", 30, 1 },
|
|
{ "HMA_PAR_ENABLE", 0x51300, 0 },
|
|
{ "HMA_INT_ENABLE", 0x51304, 0 },
|
|
{ "IDTF_INT_ENABLE", 5, 1 },
|
|
{ "OTF_INT_ENABLE", 4, 1 },
|
|
{ "RTF_INT_ENABLE", 3, 1 },
|
|
{ "PCIEMST_INT_ENABLE", 2, 1 },
|
|
{ "MAMST_INT_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "HMA_INT_CAUSE", 0x51308, 0 },
|
|
{ "IDTF_INT_CAUSE", 5, 1 },
|
|
{ "OTF_INT_CAUSE", 4, 1 },
|
|
{ "RTF_INT_CAUSE", 3, 1 },
|
|
{ "PCIEMST_INT_CAUSE", 2, 1 },
|
|
{ "MAMST_INT_CAUSE", 1, 1 },
|
|
{ "PERR_INT_CAUSE", 0, 1 },
|
|
{ "HMA_MA_MST_ERR", 0x5130c, 0 },
|
|
{ "HMA_RTF_ERR", 0x51310, 0 },
|
|
{ "HMA_OTF_ERR", 0x51314, 0 },
|
|
{ "HMA_IDTF_ERR", 0x51318, 0 },
|
|
{ "HMA_EXIT_TF", 0x5131c, 0 },
|
|
{ "TRIG", 31, 1 },
|
|
{ "RTF", 30, 1 },
|
|
{ "OTF", 29, 1 },
|
|
{ "IDTF", 28, 1 },
|
|
{ "HMA_LOCAL_DEBUG_CFG", 0x51320, 0 },
|
|
{ "DEBUG_OR", 15, 1 },
|
|
{ "DEBUG_HI", 14, 1 },
|
|
{ "DEBUG_RPT", 13, 1 },
|
|
{ "DEBUGPAGE", 10, 3 },
|
|
{ "DEBUGSELH", 5, 5 },
|
|
{ "DEBUGSELL", 0, 5 },
|
|
{ "HMA_LOCAL_DEBUG_RPT", 0x51324, 0 },
|
|
{ NULL }
|
|
};
|