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00ad14c702
should add more comments explaining which registers hold which variables. Spotted by: bde
155 lines
3.3 KiB
ArmAsm
155 lines
3.3 KiB
ArmAsm
.file "__umoddi3.s"
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// $FreeBSD$
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//
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// Copyright (c) 2000, Intel Corporation
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// All rights reserved.
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//
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// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
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// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
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// Intel Corporation.
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//
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// WARRANTY DISCLAIMER
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Intel Corporation is the author of this code, and requests that all
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// problem reports or change requests be submitted to it directly at
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// http://developer.intel.com/opensource.
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//
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.section .text
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// 64-bit unsigned integer remainder
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.proc __umoddi3#
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.align 32
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.global __umoddi3#
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.align 32
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__umoddi3:
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{ .mii
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alloc r31=ar.pfs,3,0,0,0
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nop.i 0
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nop.i 0
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} { .mmb
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// 64-BIT UNSIGNED INTEGER REMAINDER BEGINS HERE
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// general register used:
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// r32 - 64-bit unsigned integer dividend, called a below
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// r33 - 64-bit unsigned integer divisor, called b below
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// r8 - 64-bit unsigned integer result
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// floating-point registers used: f6, f7, f8, f9, f10, f11, f12
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// predicate registers used: p6
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setf.sig f12=r32 // holds a in integer form
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setf.sig f7=r33
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nop.b 0;;
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} { .mfi
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// get 2's complement of b
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sub r33=r0,r33
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fcvt.xuf.s1 f6=f12
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nop.i 0
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} { .mfi
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nop.m 0
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fcvt.xuf.s1 f7=f7
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nop.i 0;;
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} { .mfi
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nop.m 0
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// Step (1)
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// y0 = 1 / b in f8
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frcpa.s1 f8,p6=f6,f7
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nop.i 0;;
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} { .mfi
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nop.m 0
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// Step (2)
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// q0 = a * y0 in f10
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(p6) fma.s1 f10=f6,f8,f0
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nop.i 0
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} { .mfi
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nop.m 0
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// Step (3)
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// e0 = 1 - b * y0 in f9
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(p6) fnma.s1 f9=f7,f8,f1
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nop.i 0;;
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} { .mfi
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nop.m 0
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// Step (4)
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// q1 = q0 + e0 * q0 in f10
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(p6) fma.s1 f10=f9,f10,f10
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nop.i 0
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} { .mfi
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nop.m 0
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// Step (5)
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// e1 = e0 * e0 in f11
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(p6) fma.s1 f11=f9,f9,f0
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nop.i 0;;
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} { .mfi
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nop.m 0
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// Step (6)
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// y1 = y0 + e0 * y0 in f8
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(p6) fma.s1 f8=f9,f8,f8
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nop.i 0;;
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} { .mfi
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nop.m 0
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// Step (7)
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// q2 = q1 + e1 * q1 in f9
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(p6) fma.s1 f9=f11,f10,f10
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nop.i 0;;
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} { .mfi
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nop.m 0
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// Step (8)
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// y2 = y1 + e1 * y1 in f8
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(p6) fma.s1 f8=f11,f8,f8
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nop.i 0;;
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} { .mfi
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nop.m 0
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// Step (9)
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// r2 = a - b * q2 in f10
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(p6) fnma.s1 f10=f7,f9,f6
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nop.i 0;;
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} { .mfi
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// f7=-b
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setf.sig f7=r33
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// Step (10)
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// q3 = q2 + r2 * y2 in f8
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(p6) fma.s1 f8=f10,f8,f9
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nop.i 0;;
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} { .mfi
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nop.m 0
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// (11) q = trunc(q3)
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fcvt.fxu.trunc.s1 f8=f8
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nop.i 0;;
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} { .mfi
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nop.m 0
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// (12) r = a + (-b) * q
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xma.l f8=f8,f7,f12
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nop.i 0;;
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} { .mib
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getf.sig r8=f8
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nop.i 0
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nop.b 0
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}
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// 64-BIT UNSIGNED INTEGER REMAINDER ENDS HERE
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{ .mib
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nop.m 0
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nop.i 0
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br.ret.sptk b0;;
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}
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.endp __umoddi3
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