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4cd2e9581f
This reverts a private patch which is causing issues with many Intel chipsets. I will review that patch and see what we need to do to fix it up later, but for the time being, we will just get these chips working again. This update contains a lot of code cleanup and is post gem merge (no, we don't have gem support). It should prove much easier to read the code now. A lot of thanks goes to vehemens for that work. I have adapted the code to use cdevpriv for tracking per open file data. That alleviates the old ugly hack that we used to try and accomplish the task and helped to clean up the open / close behavior a good bit. This also replaces the hack that was put in place a year or so ago to prevent radeons from locking up with AIGLX enabled. I have had a couple of radeon testers report that it still works as expected, though I no longer have radeon hardware to test with myself. Other various fixes from the linux crew and Intel, many of which are muddled in with the gem merge. Approved by: jhb (mentor) Obtained from: mesa/drm git master MFC after: 2 weeks
92 lines
2.5 KiB
C
92 lines
2.5 KiB
C
/**
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* \file drm_atomic.h
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* Atomic operations used in the DRM which may or may not be provided by the OS.
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*
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* \author Eric Anholt <anholt@FreeBSD.org>
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*/
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/*-
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* Copyright 2004 Eric Anholt
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/* Many of these implementations are rather fake, but good enough. */
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typedef u_int32_t atomic_t;
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#define atomic_set(p, v) (*(p) = (v))
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#define atomic_read(p) (*(p))
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#define atomic_inc(p) atomic_add_int(p, 1)
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#define atomic_dec(p) atomic_subtract_int(p, 1)
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#define atomic_add(n, p) atomic_add_int(p, n)
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#define atomic_sub(n, p) atomic_subtract_int(p, n)
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static __inline atomic_t
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test_and_set_bit(int b, volatile void *p)
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{
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int s = splhigh();
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unsigned int m = 1<<b;
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unsigned int r = *(volatile int *)p & m;
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*(volatile int *)p |= m;
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splx(s);
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return r;
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}
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static __inline void
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clear_bit(int b, volatile void *p)
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{
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atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
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}
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static __inline void
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set_bit(int b, volatile void *p)
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{
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atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
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}
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static __inline int
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test_bit(int b, volatile void *p)
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{
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return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
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}
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static __inline int
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find_first_zero_bit(volatile void *p, int max)
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{
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int b;
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volatile int *ptr = (volatile int *)p;
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for (b = 0; b < max; b += 32) {
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if (ptr[b >> 5] != ~0) {
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for (;;) {
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if ((ptr[b >> 5] & (1 << (b & 0x1f))) == 0)
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return b;
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b++;
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}
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}
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}
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return max;
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}
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