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dc4ee6ca91
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
147 lines
3.7 KiB
C
147 lines
3.7 KiB
C
/*-
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* Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/smp.h>
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#include <sys/systm.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/smp.h>
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#include <mips/cavium/octeon_pcmap_regs.h>
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#include <contrib/octeon-sdk/cvmx.h>
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#include <mips/cavium/octeon_irq.h>
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unsigned octeon_ap_boot = ~0;
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void
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platform_ipi_send(int cpuid)
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{
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cvmx_write_csr(CVMX_CIU_MBOX_SETX(cpuid), 1);
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mips_wbflush();
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}
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void
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platform_ipi_clear(void)
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{
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uint64_t action;
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action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)));
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KASSERT(action == 1, ("unexpected IPIs: %#jx", (uintmax_t)action));
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cvmx_write_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action);
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}
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int
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platform_ipi_intrnum(void)
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{
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return (1);
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}
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void
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platform_init_ap(int cpuid)
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{
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unsigned ciu_int_mask, clock_int_mask, ipi_int_mask;
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/*
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* Set the exception base.
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*/
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mips_wr_ebase(0x80000000);
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/*
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* Clear any pending IPIs.
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*/
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cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff);
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/*
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* Set up interrupts.
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*/
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octeon_ciu_reset();
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/*
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* Unmask the clock, ipi and ciu interrupts.
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*/
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ciu_int_mask = hard_int_mask(0);
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clock_int_mask = hard_int_mask(5);
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ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
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set_intr_mask(ciu_int_mask | clock_int_mask | ipi_int_mask);
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mips_wbflush();
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}
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void
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platform_cpu_mask(cpuset_t *mask)
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{
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uint64_t core_mask = cvmx_sysinfo_get()->core_mask;
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uint64_t i, m;
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CPU_ZERO(mask);
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for (i = 0, m = 1 ; i < MAXCPU; i++, m <<= 1)
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if (core_mask & m)
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CPU_SET(i, mask);
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}
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struct cpu_group *
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platform_smp_topo(void)
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{
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return (smp_topo_none());
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}
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int
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platform_start_ap(int cpuid)
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{
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uint64_t cores_in_reset;
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/*
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* Release the core if it is in reset, and let it rev up a bit.
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* The real synchronization happens below via octeon_ap_boot.
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*/
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cores_in_reset = cvmx_read_csr(CVMX_CIU_PP_RST);
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if (cores_in_reset & (1ULL << cpuid)) {
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if (bootverbose)
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printf ("AP #%d still in reset\n", cpuid);
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cores_in_reset &= ~(1ULL << cpuid);
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cvmx_write_csr(CVMX_CIU_PP_RST, (uint64_t)(cores_in_reset));
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DELAY(2000); /* Give it a moment to start */
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}
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if (atomic_cmpset_32(&octeon_ap_boot, ~0, cpuid) == 0)
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return (-1);
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for (;;) {
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DELAY(1000);
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if (atomic_cmpset_32(&octeon_ap_boot, 0, ~0) != 0)
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return (0);
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printf("Waiting for cpu%d to start\n", cpuid);
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}
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}
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