Konstantin Belousov af95bbf5bf Intel SDM before revision 56 described the CLFLUSH instruction as only ... ordered with the MFENCE instruction. Similar weak guarantees are also specified by the AMD APM vol. 3 rev. 3.22. x86 pmap methods pmap_invalidate_cache_range() and pmap_invalidate_cache_pages() braced CLFLUSH loop with MFENCE both before and after the loop. In the revision 56 of SDM, Intel stated that all existing implementations of CLFLUSH are strict, CLFLUSH instructions execution is ordered WRT other CLFLUSH and writes. Also, the strict behaviour is made architectural. A new instruction CLFLUSHOPT (which was documented for some time in the Instruction Set Extensions Programming Reference) provides the weak behaviour which was previously attributed to CLFLUSH. Use CLFLUSHOPT when available. When CLFLUSH is used on Intel CPUs, do not execute MFENCE before and after the flushing loop. Reviewed by: alc Sponsored by: The FreeBSD Foundation		2015-10-24 21:37:47 +00:00
..
acpica	If x86 CPU implementation of the MWAIT instruction reasonably	2015-05-09 12:28:48 +00:00
bios	Pull in r267961 and r267973 again. Fix for issues reported will follow.	2014-06-28 03:56:17 +00:00
conf	Remove compatibility shims for legacy ATA device names.	2015-10-11 13:01:51 +00:00
i386	Intel SDM before revision 56 described the CLFLUSH instruction as only	2015-10-24 21:37:47 +00:00
ibcs2	Replace struct filedesc argument in getvnode with struct thread	2015-06-16 13:09:18 +00:00
include	Add CLFLUSHOPT instruction wrappers.	2015-10-23 11:45:38 +00:00
isa	Convert between abridged (from FXSAVE) and unabridged (from FSAVE)	2015-07-10 09:20:13 +00:00
linux	Fix missing semi-colon from r289055.	2015-10-08 23:27:45 +00:00
pci	Remove support for Xen PV domU kernels. Support for HVM domU kernels	2015-04-30 15:48:48 +00:00
svr4	MFamd64: Move extern declaration of _ucodesel and _udatasel to	2014-11-02 21:40:32 +00:00
xbox
Makefile