Olivier Houchard 4168e66b1f In __bswap16_var(), make sure the 16 upper bits are cleared; while ... optimizing, gcc4 doesn't always do so. Reported by: Nathan Whitehorn Approved by: re (blanket)		2007-09-09 11:58:38 +00:00
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_bus.h
_inttypes.h
_limits.h
_stdint.h
_types.h
armreg.h	XScale core 3 definitions.	2007-07-27 14:54:27 +00:00
asm.h
asmacros.h
atomic.h
blockio.h
bootconfig.h
bus_dma.h
bus.h
clock.h
cpu.h
cpuconf.h
cpufunc.h	Add a new set of functions to handle L2 cache. Make them no-op for every	2007-07-27 14:39:41 +00:00
db_machdep.h
disassem.h
elf.h
endian.h	In __bswap16_var(), make sure the 16 upper bits are cleared; while	2007-09-09 11:58:38 +00:00
exec.h
fiq.h
float.h
floatingpoint.h
fp.h
frame.h
gdb_machdep.h
ieee.h
ieeefp.h
in_cksum.h
intr.h	The iop34x has 128 interrupts.	2007-06-16 15:03:33 +00:00
katelib.h
kdb.h	Add kdb_cpu_sync_icache(), intended to synchronize instruction	2007-06-09 21:55:17 +00:00
limits.h
machdep.h
md_var.h
memdev.h
metadata.h
mutex.h
param.h
pcb.h
pcpu.h	- PCPU_ADD is no longer spelled with LAZY_ in the middle.	2007-06-06 23:23:47 +00:00
pmap.h	Properly handle supersections.	2007-07-27 14:45:04 +00:00
pmc_mdep.h
proc.h
profile.h
psl.h
pte.h	Fix the cache mode description.	2007-07-27 14:45:33 +00:00
ptrace.h
reg.h
reloc.h
resource.h
runq.h
setjmp.h
sf_buf.h
sigframe.h
signal.h
smp.h
stdarg.h
swi.h
sysarch.h
trap.h
ucontext.h
undefined.h
utrap.h
vmparam.h	Add the machine-specific definitions for configuring the new physical	2007-06-04 08:02:22 +00:00