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71 lines
2.3 KiB
C
71 lines
2.3 KiB
C
/* $NetBSD: locore.h,v 1.78 2007/10/17 19:55:36 garbled Exp $ */
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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* Junior University. All Rights Reserved.
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*
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* Permission to use, copy, modify, and distribute this
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* software and its documentation for any purpose and without
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* fee is hereby granted, provided that the above copyright
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* notice appear in all copies. Stanford University
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* makes no representations about the suitability of this
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* software for any purpose. It is provided "as is" without
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* express or implied warranty.
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*
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* $FreeBSD$
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*/
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/*
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* Jump table for MIPS cpu locore functions that are implemented
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* differently on different generations, or instruction-level
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* archtecture (ISA) level, the Mips family.
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*
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* We currently provide support for MIPS I and MIPS III.
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*/
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#ifndef _MIPS_LOCORE_H
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#define _MIPS_LOCORE_H
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#include <machine/cpufunc.h>
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#include <machine/cpuregs.h>
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#include <machine/frame.h>
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#include <machine/md_var.h>
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/*
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* CPU identification, from PRID register.
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*/
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typedef int mips_prid_t;
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#define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff)
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#define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff)
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/* pre-MIPS32/64 */
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#define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff)
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#define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f)
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#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f)
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/* MIPS32/64 */
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#define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */
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#define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */
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#define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */
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#define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */
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#define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */
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#define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */
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#define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */
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#define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */
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#define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */
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#define MIPS_PRID_CID_LSI 0x08 /* LSI */
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/* 0x09 unannounced */
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/* 0x0a unannounced */
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#define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */
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#define MIPS_PRID_CID_RMI 0x0c /* RMI */
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#define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */
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#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */
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#ifdef _KERNEL
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#ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG
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void mips_machdep_cache_config(void);
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#endif
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#endif /* _KERNEL */
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#endif /* _MIPS_LOCORE_H */
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