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bda8e754a1
- Implement bus_adjust_resource() methods as far as necessary and in non-PCI bridge drivers as far as feasible without rototilling them. - As NEW_PCIB does a layering violation by activating resources at layers above pci(4) without previously bubbling up their allocation there, move the assignment of bus tags and handles from the bus_alloc_resource() to the bus_activate_resource() methods like at least the other NEW_PCIB enabled architectures do. This is somewhat unfortunate as previously sparc64 (ab)used resource activation to indicate whether SYS_RES_MEMORY resources should be mapped into KVA, which is only necessary if their going to be accessed via the pointer returned from rman_get_virtual() but not for bus_space(9) as the later always uses physical access on sparc64. Besides wasting KVA if we always map in SYS_RES_MEMORY resources, a driver also may deliberately not map them in if the firmware already has done so, possibly in a special way. So in order to still allow a driver to decide whether a SYS_RES_MEMORY resource should be mapped into KVA we let it indicate that by calling bus_space_map(9) with BUS_SPACE_MAP_LINEAR as actually documented in the bus_space(9) page. This is implemented by allocating a separate bus tag per SYS_RES_MEMORY resource and passing the resource via the previously unused bus tag cookie so we later on can call rman_set_virtual() in sparc64_bus_mem_map(). As a side effect this now also allows to actually indicate that a SYS_RES_MEMORY resource should be mapped in as cacheable and/or read-only via BUS_SPACE_MAP_CACHEABLE and BUS_SPACE_MAP_READONLY respectively. - Do some minor cleanup like taking advantage of rman_init_from_resource(), factor out the common part of bus tag allocation into a newly added sparc64_alloc_bus_tag(), hook up some missing newbus methods and replace some homegrown versions with the generic counterparts etc. - While at it, let apb_attach() (which can't use the generic NEW_PCIB code as APB bridges just don't have the base and limit registers implemented) regarding the config space registers cached in pcib_softc and the SYSCTL reporting nodes set up.
855 lines
22 KiB
C
855 lines
22 KiB
C
/*-
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* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1997-1999 Eduardo E. Horvath. All rights reserved.
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* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from: NetBSD: bus.h,v 1.58 2008/04/28 20:23:36 martin Exp
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* and
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* from: FreeBSD: src/sys/alpha/include/bus.h,v 1.9 2001/01/09
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_BUS_H_
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#define _MACHINE_BUS_H_
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#ifdef BUS_SPACE_DEBUG
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#include <sys/ktr.h>
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#endif
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#include <machine/_bus.h>
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#include <machine/cpufunc.h>
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/*
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* Nexus and SBus spaces are non-cached and big endian
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* (except for RAM and PROM)
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*
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* PCI spaces are non-cached and little endian
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*/
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#define NEXUS_BUS_SPACE 0
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#define SBUS_BUS_SPACE 1
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#define PCI_CONFIG_BUS_SPACE 2
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#define PCI_IO_BUS_SPACE 3
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#define PCI_MEMORY_BUS_SPACE 4
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#define LAST_BUS_SPACE 5
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extern const int bus_type_asi[];
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extern const int bus_stream_asi[];
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#define __BUS_SPACE_HAS_STREAM_METHODS 1
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#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF
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#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
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#define BUS_SPACE_MAXSIZE 0xFFFFFFFFFFFFFFFF
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#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF
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#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
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#define BUS_SPACE_MAXADDR 0xFFFFFFFF
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#define BUS_SPACE_UNRESTRICTED (~0)
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struct bus_space_tag {
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void *bst_cookie;
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bus_space_tag_t bst_parent;
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int bst_type;
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void (*bst_bus_barrier)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, bus_size_t, int);
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};
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/*
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* Bus space function prototypes.
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*/
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static void bus_space_barrier(bus_space_tag_t, bus_space_handle_t, bus_size_t,
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bus_size_t, int);
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static int bus_space_subregion(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, bus_size_t, bus_space_handle_t *);
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/*
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* Map a region of device bus space into CPU virtual address space.
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*/
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int bus_space_map(bus_space_tag_t tag, bus_addr_t address, bus_size_t size,
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int flags, bus_space_handle_t *handlep);
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/*
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* Unmap a region of device bus space.
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*/
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void bus_space_unmap(bus_space_tag_t tag, bus_space_handle_t handle,
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bus_size_t size);
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/* This macro finds the first "upstream" implementation of method `f' */
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#define _BS_CALL(t,f) \
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while (t->f == NULL) \
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t = t->bst_parent; \
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return (*(t)->f)
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static __inline void
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bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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bus_size_t s, int f)
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{
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_BS_CALL(t, bst_bus_barrier)(t, h, o, s, f);
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}
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static __inline int
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bus_space_subregion(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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bus_size_t s, bus_space_handle_t *hp)
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{
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*hp = h + o;
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return (0);
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}
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/* flags for bus space map functions */
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#define BUS_SPACE_MAP_CACHEABLE 0x0001
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#define BUS_SPACE_MAP_LINEAR 0x0002
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#define BUS_SPACE_MAP_READONLY 0x0004
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#define BUS_SPACE_MAP_PREFETCHABLE 0x0008
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/* placeholders for bus functions... */
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#define BUS_SPACE_MAP_BUS1 0x0100
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#define BUS_SPACE_MAP_BUS2 0x0200
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#define BUS_SPACE_MAP_BUS3 0x0400
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#define BUS_SPACE_MAP_BUS4 0x0800
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/* flags for bus_space_barrier() */
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#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
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#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
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#ifdef BUS_SPACE_DEBUG
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#define KTR_BUS KTR_SPARE2
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#define __BUS_DEBUG_ACCESS(h, o, desc, sz) do { \
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CTR4(KTR_BUS, "bus space: %s %d: handle %#lx, offset %#lx", \
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(desc), (sz), (h), (o)); \
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} while (0)
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#else
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#define __BUS_DEBUG_ACCESS(h, o, desc, sz)
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#endif
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static __inline uint8_t
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bus_space_read_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
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{
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__BUS_DEBUG_ACCESS(h, o, "read", 1);
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return (lduba_nc((caddr_t)(h + o), bus_type_asi[t->bst_type]));
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}
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static __inline uint16_t
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bus_space_read_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
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{
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__BUS_DEBUG_ACCESS(h, o, "read", 2);
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return (lduha_nc((caddr_t)(h + o), bus_type_asi[t->bst_type]));
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}
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static __inline uint32_t
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bus_space_read_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
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{
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__BUS_DEBUG_ACCESS(h, o, "read", 4);
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return (lduwa_nc((caddr_t)(h + o), bus_type_asi[t->bst_type]));
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}
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static __inline uint64_t
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bus_space_read_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
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{
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__BUS_DEBUG_ACCESS(h, o, "read", 8);
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return (ldxa_nc((caddr_t)(h + o), bus_type_asi[t->bst_type]));
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}
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static __inline void
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bus_space_read_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint8_t *a, size_t c)
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{
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while (c-- > 0)
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*a++ = bus_space_read_1(t, h, o);
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}
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static __inline void
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bus_space_read_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint16_t *a, size_t c)
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{
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while (c-- > 0)
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*a++ = bus_space_read_2(t, h, o);
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}
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static __inline void
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bus_space_read_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint32_t *a, size_t c)
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{
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while (c-- > 0)
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*a++ = bus_space_read_4(t, h, o);
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}
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static __inline void
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bus_space_read_multi_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint64_t *a, size_t c)
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{
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while (c-- > 0)
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*a++ = bus_space_read_8(t, h, o);
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}
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static __inline void
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bus_space_write_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint8_t v)
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{
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__BUS_DEBUG_ACCESS(h, o, "write", 1);
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stba_nc((caddr_t)(h + o), bus_type_asi[t->bst_type], v);
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}
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static __inline void
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bus_space_write_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint16_t v)
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{
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__BUS_DEBUG_ACCESS(h, o, "write", 2);
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stha_nc((caddr_t)(h + o), bus_type_asi[t->bst_type], v);
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}
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static __inline void
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bus_space_write_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint32_t v)
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{
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__BUS_DEBUG_ACCESS(h, o, "write", 4);
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stwa_nc((caddr_t)(h + o), bus_type_asi[t->bst_type], v);
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}
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static __inline void
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bus_space_write_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint64_t v)
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{
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__BUS_DEBUG_ACCESS(h, o, "write", 8);
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stxa_nc((caddr_t)(h + o), bus_type_asi[t->bst_type], v);
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}
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static __inline void
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bus_space_write_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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const uint8_t *a, size_t c)
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{
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while (c-- > 0)
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bus_space_write_1(t, h, o, *a++);
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}
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static __inline void
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bus_space_write_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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const uint16_t *a, size_t c)
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{
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while (c-- > 0)
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bus_space_write_2(t, h, o, *a++);
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}
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static __inline void
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bus_space_write_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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const uint32_t *a, size_t c)
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{
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while (c-- > 0)
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bus_space_write_4(t, h, o, *a++);
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}
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static __inline void
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bus_space_write_multi_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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const uint64_t *a, size_t c)
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{
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while (c-- > 0)
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bus_space_write_8(t, h, o, *a++);
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}
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static __inline void
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bus_space_set_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint8_t v, size_t c)
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{
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while (c-- > 0)
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bus_space_write_1(t, h, o, v);
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}
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static __inline void
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bus_space_set_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint16_t v, size_t c)
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{
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while (c-- > 0)
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bus_space_write_2(t, h, o, v);
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}
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static __inline void
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bus_space_set_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint32_t v, size_t c)
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{
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while (c-- > 0)
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bus_space_write_4(t, h, o, v);
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}
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static __inline void
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bus_space_set_multi_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint64_t v, size_t c)
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{
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while (c-- > 0)
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bus_space_write_8(t, h, o, v);
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}
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static __inline void
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bus_space_read_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint8_t *a, bus_size_t c)
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{
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for (; c; a++, c--, o++)
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*a = bus_space_read_1(t, h, o);
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}
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static __inline void
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bus_space_read_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint16_t *a, bus_size_t c)
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{
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for (; c; a++, c--, o += 2)
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*a = bus_space_read_2(t, h, o);
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}
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static __inline void
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bus_space_read_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint32_t *a, bus_size_t c)
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{
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for (; c; a++, c--, o += 4)
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*a = bus_space_read_4(t, h, o);
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}
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static __inline void
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bus_space_read_region_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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uint64_t *a, bus_size_t c)
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{
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for (; c; a++, c--, o += 8)
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*a = bus_space_read_8(t, h, o);
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}
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static __inline void
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bus_space_write_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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const uint8_t *a, bus_size_t c)
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{
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for (; c; a++, c--, o++)
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bus_space_write_1(t, h, o, *a);
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}
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static __inline void
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bus_space_write_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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const uint16_t *a, bus_size_t c)
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{
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for (; c; a++, c--, o += 2)
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bus_space_write_2(t, h, o, *a);
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}
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static __inline void
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bus_space_write_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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const uint32_t *a, bus_size_t c)
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{
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for (; c; a++, c--, o += 4)
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bus_space_write_4(t, h, o, *a);
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}
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static __inline void
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bus_space_write_region_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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const uint64_t *a, bus_size_t c)
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{
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for (; c; a++, c--, o += 8)
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bus_space_write_8(t, h, o, *a);
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}
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static __inline void
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bus_space_set_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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const uint8_t v, bus_size_t c)
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{
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for (; c; c--, o++)
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bus_space_write_1(t, h, o, v);
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}
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static __inline void
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bus_space_set_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
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|
const uint16_t v, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o += 2)
|
|
bus_space_write_2(t, h, o, v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
|
|
const uint32_t v, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o += 4)
|
|
bus_space_write_4(t, h, o, v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_region_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
|
|
const uint64_t v, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o += 8)
|
|
bus_space_write_8(t, h, o, v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_copy_region_1(bus_space_tag_t t, bus_space_handle_t h1,
|
|
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o1++, o2++)
|
|
bus_space_write_1(t, h1, o1, bus_space_read_1(t, h2, o2));
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_copy_region_2(bus_space_tag_t t, bus_space_handle_t h1,
|
|
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o1 += 2, o2 += 2)
|
|
bus_space_write_2(t, h1, o1, bus_space_read_2(t, h2, o2));
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_copy_region_4(bus_space_tag_t t, bus_space_handle_t h1,
|
|
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o1 += 4, o2 += 4)
|
|
bus_space_write_4(t, h1, o1, bus_space_read_4(t, h2, o2));
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_copy_region_8(bus_space_tag_t t, bus_space_handle_t h1,
|
|
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o1 += 8, o2 += 8)
|
|
bus_space_write_8(t, h1, o1, bus_space_read_8(t, h2, o2));
|
|
}
|
|
|
|
static __inline uint8_t
|
|
bus_space_read_stream_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
|
|
{
|
|
|
|
__BUS_DEBUG_ACCESS(h, o, "read stream", 1);
|
|
return (lduba_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type]));
|
|
}
|
|
|
|
static __inline uint16_t
|
|
bus_space_read_stream_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
|
|
{
|
|
|
|
__BUS_DEBUG_ACCESS(h, o, "read stream", 2);
|
|
return (lduha_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type]));
|
|
}
|
|
|
|
static __inline uint32_t
|
|
bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
|
|
{
|
|
|
|
__BUS_DEBUG_ACCESS(h, o, "read stream", 4);
|
|
return (lduwa_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type]));
|
|
}
|
|
|
|
static __inline uint64_t
|
|
bus_space_read_stream_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
|
|
{
|
|
|
|
__BUS_DEBUG_ACCESS(h, o, "read stream", 8);
|
|
return (ldxa_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type]));
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_read_multi_stream_1(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, uint8_t *a, size_t c)
|
|
{
|
|
|
|
while (c-- > 0)
|
|
*a++ = bus_space_read_stream_1(t, h, o);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_read_multi_stream_2(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, uint16_t *a, size_t c)
|
|
{
|
|
|
|
while (c-- > 0)
|
|
*a++ = bus_space_read_stream_2(t, h, o);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_read_multi_stream_4(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, uint32_t *a, size_t c)
|
|
{
|
|
|
|
while (c-- > 0)
|
|
*a++ = bus_space_read_stream_4(t, h, o);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_read_multi_stream_8(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, uint64_t *a, size_t c)
|
|
{
|
|
|
|
while (c-- > 0)
|
|
*a++ = bus_space_read_stream_8(t, h, o);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_stream_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
|
|
uint8_t v)
|
|
{
|
|
|
|
__BUS_DEBUG_ACCESS(h, o, "write stream", 1);
|
|
stba_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type], v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_stream_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
|
|
uint16_t v)
|
|
{
|
|
|
|
__BUS_DEBUG_ACCESS(h, o, "write stream", 2);
|
|
stha_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type], v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
|
|
uint32_t v)
|
|
{
|
|
|
|
__BUS_DEBUG_ACCESS(h, o, "write stream", 4);
|
|
stwa_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type], v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_stream_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
|
|
uint64_t v)
|
|
{
|
|
|
|
__BUS_DEBUG_ACCESS(h, o, "write stream", 8);
|
|
stxa_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type], v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_multi_stream_1(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, const uint8_t *a, size_t c)
|
|
{
|
|
|
|
while (c-- > 0)
|
|
bus_space_write_stream_1(t, h, o, *a++);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_multi_stream_2(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, const uint16_t *a, size_t c)
|
|
{
|
|
|
|
while (c-- > 0)
|
|
bus_space_write_stream_2(t, h, o, *a++);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_multi_stream_4(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, const uint32_t *a, size_t c)
|
|
{
|
|
|
|
while (c-- > 0)
|
|
bus_space_write_stream_4(t, h, o, *a++);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_multi_stream_8(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, const uint64_t *a, size_t c)
|
|
{
|
|
|
|
while (c-- > 0)
|
|
bus_space_write_stream_8(t, h, o, *a++);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_multi_stream_1(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, uint8_t v, size_t c)
|
|
{
|
|
|
|
while (c-- > 0)
|
|
bus_space_write_stream_1(t, h, o, v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_multi_stream_2(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, uint16_t v, size_t c)
|
|
{
|
|
|
|
while (c-- > 0)
|
|
bus_space_write_stream_2(t, h, o, v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_multi_stream_4(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, uint32_t v, size_t c)
|
|
{
|
|
|
|
while (c-- > 0)
|
|
bus_space_write_stream_4(t, h, o, v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_multi_stream_8(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, uint64_t v, size_t c)
|
|
{
|
|
|
|
while (c-- > 0)
|
|
bus_space_write_stream_8(t, h, o, v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_read_region_stream_1(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, uint8_t *a, bus_size_t c)
|
|
{
|
|
|
|
for (; c; a++, c--, o++)
|
|
*a = bus_space_read_stream_1(t, h, o);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_read_region_stream_2(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, uint16_t *a, bus_size_t c)
|
|
{
|
|
|
|
for (; c; a++, c--, o += 2)
|
|
*a = bus_space_read_stream_2(t, h, o);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, uint32_t *a, bus_size_t c)
|
|
{
|
|
|
|
for (; c; a++, c--, o += 4)
|
|
*a = bus_space_read_stream_4(t, h, o);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_read_region_stream_8(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, uint64_t *a, bus_size_t c)
|
|
{
|
|
|
|
for (; c; a++, c--, o += 8)
|
|
*a = bus_space_read_stream_8(t, h, o);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_region_stream_1(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, const uint8_t *a, bus_size_t c)
|
|
{
|
|
|
|
for (; c; a++, c--, o++)
|
|
bus_space_write_stream_1(t, h, o, *a);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_region_stream_2(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, const uint16_t *a, bus_size_t c)
|
|
{
|
|
|
|
for (; c; a++, c--, o += 2)
|
|
bus_space_write_stream_2(t, h, o, *a);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_region_stream_4(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, const uint32_t *a, bus_size_t c)
|
|
{
|
|
|
|
for (; c; a++, c--, o += 4)
|
|
bus_space_write_stream_4(t, h, o, *a);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_region_stream_8(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, const uint64_t *a, bus_size_t c)
|
|
{
|
|
|
|
for (; c; a++, c--, o += 8)
|
|
bus_space_write_stream_8(t, h, o, *a);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_region_stream_1(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, const uint8_t v, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o++)
|
|
bus_space_write_stream_1(t, h, o, v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_region_stream_2(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, const uint16_t v, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o += 2)
|
|
bus_space_write_stream_2(t, h, o, v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_region_stream_4(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, const uint32_t v, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o += 4)
|
|
bus_space_write_stream_4(t, h, o, v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_region_stream_8(bus_space_tag_t t, bus_space_handle_t h,
|
|
bus_size_t o, const uint64_t v, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o += 8)
|
|
bus_space_write_stream_8(t, h, o, v);
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_copy_region_stream_1(bus_space_tag_t t, bus_space_handle_t h1,
|
|
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o1++, o2++)
|
|
bus_space_write_stream_1(t, h1, o1, bus_space_read_stream_1(t, h2,
|
|
o2));
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_copy_region_stream_2(bus_space_tag_t t, bus_space_handle_t h1,
|
|
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o1 += 2, o2 += 2)
|
|
bus_space_write_stream_2(t, h1, o1, bus_space_read_stream_2(t, h2,
|
|
o2));
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_copy_region_stream_4(bus_space_tag_t t, bus_space_handle_t h1,
|
|
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o1 += 4, o2 += 4)
|
|
bus_space_write_stream_4(t, h1, o1, bus_space_read_stream_4(t, h2,
|
|
o2));
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_copy_region_stream_8(bus_space_tag_t t, bus_space_handle_t h1,
|
|
bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
|
|
{
|
|
|
|
for (; c; c--, o1 += 8, o2 += 8)
|
|
bus_space_write_stream_8(t, h1, o1, bus_space_read_8(t, h2, o2));
|
|
}
|
|
|
|
static __inline int
|
|
bus_space_peek_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
|
|
uint8_t *a)
|
|
{
|
|
|
|
__BUS_DEBUG_ACCESS(h, o, "peek", 1);
|
|
return (fasword8(bus_type_asi[t->bst_type], (caddr_t)(h + o), a));
|
|
}
|
|
|
|
static __inline int
|
|
bus_space_peek_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
|
|
uint16_t *a)
|
|
{
|
|
|
|
__BUS_DEBUG_ACCESS(h, o, "peek", 2);
|
|
return (fasword16(bus_type_asi[t->bst_type], (caddr_t)(h + o), a));
|
|
}
|
|
|
|
static __inline int
|
|
bus_space_peek_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
|
|
uint32_t *a)
|
|
{
|
|
|
|
__BUS_DEBUG_ACCESS(h, o, "peek", 4);
|
|
return (fasword32(bus_type_asi[t->bst_type], (caddr_t)(h + o), a));
|
|
}
|
|
|
|
#include <machine/bus_dma.h>
|
|
|
|
#endif /* !_MACHINE_BUS_H_ */
|