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baf7f63f9a
is temporary code to keep imx development moving forward for now. In the long run we need a SoC-independant clock management API.
259 lines
10 KiB
C
259 lines
10 KiB
C
/* $NetBSD: imx51_ccmreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
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/*
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* Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 2012, 2013 The FreeBSD Foundation
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* All rights reserved.
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*
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* Portions of this software were developed by Oleksandr Rybalko
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IMX51_CCMREG_H
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#define _IMX51_CCMREG_H
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#include <sys/cdefs.h>
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/* register offset address */
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#define CCMC_BASE 0x73fd4000
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#define CCMC_CCR 0x0000
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#define CCR_FPM_MULT 0x00001000
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#define CCMC_CCDR 0x0004
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#define CCMC_CSR 0x0008
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#define CCMC_CCSR 0x000c
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#define CCSR_LP_APM 0x00000200
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#define CCSR_STEP_SEL_SHIFT 7
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#define CCSR_STEP_SEL_MASK 0x00000180
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#define CCSR_PLL2_DIV_PODF_SHIFT 5
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#define CCSR_PLL2_DIV_PODF_MASK 0x00000060
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#define CCSR_PLL3_DIV_PODF_SHIFT 3
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#define CCSR_PLL3_DIV_PODF_MASK 0x00000030
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#define CCSR_PLL1_SW_CLK_SEL 0x00000004
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#define CCSR_PLL2_SW_CLK_SEL 0x00000002
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#define CCSR_PLL3_SW_CLK_SEL 0x00000001
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#define CCMC_CACRR 0x0010
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#define CCMC_CBCDR 0x0014
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#define CBCDR_DDR_HIGH_FREQ_CLK_SEL 0x40000000
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#define CBCDR_DDR_CLK_PODF_SHIFT 27
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#define CBCDR_DDR_CLK_PODF_MASK 0x38000000
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#define CBCDR_EMI_CLK_SEL 0x04000000
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#define CBCDR_PERIPH_CLK_SEL 0x02000000
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#define CBCDR_EMI_SLOW_PODF_SHIFT 22
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#define CBCDR_EMI_SLOW_PODF_MASK 0x01c00000
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#define CBCDR_AXI_B_PODF_SHIFT 19
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#define CBCDR_AXI_B_PODF_MASK 0x00380000
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#define CBCDR_AXI_A_PODF_SHIFT 16
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#define CBCDR_AXI_A_PODF_MASK 0x1fff0000
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#define CBCDR_NFC_PODF_SHIFT 13
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#define CBCDR_NFC_PODF_MASK 0x00018000
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#define CBCDR_AHB_PODF_SHIFT 10
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#define CBCDR_AHB_PODF_MASK 0x00001c00
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#define CBCDR_IPG_PODF_SHIFT 8
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#define CBCDR_IPG_PODF_MASK 0x00000300
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#define CBCDR_PERCLK_PRED1_SHIFT 6
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#define CBCDR_PERCLK_PRED1_MASK 0x000000c0
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#define CBCDR_PERCLK_PRED2_SHIFT 3
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#define CBCDR_PERCLK_PRED2_MASK 0x00000038
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#define CBCDR_PERCLK_PODF_SHIFT 0
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#define CBCDR_PERCLK_PODF_MASK 0x00000007
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#define CCMC_CBCMR 0x0018
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#define CBCMR_PERIPH_APM_SEL_SHIFT 12
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#define CBCMR_PERIPH_APM_SEL_MASK 0x00003000
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#define CBCMR_IPU_HSP_CLK_SEL_SHIFT 6
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#define CBCMR_IPU_HSP_CLK_SEL_MASK 0x000000c0
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#define CBCMR_PERCLK_LP_APM_SEL 0x00000002
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#define CBCMR_PERCLK_IPG_SEL 0x00000001
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#define CCMC_CSCMR1 0x001c
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#define CSCMR1_UART_CLK_SEL_SHIFT 24
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#define CSCMR1_UART_CLK_SEL_MASK 0x03000000
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#define CSCMR1_USBPHY_CLK_SEL_SHIFT 26
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#define CSCMR1_USBPHY_CLK_SEL_MASK 0x04000000
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#define CSCMR1_USBOH3_CLK_SEL_SHIFT 22
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#define CSCMR1_USBOH3_CLK_SEL_MASK 0x00c00000
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#define CCMC_CSCMR2 0x0020
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#define CCMC_CSCDR1 0x0024
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#define CSCDR1_UART_CLK_PRED_SHIFT 3
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#define CSCDR1_UART_CLK_PRED_MASK 0x00000038
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#define CSCDR1_UART_CLK_PODF_SHIFT 0
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#define CSCDR1_UART_CLK_PODF_MASK 0x00000007
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#define CSCDR1_USBOH3_CLK_PRED_SHIFT 8
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#define CSCDR1_USBOH3_CLK_PRED_MASK 0x00000700
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#define CSCDR1_USBOH3_CLK_PODF_SHIFT 6
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#define CSCDR1_USBOH3_CLK_PODF_MASK 0x000000c0
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#define CCMC_CS1CDR 0x0028
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#define CCMC_CS2CDR 0x002c
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#define CCMC_CDCDR 0x0030
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#define CCMC_CSCDR2 0x0038
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#define CCMC_CSCDR3 0x003c
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#define CCMC_CSCDR4 0x0040
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#define CCMC_CWDR 0x0044
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#define CCMC_CDHIPR 0x0048
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#define CCMC_CDCR 0x004c
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#define CDCR_PERIPH_CLK_DVFS_PODF_SHIFT 0
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#define CDCR_PERIPH_CLK_DVFS_PODF_MASK 0x00000003
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#define CCMC_CTOR 0x0050
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#define CCMC_CLPCR 0x0054
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#define CCMC_CISR 0x0058
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#define CCMC_CIMR 0x005c
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#define CCMC_CCOSR 0x0060
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#define CCMC_CGPR 0x0064
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#define CCMC_CCGR(n) (0x0068 + (n) * 4)
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#define CCMC_CMEOR 0x0084
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#define CCMC_SIZE 0x88
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/* CCGR Clock Gate Register */
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#define CCMR_CCGR_NSOURCE 16
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#define CCMR_CCGR_NGROUPS 7
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#define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE)
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#define __CCGR_NUM(a, b) ((a) * 16 + (b))
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#define CCGR_ARM_BUS_CLK __CCGR_NUM(0, 0)
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#define CCGR_ARM_AXI_CLK __CCGR_NUM(0, 1)
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#define CCGR_ARM_DEBUG_CLK __CCGR_NUM(0, 2)
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#define CCGR_TZIC_CLK __CCGR_NUM(0, 3)
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#define CCGR_DAP_CLK __CCGR_NUM(0, 4)
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#define CCGR_TPIU_CLK __CCGR_NUM(0, 5)
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#define CCGR_CTI2_CLK __CCGR_NUM(0, 6)
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#define CCGR_CTI3_CLK __CCGR_NUM(0, 7)
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#define CCGR_AHBMUX1_CLK __CCGR_NUM(0, 8)
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#define CCGR_AHBMUX2_CLK __CCGR_NUM(0, 9)
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#define CCGR_ROMCP_CLK __CCGR_NUM(0, 10)
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#define CCGR_ROM_CLK __CCGR_NUM(0, 11)
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#define CCGR_AIPS_TZ1_CLK __CCGR_NUM(0, 12)
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#define CCGR_AIPS_TZ2_CLK __CCGR_NUM(0, 13)
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#define CCGR_AHB_MAX_CLK __CCGR_NUM(0, 14)
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#define CCGR_IIM_CLK __CCGR_NUM(0, 15)
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#define CCGR_TMAX1_CLK __CCGR_NUM(1, 0)
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#define CCGR_TMAX2_CLK __CCGR_NUM(1, 1)
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#define CCGR_TMAX3_CLK __CCGR_NUM(1, 2)
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#define CCGR_UART1_CLK __CCGR_NUM(1, 3)
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#define CCGR_UART1_SERIAL_CLK __CCGR_NUM(1, 4)
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#define CCGR_UART2_CLK __CCGR_NUM(1, 5)
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#define CCGR_UART2_SERIAL_CLK __CCGR_NUM(1, 6)
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#define CCGR_UART3_CLK __CCGR_NUM(1, 7)
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#define CCGR_UART3_SERIAL_CLK __CCGR_NUM(1, 8)
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#define CCGR_I2C1_SERIAL_CLK __CCGR_NUM(1, 9)
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#define CCGR_I2C2_SERIAL_CLK __CCGR_NUM(1, 10)
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#define CCGR_HSI2C_CLK __CCGR_NUM(1, 11)
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#define CCGR_HSI2C_SERIAL_CLK __CCGR_NUM(1, 12)
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#define CCGR_FIRI_CLK __CCGR_NUM(1, 13)
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#define CCGR_FIRI_SERIAL_CLK __CCGR_NUM(1, 14)
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#define CCGR_SCC_CLK __CCGR_NUM(1, 15)
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#define CCGR_USB_PHY_CLK __CCGR_NUM(2, 0)
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#define CCGR_EPIT1_CLK __CCGR_NUM(2, 1)
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#define CCGR_EPIT1_SERIAL_CLK __CCGR_NUM(2, 2)
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#define CCGR_EPIT2_CLK __CCGR_NUM(2, 3)
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#define CCGR_EPIT2_SERIAL_CLK __CCGR_NUM(2, 4)
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#define CCGR_PWM1_CLK __CCGR_NUM(2, 5)
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#define CCGR_PWM1_SERIAL_CLK __CCGR_NUM(2, 6)
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#define CCGR_PWM2_CLK __CCGR_NUM(2, 7)
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#define CCGR_PWM2_SERIAL_CLK __CCGR_NUM(2, 8)
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#define CCGR_GPT_CLK __CCGR_NUM(2, 9)
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#define CCGR_GPT_SERIAL_CLK __CCGR_NUM(2, 10)
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#define CCGR_OWIRE_CLK __CCGR_NUM(2, 11)
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#define CCGR_FEC_CLK __CCGR_NUM(2, 12)
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#define CCGR_USBOH3_IPG_AHB_CLK __CCGR_NUM(2, 13)
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#define CCGR_USBOH3_60M_CLK __CCGR_NUM(2, 14)
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#define CCGR_TVE_CLK __CCGR_NUM(2, 15)
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#define CCGR_ESDHC1_CLK __CCGR_NUM(3, 0)
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#define CCGR_ESDHC1_SERIAL_CLK __CCGR_NUM(3, 1)
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#define CCGR_ESDHC2_CLK __CCGR_NUM(3, 2)
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#define CCGR_ESDHC2_SERIAL_CLK __CCGR_NUM(3, 3)
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#define CCGR_ESDHC3_CLK __CCGR_NUM(3, 4)
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#define CCGR_ESDHC3_SERIAL_CLK __CCGR_NUM(3, 5)
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#define CCGR_ESDHC4_CLK __CCGR_NUM(3, 6)
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#define CCGR_ESDHC4_SERIAL_CLK __CCGR_NUM(3, 7)
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#define CCGR_SSI1_CLK __CCGR_NUM(3, 8)
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#define CCGR_SSI1_SERIAL_CLK __CCGR_NUM(3, 9)
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#define CCGR_SSI2_CLK __CCGR_NUM(3, 10)
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#define CCGR_SSI2_SERIAL_CLK __CCGR_NUM(3, 11)
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#define CCGR_SSI3_CLK __CCGR_NUM(3, 12)
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#define CCGR_SSI3_SERIAL_CLK __CCGR_NUM(3, 13)
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#define CCGR_SSI_EXT1_CLK __CCGR_NUM(3, 14)
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#define CCGR_SSI_EXT2_CLK __CCGR_NUM(3, 15)
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#define CCGR_PATA_CLK __CCGR_NUM(4, 0)
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#define CCGR_SIM_CLK __CCGR_NUM(4, 1)
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#define CCGR_SIM_SERIAL_CLK __CCGR_NUM(4, 2)
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#define CCGR_SAHARA_CLK __CCGR_NUM(4, 3)
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#define CCGR_RTIC_CLK __CCGR_NUM(4, 4)
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#define CCGR_ECSPI1_CLK __CCGR_NUM(4, 5)
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#define CCGR_ECSPI1_SERIAL_CLK __CCGR_NUM(4, 6)
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#define CCGR_ECSPI2_CLK __CCGR_NUM(4, 7)
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#define CCGR_ECSPI2_SERIAL_CLK __CCGR_NUM(4, 8)
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#define CCGR_CSPI_CLK __CCGR_NUM(4, 9)
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#define CCGR_SRTC_CLK __CCGR_NUM(4, 10)
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#define CCGR_SDMA_CLK __CCGR_NUM(4, 11)
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#define CCGR_SPBA_CLK __CCGR_NUM(5, 0)
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#define CCGR_GPU_CLK __CCGR_NUM(5, 1)
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#define CCGR_GARB_CLK __CCGR_NUM(5, 2)
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#define CCGR_VPU_CLK __CCGR_NUM(5, 3)
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#define CCGR_VPU_SERIAL_CLK __CCGR_NUM(5, 4)
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#define CCGR_IPU_CLK __CCGR_NUM(5, 5)
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#define CCGR_EMI_GARB_CLK __CCGR_NUM(6, 0)
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#define CCGR_IPU_DI0_CLK __CCGR_NUM(6, 1)
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#define CCGR_IPU_DI1_CLK __CCGR_NUM(6, 2)
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#define CCGR_GPU2D_CLK __CCGR_NUM(6, 3)
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#define CCGR_SLIMBUS_CLK __CCGR_NUM(6, 4)
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#define CCGR_SLIMBUS_SERIAL_CLK __CCGR_NUM(6, 5)
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#define CCGR_CLK_MODE_OFF 0
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#define CCGR_CLK_MODE_RUNMODE 1
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#define CCGR_CLK_MODE_ALWAYS 3
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#endif /* _IMX51_CCMREG_H */
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