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213 lines
7.5 KiB
C
213 lines
7.5 KiB
C
/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
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* from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_IOMMUREG_H_
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#define _MACHINE_IOMMUREG_H_
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/*
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* UltraSPARC IOMMU registers, common to both the PCI and SBus
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* controllers.
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*/
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/* IOMMU registers */
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#define IMR_CTL 0x0000 /* IOMMU control register */
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#define IMR_TSB 0x0008 /* IOMMU TSB base register */
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#define IMR_FLUSH 0x0010 /* IOMMU flush register */
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/* The TTE Cache is Fire and Oberon only. */
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#define IMR_CACHE_FLUSH 0x0100 /* IOMMU TTE cache flush address register */
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#define IMR_CACHE_INVAL 0x0108 /* IOMMU TTE cache invalidate register */
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/* streaming buffer registers */
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#define ISR_CTL 0x0000 /* streaming buffer control reg */
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#define ISR_PGFLUSH 0x0008 /* streaming buffer page flush */
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#define ISR_FLUSHSYNC 0x0010 /* streaming buffer flush sync */
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/* streaming buffer diagnostics registers */
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#define ISD_DATA_DIAG 0x0000 /* streaming buffer data RAM diag 0..127 */
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#define ISD_ERROR_DIAG 0x0400 /* streaming buffer error status diag 0..127 */
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#define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */
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#define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */
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/* streaming buffer control register */
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#define STRBUF_EN 0x0000000000000001UL
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#define STRBUF_D 0x0000000000000002UL
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#define STRBUF_RR_DIS 0x0000000000000004UL
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#define IOMMU_MAXADDR(bits) ((1UL << (bits)) - 1)
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/*
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* control register bits
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*/
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/* Nummber of entries in the IOTSB - pre-Fire only */
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#define IOMMUCR_TSBSZ_MASK 0x0000000000070000UL
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#define IOMMUCR_TSBSZ_SHIFT 16
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/* TSB cache snoop enable */
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#define IOMMUCR_SE 0x0000000000000400UL
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/* Cache modes - Fire and Oberon */
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#define IOMMUCR_CM_NC_TLB_TBW 0x0000000000000000UL
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#define IOMMUCR_CM_LC_NTLB_NTBW 0x0000000000000100UL
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#define IOMMUCR_CM_LC_TLB_TBW 0x0000000000000200UL
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#define IOMMUCR_CM_C_TLB_TBW 0x0000000000000300UL
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/* IOMMU page size - pre-Fire only */
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#define IOMMUCR_8KPG 0x0000000000000000UL
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#define IOMMUCR_64KPG 0x0000000000000004UL
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/* Bypass enable - Fire and Oberon */
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#define IOMMUCR_BE 0x0000000000000002UL
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/* Diagnostic mode enable - pre-Fire only */
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#define IOMMUCR_DE 0x0000000000000002UL
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/* IOMMU/translation enable */
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#define IOMMUCR_EN 0x0000000000000001UL
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/*
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* TSB base register bits
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*/
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/* TSB base address */
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#define IOMMUTB_TB_MASK 0x000007ffffffe000UL
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#define IOMMUTB_TB_SHIFT 13
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/* IOMMU page size - Fire and Oberon */
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#define IOMMUTB_8KPG 0x0000000000000000UL
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#define IOMMUTB_64KPG 0x0000000000000100UL
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/* Nummber of entries in the IOTSB - Fire and Oberon */
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#define IOMMUTB_TSBSZ_MASK 0x0000000000000004UL
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#define IOMMUTB_TSBSZ_SHIFT 0
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/*
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* TSB size definitions for both control and TSB base register */
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#define IOMMU_TSB1K 0
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#define IOMMU_TSB2K 1
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#define IOMMU_TSB4K 2
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#define IOMMU_TSB8K 3
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#define IOMMU_TSB16K 4
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#define IOMMU_TSB32K 5
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#define IOMMU_TSB64K 6
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#define IOMMU_TSB128K 7
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/* Fire and Oberon */
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#define IOMMU_TSB256K 8
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/* Fire and Oberon */
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#define IOMMU_TSB512K 9
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#define IOMMU_TSBENTRIES(tsbsz) \
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((1 << (tsbsz)) << (IO_PAGE_SHIFT - IOTTE_SHIFT))
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/*
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* Diagnostic register definitions
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*/
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#define IOMMU_DTAG_VPNBITS 19
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#define IOMMU_DTAG_VPNMASK ((1 << IOMMU_DTAG_VPNBITS) - 1)
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#define IOMMU_DTAG_VPNSHIFT 13
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#define IOMMU_DTAG_ERRBITS 3
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#define IOMMU_DTAG_ERRSHIFT 22
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#define IOMMU_DTAG_ERRMASK \
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(((1 << IOMMU_DTAG_ERRBITS) - 1) << IOMMU_DTAG_ERRSHIFT)
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#define IOMMU_DDATA_PGBITS 21
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#define IOMMU_DDATA_PGMASK ((1 << IOMMU_DDATA_PGBITS) - 1)
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#define IOMMU_DDATA_PGSHIFT 13
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#define IOMMU_DDATA_C (1 << 28)
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#define IOMMU_DDATA_V (1 << 30)
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/*
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* IOMMU stuff
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*/
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/* Entry valid */
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#define IOTTE_V 0x8000000000000000UL
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/* Page size - pre-Fire only */
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#define IOTTE_64K 0x2000000000000000UL
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#define IOTTE_8K 0x0000000000000000UL
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/* Streamable page - streaming buffer equipped variants only */
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#define IOTTE_STREAM 0x1000000000000000UL
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/* Accesses to the same bus segment - SBus only */
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#define IOTTE_LOCAL 0x0800000000000000UL
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/* Physical address mask (based on Oberon) */
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#define IOTTE_PAMASK 0x00007fffffffe000UL
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/* Accesses to cacheable space - pre-Fire only */
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#define IOTTE_C 0x0000000000000010UL
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/* Writeable */
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#define IOTTE_W 0x0000000000000002UL
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/* log2 of the IOMMU TTE size */
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#define IOTTE_SHIFT 3
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/* Streaming buffer line size */
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#define STRBUF_LINESZ 64
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/*
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* Number of bytes written by a stream buffer flushsync operation to indicate
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* completion.
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*/
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#define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ
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/*
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* On sun4u each bus controller has a separate IOMMU. The IOMMU has
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* a TSB which must be page aligned and physically contiguous. Mappings
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* can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility
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* with the CPU's MMU.
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*
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* On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the
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* following size segments:
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*
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* VA size VA base TSB size tsbsize
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* -------- -------- --------- -------
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* 8MB ff800000 8K 0
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* 16MB ff000000 16K 1
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* 32MB fe000000 32K 2
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* 64MB fc000000 64K 3
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* 128MB f8000000 128K 4
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* 256MB f0000000 256K 5
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* 512MB e0000000 512K 6
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* 1GB c0000000 1MB 7
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*
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* Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use
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* this scheme to determine the IOVA base address. Instead, bits 31-29 are
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* used to check against the Target Address Space register in the IIi and
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* the IOMMU is used if they hit. God knows what goes on in the IIe.
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*
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*/
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#define IOTSB_BASESZ (1024 << IOTTE_SHIFT)
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#define IOTSB_VEND (~IO_PAGE_MASK)
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#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10))
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#define MAKEIOTTE(pa, w, c, s) \
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(((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \
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((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \
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(IOTTE_V | IOTTE_8K))
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#define IOTSBSLOT(va) \
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((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT)
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#endif /* !_MACHINE_IOMMUREG_H_ */
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