Marcel Moolenaar 2fa9a15eca Further enhance the handling of misaligned loads and stores: ... o implement double-extended and single precision loads and stores, o implement double precision stores, o replace the machdep.unaligned_print sysctl with debug.unaligned_print and change the default value to 0, o replace the machdep.unaligned_sigbus sysctl with debug.unaligned_test, o Remmove the fillfd() function. The function is trvial enough for inline assembly. The debug.unaligned_test sysctl is used to test the emulation of misaligned loads and stores. When PSR.ac is 0, the CPU will handle misaligned memory accesses itselfi and we don't get an exception for it. When PSR.ac is 1, the process needs to be signalled and we should not emulate. The sysctl takes effect when PSR.ac is 1 and tells us that we should emulate and not send a signal. PR: 72268 MFC after: 1 week		2005-01-02 00:20:54 +00:00
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acpica	Move the code for halting the CPU (acpi_cpu_c1) into machdep files.	2004-10-11 05:39:15 +00:00
compile
conf	Remove the BR tag. When the machine doesn't have the DIG64 HCDP	2004-11-14 23:42:48 +00:00
disasm	ITC.{i,d} instructions use format M41 not M42.	2004-08-16 18:41:24 +00:00
ia32	...And fix WITNESS builds: declare syscallnames.	2004-09-26 20:39:56 +00:00
ia64	Further enhance the handling of misaligned loads and stores:	2005-01-02 00:20:54 +00:00
include	Further enhance the handling of misaligned loads and stores:	2005-01-02 00:20:54 +00:00
isa	Add new a function isa_dma_init() which returns an errno when it fails	2004-09-15 12:09:50 +00:00
pci	Delete legacy pcib code - we can't possibly work without acpi on ia64.	2001-10-06 10:09:57 +00:00