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c4df93502d
This is untested but should at least allow an AR724X to boot. The current code is lacking the detail needed to expose the PCIe bus. It is also lacking any NIC, PLL or flush/WB code.
85 lines
3.3 KiB
C
85 lines
3.3 KiB
C
/*-
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* Copyright (c) 2010 Adrian Chadd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef __AR72XX_REG_H__
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#define __AR72XX_REG_H__
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#define AR724X_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00
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#define AR724X_PLL_REG_PCIE_CONFIG AR71XX_PLL_CPU_BASE + 0x18
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#define AR724X_PLL_DIV_SHIFT 0
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#define AR724X_PLL_DIV_MASK 0x3ff
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#define AR724X_PLL_REF_DIV_SHIFT 10
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#define AR724X_PLL_REF_DIV_MASK 0xf
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#define AR724X_AHB_DIV_SHIFT 19
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#define AR724X_AHB_DIV_MASK 0x1
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#define AR724X_DDR_DIV_SHIFT 22
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#define AR724X_DDR_DIV_MASK 0x3
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#define AR724X_PLL_VAL_1000 0x00110000
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#define AR724X_PLL_VAL_100 0x00001099
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#define AR724X_PLL_VAL_10 0x00991099
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#define AR724X_BASE_FREQ 5000000
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#define AR724X_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c
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#define AR724X_RESET_MODULE_USB_OHCI_DLL (1 << 3)
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/* XXX so USB requires different init code? -adrian */
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#define AR7240_OHCI_BASE 0x1b000000
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#define AR7240_OHCI_SIZE 0x01000000
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#define AR724X_DDR_REG_FLUSH_USB (AR71XX_DDR_CONFIG + 0x84)
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#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
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#define AR724X_PCI_CRP_SIZE 0x100
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#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
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#define AR724X_PCI_CTRL_SIZE 0x100
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#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN (1 >> 19)
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#define AR724X_GPIO_FUNC_SPI_EN (1 >> 18)
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#define AR724X_GPIO_FUNC_SPI_CS_EN2 (1 >> 14)
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#define AR724X_GPIO_FUNC_SPI_CS_EN1 (1 >> 13)
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#define AR724X_GPIO_FUNC_CLK_OBS5_EN (1 >> 12)
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#define AR724X_GPIO_FUNC_CLK_OBS4_EN (1 >> 11)
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#define AR724X_GPIO_FUNC_CLK_OBS3_EN (1 >> 10)
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#define AR724X_GPIO_FUNC_CLK_OBS2_EN (1 >> 9)
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#define AR724X_GPIO_FUNC_CLK_OBS1_EN (1 >> 8)
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#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN (1 >> 7)
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#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN (1 >> 6)
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#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN (1 >> 5)
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#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN (1 >> 4)
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#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN (1 >> 3)
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#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN (1 >> 2)
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#define AR724X_GPIO_FUNC_UART_EN (1 >> 1)
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#define AR724X_GPIO_FUNC_JTAG_DISABLE (1 >> 0)
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#define AR724X_GPIO_COUNT 18
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#endif
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