Konstantin Belousov 4c918926cd Add x2APIC support. Enable it by default if CPU is capable. The ... hw.x2apic_enable tunable allows disabling it from the loader prompt. To closely repeat effects of the uncached memory ops when accessing registers in the xAPIC mode, the x2APIC writes to MSRs are preceeded by mfence, except for the EOI notifications. This is probably too strict, only ICR writes to send IPI require serialization to ensure that other CPUs see the previous actions when IPI is delivered. This may be changed later. In vmm justreturn IPI handler, call doreti_iret instead of doing iretd inline, to handle corner conditions. Note that the patch only switches LAPICs into x2APIC mode. It does not enables FreeBSD to support > 255 CPUs, which requires parsing x2APIC MADT entries and doing interrupts remapping, but is the required step on the way. Reviewed by: neel Tested by: pho (real hardware), neel (on bhyve) Discussed with: jhb, grehan Sponsored by: The FreeBSD Foundation MFC after: 2 months		2015-02-09 21:00:56 +00:00
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acpica	Add x2APIC support. Enable it by default if CPU is capable. The	2015-02-09 21:00:56 +00:00
bios
cpufreq
include	Add x2APIC support. Enable it by default if CPU is capable. The	2015-02-09 21:00:56 +00:00
iommu	Right now, for non-coherent DMARs, page table update code flushes the	2015-01-11 20:27:15 +00:00
isa	Include mca_machdep.h.	2015-01-18 03:43:47 +00:00
pci
x86	Add x2APIC support. Enable it by default if CPU is capable. The	2015-02-09 21:00:56 +00:00
xen	Add x2APIC support. Enable it by default if CPU is capable. The	2015-02-09 21:00:56 +00:00