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b18f8431a0
instruction set. Thumb-2 requires an if-then instruction to implement conditional codes. When building for ARM mode the it-then instructions do not generate any assembled instruction as per the ARMv7-A Architecture Reference Manual, and are safe to use. While this allows the atomic instructions to be built, it doesn't mean we fully support Thumb code. It works in small tests, but is still known to fail in a large number of places. While here add a check for the armv6t2 architecture.
818 lines
20 KiB
C
818 lines
20 KiB
C
/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
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/*-
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* Copyright (C) 2003-2004 Olivier Houchard
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* Copyright (C) 1994-1997 Mark Brinicombe
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* Copyright (C) 1994 Brini
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of Brini may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ATOMIC_H_
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#define _MACHINE_ATOMIC_H_
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#include <sys/types.h>
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#ifndef _KERNEL
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#include <machine/sysarch.h>
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#else
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#include <machine/cpuconf.h>
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#endif
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#if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__)
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#define isb() __asm __volatile("isb" : : : "memory")
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#define dsb() __asm __volatile("dsb" : : : "memory")
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#define dmb() __asm __volatile("dmb" : : : "memory")
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#elif defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) || \
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defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6T2__) || \
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defined (__ARM_ARCH_6Z__) || defined (__ARM_ARCH_6ZK__)
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#define isb() __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory")
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#define dsb() __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory")
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#define dmb() __asm __volatile("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory")
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#else
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#define isb()
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#define dsb()
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#define dmb()
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#endif
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#define mb() dmb()
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#define wmb() dmb()
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#define rmb() dmb()
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#ifndef I32_bit
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#define I32_bit (1 << 7) /* IRQ disable */
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#endif
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#ifndef F32_bit
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#define F32_bit (1 << 6) /* FIQ disable */
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#endif
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/*
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* It would be nice to use _HAVE_ARMv6_INSTRUCTIONS from machine/asm.h
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* here, but that header can't be included here because this is C
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* code. I would like to move the _HAVE_ARMv6_INSTRUCTIONS definition
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* out of asm.h so it can be used in both asm and C code. - kientzle@
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*/
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#if defined (__ARM_ARCH_7__) || \
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defined (__ARM_ARCH_7A__) || \
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defined (__ARM_ARCH_6__) || \
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defined (__ARM_ARCH_6J__) || \
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defined (__ARM_ARCH_6K__) || \
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defined (__ARM_ARCH_6T2__) || \
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defined (__ARM_ARCH_6Z__) || \
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defined (__ARM_ARCH_6ZK__)
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static __inline void
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__do_dmb(void)
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{
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#if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__)
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__asm __volatile("dmb" : : : "memory");
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#else
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__asm __volatile("mcr p15, 0, r0, c7, c10, 5" : : : "memory");
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#endif
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}
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#define ATOMIC_ACQ_REL_LONG(NAME) \
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static __inline void \
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atomic_##NAME##_acq_long(__volatile u_long *p, u_long v) \
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{ \
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atomic_##NAME##_long(p, v); \
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__do_dmb(); \
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} \
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\
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static __inline void \
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atomic_##NAME##_rel_long(__volatile u_long *p, u_long v) \
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{ \
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__do_dmb(); \
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atomic_##NAME##_long(p, v); \
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}
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#define ATOMIC_ACQ_REL(NAME, WIDTH) \
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static __inline void \
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atomic_##NAME##_acq_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
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{ \
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atomic_##NAME##_##WIDTH(p, v); \
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__do_dmb(); \
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} \
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\
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static __inline void \
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atomic_##NAME##_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
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{ \
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__do_dmb(); \
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atomic_##NAME##_##WIDTH(p, v); \
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}
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static __inline void
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atomic_set_32(volatile uint32_t *address, uint32_t setmask)
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{
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uint32_t tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%2]\n"
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"orr %0, %0, %3\n"
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"strex %1, %0, [%2]\n"
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"cmp %1, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=&r" (tmp), "+r" (tmp2)
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, "+r" (address), "+r" (setmask) : : "cc", "memory");
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}
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static __inline void
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atomic_set_long(volatile u_long *address, u_long setmask)
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{
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u_long tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%2]\n"
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"orr %0, %0, %3\n"
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"strex %1, %0, [%2]\n"
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"cmp %1, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=&r" (tmp), "+r" (tmp2)
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, "+r" (address), "+r" (setmask) : : "cc", "memory");
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}
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static __inline void
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atomic_clear_32(volatile uint32_t *address, uint32_t setmask)
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{
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uint32_t tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%2]\n"
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"bic %0, %0, %3\n"
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"strex %1, %0, [%2]\n"
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"cmp %1, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=&r" (tmp), "+r" (tmp2)
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,"+r" (address), "+r" (setmask) : : "cc", "memory");
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}
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static __inline void
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atomic_clear_long(volatile u_long *address, u_long setmask)
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{
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u_long tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%2]\n"
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"bic %0, %0, %3\n"
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"strex %1, %0, [%2]\n"
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"cmp %1, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=&r" (tmp), "+r" (tmp2)
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,"+r" (address), "+r" (setmask) : : "cc", "memory");
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}
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static __inline u_int32_t
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atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
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{
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uint32_t ret;
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__asm __volatile("1: ldrex %0, [%1]\n"
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"cmp %0, %2\n"
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"it ne\n"
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"movne %0, #0\n"
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"bne 2f\n"
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"strex %0, %3, [%1]\n"
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"cmp %0, #0\n"
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"ite eq\n"
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"moveq %0, #1\n"
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"bne 1b\n"
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"2:"
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: "=&r" (ret)
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,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc",
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"memory");
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return (ret);
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}
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static __inline u_long
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atomic_cmpset_long(volatile u_long *p, volatile u_long cmpval, volatile u_long newval)
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{
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u_long ret;
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__asm __volatile("1: ldrex %0, [%1]\n"
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"cmp %0, %2\n"
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"itt ne\n"
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"movne %0, #0\n"
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"bne 2f\n"
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"strex %0, %3, [%1]\n"
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"cmp %0, #0\n"
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"ite eq\n"
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"moveq %0, #1\n"
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"bne 1b\n"
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"2:"
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: "=&r" (ret)
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,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc",
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"memory");
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return (ret);
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}
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static __inline u_int32_t
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atomic_cmpset_acq_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
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{
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u_int32_t ret = atomic_cmpset_32(p, cmpval, newval);
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__do_dmb();
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return (ret);
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}
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static __inline u_long
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atomic_cmpset_acq_long(volatile u_long *p, volatile u_long cmpval, volatile u_long newval)
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{
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u_long ret = atomic_cmpset_long(p, cmpval, newval);
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__do_dmb();
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return (ret);
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}
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static __inline u_int32_t
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atomic_cmpset_rel_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
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{
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__do_dmb();
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return (atomic_cmpset_32(p, cmpval, newval));
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}
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static __inline u_long
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atomic_cmpset_rel_long(volatile u_long *p, volatile u_long cmpval, volatile u_long newval)
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{
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__do_dmb();
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return (atomic_cmpset_long(p, cmpval, newval));
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}
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static __inline void
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atomic_add_32(volatile u_int32_t *p, u_int32_t val)
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{
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uint32_t tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%2]\n"
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"add %0, %0, %3\n"
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"strex %1, %0, [%2]\n"
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"cmp %1, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=&r" (tmp), "+r" (tmp2)
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,"+r" (p), "+r" (val) : : "cc", "memory");
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}
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static __inline void
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atomic_add_long(volatile u_long *p, u_long val)
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{
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u_long tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%2]\n"
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"add %0, %0, %3\n"
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"strex %1, %0, [%2]\n"
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"cmp %1, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=&r" (tmp), "+r" (tmp2)
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,"+r" (p), "+r" (val) : : "cc", "memory");
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}
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static __inline void
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atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
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{
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uint32_t tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%2]\n"
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"sub %0, %0, %3\n"
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"strex %1, %0, [%2]\n"
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"cmp %1, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=&r" (tmp), "+r" (tmp2)
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,"+r" (p), "+r" (val) : : "cc", "memory");
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}
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static __inline void
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atomic_subtract_long(volatile u_long *p, u_long val)
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{
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u_long tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%2]\n"
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"sub %0, %0, %3\n"
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"strex %1, %0, [%2]\n"
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"cmp %1, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=&r" (tmp), "+r" (tmp2)
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,"+r" (p), "+r" (val) : : "cc", "memory");
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}
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ATOMIC_ACQ_REL(clear, 32)
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ATOMIC_ACQ_REL(add, 32)
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ATOMIC_ACQ_REL(subtract, 32)
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ATOMIC_ACQ_REL(set, 32)
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ATOMIC_ACQ_REL_LONG(clear)
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ATOMIC_ACQ_REL_LONG(add)
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ATOMIC_ACQ_REL_LONG(subtract)
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ATOMIC_ACQ_REL_LONG(set)
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#undef ATOMIC_ACQ_REL
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#undef ATOMIC_ACQ_REL_LONG
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static __inline uint32_t
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atomic_fetchadd_32(volatile uint32_t *p, uint32_t val)
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{
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uint32_t tmp = 0, tmp2 = 0, ret = 0;
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__asm __volatile("1: ldrex %0, [%3]\n"
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"add %1, %0, %4\n"
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"strex %2, %1, [%3]\n"
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"cmp %2, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "+r" (ret), "=&r" (tmp), "+r" (tmp2)
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,"+r" (p), "+r" (val) : : "cc", "memory");
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return (ret);
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}
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static __inline uint32_t
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atomic_readandclear_32(volatile u_int32_t *p)
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{
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uint32_t ret, tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%3]\n"
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"mov %1, #0\n"
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"strex %2, %1, [%3]\n"
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"cmp %2, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=r" (ret), "=&r" (tmp), "+r" (tmp2)
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,"+r" (p) : : "cc", "memory");
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return (ret);
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}
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static __inline uint32_t
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atomic_load_acq_32(volatile uint32_t *p)
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{
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uint32_t v;
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v = *p;
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__do_dmb();
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return (v);
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}
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static __inline void
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atomic_store_rel_32(volatile uint32_t *p, uint32_t v)
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{
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__do_dmb();
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*p = v;
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}
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static __inline u_long
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atomic_fetchadd_long(volatile u_long *p, u_long val)
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{
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u_long tmp = 0, tmp2 = 0, ret = 0;
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__asm __volatile("1: ldrex %0, [%3]\n"
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"add %1, %0, %4\n"
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"strex %2, %1, [%3]\n"
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"cmp %2, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "+r" (ret), "=&r" (tmp), "+r" (tmp2)
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,"+r" (p), "+r" (val) : : "cc", "memory");
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return (ret);
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}
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static __inline u_long
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atomic_readandclear_long(volatile u_long *p)
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{
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u_long ret, tmp = 0, tmp2 = 0;
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__asm __volatile("1: ldrex %0, [%3]\n"
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"mov %1, #0\n"
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"strex %2, %1, [%3]\n"
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"cmp %2, #0\n"
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"it ne\n"
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"bne 1b\n"
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: "=r" (ret), "=&r" (tmp), "+r" (tmp2)
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,"+r" (p) : : "cc", "memory");
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return (ret);
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}
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static __inline u_long
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atomic_load_acq_long(volatile u_long *p)
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{
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u_long v;
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v = *p;
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__do_dmb();
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return (v);
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}
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static __inline void
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atomic_store_rel_long(volatile u_long *p, u_long v)
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{
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__do_dmb();
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*p = v;
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}
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#else /* < armv6 */
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#define __with_interrupts_disabled(expr) \
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do { \
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u_int cpsr_save, tmp; \
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\
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__asm __volatile( \
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"mrs %0, cpsr;" \
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"orr %1, %0, %2;" \
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"msr cpsr_all, %1;" \
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: "=r" (cpsr_save), "=r" (tmp) \
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: "I" (I32_bit | F32_bit) \
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: "cc" ); \
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(expr); \
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__asm __volatile( \
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"msr cpsr_all, %0" \
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: /* no output */ \
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: "r" (cpsr_save) \
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: "cc" ); \
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} while(0)
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static __inline uint32_t
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__swp(uint32_t val, volatile uint32_t *ptr)
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{
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__asm __volatile("swp %0, %2, [%3]"
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: "=&r" (val), "=m" (*ptr)
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: "r" (val), "r" (ptr), "m" (*ptr)
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: "memory");
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return (val);
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|
}
|
|
|
|
|
|
#ifdef _KERNEL
|
|
static __inline void
|
|
atomic_set_32(volatile uint32_t *address, uint32_t setmask)
|
|
{
|
|
__with_interrupts_disabled(*address |= setmask);
|
|
}
|
|
|
|
static __inline void
|
|
atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
|
|
{
|
|
__with_interrupts_disabled(*address &= ~clearmask);
|
|
}
|
|
|
|
static __inline u_int32_t
|
|
atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
|
|
{
|
|
int ret;
|
|
|
|
__with_interrupts_disabled(
|
|
{
|
|
if (*p == cmpval) {
|
|
*p = newval;
|
|
ret = 1;
|
|
} else {
|
|
ret = 0;
|
|
}
|
|
});
|
|
return (ret);
|
|
}
|
|
|
|
static __inline void
|
|
atomic_add_32(volatile u_int32_t *p, u_int32_t val)
|
|
{
|
|
__with_interrupts_disabled(*p += val);
|
|
}
|
|
|
|
static __inline void
|
|
atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
|
|
{
|
|
__with_interrupts_disabled(*p -= val);
|
|
}
|
|
|
|
static __inline uint32_t
|
|
atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
|
|
{
|
|
uint32_t value;
|
|
|
|
__with_interrupts_disabled(
|
|
{
|
|
value = *p;
|
|
*p += v;
|
|
});
|
|
return (value);
|
|
}
|
|
|
|
#else /* !_KERNEL */
|
|
|
|
static __inline u_int32_t
|
|
atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
|
|
{
|
|
register int done, ras_start = ARM_RAS_START;
|
|
|
|
__asm __volatile("1:\n"
|
|
"adr %1, 1b\n"
|
|
"str %1, [%0]\n"
|
|
"adr %1, 2f\n"
|
|
"str %1, [%0, #4]\n"
|
|
"ldr %1, [%2]\n"
|
|
"cmp %1, %3\n"
|
|
"streq %4, [%2]\n"
|
|
"2:\n"
|
|
"mov %1, #0\n"
|
|
"str %1, [%0]\n"
|
|
"mov %1, #0xffffffff\n"
|
|
"str %1, [%0, #4]\n"
|
|
"moveq %1, #1\n"
|
|
"movne %1, #0\n"
|
|
: "+r" (ras_start), "=r" (done)
|
|
,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc", "memory");
|
|
return (done);
|
|
}
|
|
|
|
static __inline void
|
|
atomic_add_32(volatile u_int32_t *p, u_int32_t val)
|
|
{
|
|
int start, ras_start = ARM_RAS_START;
|
|
|
|
__asm __volatile("1:\n"
|
|
"adr %1, 1b\n"
|
|
"str %1, [%0]\n"
|
|
"adr %1, 2f\n"
|
|
"str %1, [%0, #4]\n"
|
|
"ldr %1, [%2]\n"
|
|
"add %1, %1, %3\n"
|
|
"str %1, [%2]\n"
|
|
"2:\n"
|
|
"mov %1, #0\n"
|
|
"str %1, [%0]\n"
|
|
"mov %1, #0xffffffff\n"
|
|
"str %1, [%0, #4]\n"
|
|
: "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
|
|
: : "memory");
|
|
}
|
|
|
|
static __inline void
|
|
atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
|
|
{
|
|
int start, ras_start = ARM_RAS_START;
|
|
|
|
__asm __volatile("1:\n"
|
|
"adr %1, 1b\n"
|
|
"str %1, [%0]\n"
|
|
"adr %1, 2f\n"
|
|
"str %1, [%0, #4]\n"
|
|
"ldr %1, [%2]\n"
|
|
"sub %1, %1, %3\n"
|
|
"str %1, [%2]\n"
|
|
"2:\n"
|
|
"mov %1, #0\n"
|
|
"str %1, [%0]\n"
|
|
"mov %1, #0xffffffff\n"
|
|
"str %1, [%0, #4]\n"
|
|
|
|
: "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
|
|
: : "memory");
|
|
}
|
|
|
|
static __inline void
|
|
atomic_set_32(volatile uint32_t *address, uint32_t setmask)
|
|
{
|
|
int start, ras_start = ARM_RAS_START;
|
|
|
|
__asm __volatile("1:\n"
|
|
"adr %1, 1b\n"
|
|
"str %1, [%0]\n"
|
|
"adr %1, 2f\n"
|
|
"str %1, [%0, #4]\n"
|
|
"ldr %1, [%2]\n"
|
|
"orr %1, %1, %3\n"
|
|
"str %1, [%2]\n"
|
|
"2:\n"
|
|
"mov %1, #0\n"
|
|
"str %1, [%0]\n"
|
|
"mov %1, #0xffffffff\n"
|
|
"str %1, [%0, #4]\n"
|
|
|
|
: "+r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask)
|
|
: : "memory");
|
|
}
|
|
|
|
static __inline void
|
|
atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
|
|
{
|
|
int start, ras_start = ARM_RAS_START;
|
|
|
|
__asm __volatile("1:\n"
|
|
"adr %1, 1b\n"
|
|
"str %1, [%0]\n"
|
|
"adr %1, 2f\n"
|
|
"str %1, [%0, #4]\n"
|
|
"ldr %1, [%2]\n"
|
|
"bic %1, %1, %3\n"
|
|
"str %1, [%2]\n"
|
|
"2:\n"
|
|
"mov %1, #0\n"
|
|
"str %1, [%0]\n"
|
|
"mov %1, #0xffffffff\n"
|
|
"str %1, [%0, #4]\n"
|
|
: "+r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask)
|
|
: : "memory");
|
|
|
|
}
|
|
|
|
static __inline uint32_t
|
|
atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
|
|
{
|
|
uint32_t start, tmp, ras_start = ARM_RAS_START;
|
|
|
|
__asm __volatile("1:\n"
|
|
"adr %1, 1b\n"
|
|
"str %1, [%0]\n"
|
|
"adr %1, 2f\n"
|
|
"str %1, [%0, #4]\n"
|
|
"ldr %1, [%3]\n"
|
|
"mov %2, %1\n"
|
|
"add %2, %2, %4\n"
|
|
"str %2, [%3]\n"
|
|
"2:\n"
|
|
"mov %2, #0\n"
|
|
"str %2, [%0]\n"
|
|
"mov %2, #0xffffffff\n"
|
|
"str %2, [%0, #4]\n"
|
|
: "+r" (ras_start), "=r" (start), "=r" (tmp), "+r" (p), "+r" (v)
|
|
: : "memory");
|
|
return (start);
|
|
}
|
|
|
|
#endif /* _KERNEL */
|
|
|
|
|
|
static __inline uint32_t
|
|
atomic_readandclear_32(volatile u_int32_t *p)
|
|
{
|
|
|
|
return (__swp(0, p));
|
|
}
|
|
|
|
#define atomic_cmpset_rel_32 atomic_cmpset_32
|
|
#define atomic_cmpset_acq_32 atomic_cmpset_32
|
|
#define atomic_set_rel_32 atomic_set_32
|
|
#define atomic_set_acq_32 atomic_set_32
|
|
#define atomic_clear_rel_32 atomic_clear_32
|
|
#define atomic_clear_acq_32 atomic_clear_32
|
|
#define atomic_add_rel_32 atomic_add_32
|
|
#define atomic_add_acq_32 atomic_add_32
|
|
#define atomic_subtract_rel_32 atomic_subtract_32
|
|
#define atomic_subtract_acq_32 atomic_subtract_32
|
|
#define atomic_store_rel_32 atomic_store_32
|
|
#define atomic_store_rel_long atomic_store_long
|
|
#define atomic_load_acq_32 atomic_load_32
|
|
#define atomic_load_acq_long atomic_load_long
|
|
#define atomic_add_acq_long atomic_add_long
|
|
#define atomic_add_rel_long atomic_add_long
|
|
#define atomic_subtract_acq_long atomic_subtract_long
|
|
#define atomic_subtract_rel_long atomic_subtract_long
|
|
#define atomic_clear_acq_long atomic_clear_long
|
|
#define atomic_clear_rel_long atomic_clear_long
|
|
#define atomic_set_acq_long atomic_set_long
|
|
#define atomic_set_rel_long atomic_set_long
|
|
#define atomic_cmpset_acq_long atomic_cmpset_long
|
|
#define atomic_cmpset_rel_long atomic_cmpset_long
|
|
#define atomic_load_acq_long atomic_load_long
|
|
#undef __with_interrupts_disabled
|
|
|
|
static __inline void
|
|
atomic_add_long(volatile u_long *p, u_long v)
|
|
{
|
|
|
|
atomic_add_32((volatile uint32_t *)p, v);
|
|
}
|
|
|
|
static __inline void
|
|
atomic_clear_long(volatile u_long *p, u_long v)
|
|
{
|
|
|
|
atomic_clear_32((volatile uint32_t *)p, v);
|
|
}
|
|
|
|
static __inline int
|
|
atomic_cmpset_long(volatile u_long *dst, u_long old, u_long newe)
|
|
{
|
|
|
|
return (atomic_cmpset_32((volatile uint32_t *)dst, old, newe));
|
|
}
|
|
|
|
static __inline u_long
|
|
atomic_fetchadd_long(volatile u_long *p, u_long v)
|
|
{
|
|
|
|
return (atomic_fetchadd_32((volatile uint32_t *)p, v));
|
|
}
|
|
|
|
static __inline void
|
|
atomic_readandclear_long(volatile u_long *p)
|
|
{
|
|
|
|
atomic_readandclear_32((volatile uint32_t *)p);
|
|
}
|
|
|
|
static __inline void
|
|
atomic_set_long(volatile u_long *p, u_long v)
|
|
{
|
|
|
|
atomic_set_32((volatile uint32_t *)p, v);
|
|
}
|
|
|
|
static __inline void
|
|
atomic_subtract_long(volatile u_long *p, u_long v)
|
|
{
|
|
|
|
atomic_subtract_32((volatile uint32_t *)p, v);
|
|
}
|
|
|
|
|
|
|
|
#endif /* Arch >= v6 */
|
|
|
|
static __inline int
|
|
atomic_load_32(volatile uint32_t *v)
|
|
{
|
|
|
|
return (*v);
|
|
}
|
|
|
|
static __inline void
|
|
atomic_store_32(volatile uint32_t *dst, uint32_t src)
|
|
{
|
|
*dst = src;
|
|
}
|
|
|
|
static __inline int
|
|
atomic_load_long(volatile u_long *v)
|
|
{
|
|
|
|
return (*v);
|
|
}
|
|
|
|
static __inline void
|
|
atomic_store_long(volatile u_long *dst, u_long src)
|
|
{
|
|
*dst = src;
|
|
}
|
|
|
|
#define atomic_clear_ptr atomic_clear_32
|
|
#define atomic_set_ptr atomic_set_32
|
|
#define atomic_cmpset_ptr atomic_cmpset_32
|
|
#define atomic_cmpset_rel_ptr atomic_cmpset_rel_32
|
|
#define atomic_cmpset_acq_ptr atomic_cmpset_acq_32
|
|
#define atomic_store_ptr atomic_store_32
|
|
#define atomic_store_rel_ptr atomic_store_rel_32
|
|
|
|
#define atomic_add_int atomic_add_32
|
|
#define atomic_add_acq_int atomic_add_acq_32
|
|
#define atomic_add_rel_int atomic_add_rel_32
|
|
#define atomic_subtract_int atomic_subtract_32
|
|
#define atomic_subtract_acq_int atomic_subtract_acq_32
|
|
#define atomic_subtract_rel_int atomic_subtract_rel_32
|
|
#define atomic_clear_int atomic_clear_32
|
|
#define atomic_clear_acq_int atomic_clear_acq_32
|
|
#define atomic_clear_rel_int atomic_clear_rel_32
|
|
#define atomic_set_int atomic_set_32
|
|
#define atomic_set_acq_int atomic_set_acq_32
|
|
#define atomic_set_rel_int atomic_set_rel_32
|
|
#define atomic_cmpset_int atomic_cmpset_32
|
|
#define atomic_cmpset_acq_int atomic_cmpset_acq_32
|
|
#define atomic_cmpset_rel_int atomic_cmpset_rel_32
|
|
#define atomic_fetchadd_int atomic_fetchadd_32
|
|
#define atomic_readandclear_int atomic_readandclear_32
|
|
#define atomic_load_acq_int atomic_load_acq_32
|
|
#define atomic_store_rel_int atomic_store_rel_32
|
|
|
|
#endif /* _MACHINE_ATOMIC_H_ */
|